Mitsubishi M5M5256DVP-70XL, M5M5256DRV-70XL, M5M5256DVP-55XL, M5M5256DVP-55LL, M5M5256DVP-45XL Datasheet
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'97.4.7 MITSUBISHI LSIs
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5256DP,FP,VP,RV is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface.
Especially the M5M5256DVP,RV are packaged in a 28-pin thin small outline package.Two types of devices are available, M5M5256DVP(normal lead bend type package), M5M5256DRV(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.
FEATURE
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Access |
Power supply current |
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Type |
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time |
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Active |
Stand-by |
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(max) |
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(max) |
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M5M5256DP, FP,VP,RV-45LL |
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45ns |
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M5M5256DP, FP,VP,RV-55LL |
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55ns |
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20µA |
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M5M5256DP, FP,VP,RV-70LL |
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70ns |
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(Vcc=5.5V) |
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55mA |
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M5M5256DP, FP,VP,RV-45XL |
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45ns |
(Vcc=5.5V) |
5µA |
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(Vcc=5.5V) |
M5M5256DP, FP,VP,RV-55XL |
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55ns |
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0.05µA |
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70ns |
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(Vcc=3.0V, |
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M5M5256DP, FP,VP,RV-70XL |
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Typical) |
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•Single +5V power supply |
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•No clocks, no refresh |
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•Data-Hold on +2.0V power supply |
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•Directly TTL compatible : all inputs and outputs |
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•Three-state outputs : OR-tie capability |
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•/OE prevents data contention in the I/O bus |
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•Common Data I/O |
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•Battery backup capability |
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•Low stand-by current··········0.05µA(typ.) |
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PACKAGE
M5M256DP |
: 28 pin 600 mil DIP |
M5M5256DFP |
: 28 pin 450 mil SOP |
M5M5256DVP,RV : 28pin 8 X 13.4 mm2 TSOP
APPLICATION
Small capacity memory units
PIN CONFIGURATION (TOP VIEW)
A14 |
1 |
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28 |
Vcc |
A12 |
2 |
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27 |
/W |
A7 |
3 |
M5M5256DP,FP |
26 |
A13 |
A0 |
10 |
19 |
DQ8 |
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A6 |
4 |
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25 |
A8 |
A5 |
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24 |
A9 |
A4 |
6 |
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23 |
A11 |
A3 |
7 |
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22 |
/OE |
A2 |
8 |
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21 |
A10 |
A1 |
9 |
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20 |
/S |
DQ1 |
11 |
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18 |
DQ7 |
DQ2 |
12 |
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17 |
DQ6 |
DQ3 |
13 |
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16 |
DQ5 |
GND |
14 |
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15 |
DQ4 |
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Outline 28P4 (DP) |
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28P2W-C (DFP) |
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A10 |
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22 |
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/OE |
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21 |
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A11 |
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23 |
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/S |
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20 |
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A9 |
DQ8 |
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24 |
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19 |
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25 |
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A8 |
DQ7 |
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18 |
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A13 |
DQ6 |
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26 |
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17 |
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DQ5 |
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27 |
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/W |
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16 |
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28Vcc |
DQ415 |
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A14 M5M5256DVP |
GND |
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1 |
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14 |
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A12 |
DQ313 |
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2 |
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A7 |
DQ212 |
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3 |
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DQ1 |
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A6 |
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4 |
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A0 |
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A5 |
10 |
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5 |
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A1 |
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A4 |
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A2 |
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A3 |
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Outline 28P2C-A (DVP)
7 |
A3 |
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A2 8 |
6 |
A4 |
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A1 9 |
5 |
A5 |
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A0 10 |
4 |
A6 |
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DQ1 11 |
3 |
A7 |
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DQ2 12 |
2 |
A12 |
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DQ3 13 |
1 |
A14 |
M5M5256DRV |
GND 14 |
28 Vcc |
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DQ4 15 |
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27 /W |
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DQ5 16 |
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26 A13 |
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DQ6 17 |
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25 A8 |
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DQ7 18 |
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24 A9 |
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DQ8 19 |
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23 |
A11 |
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/S 20 |
22 /OE |
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A10 21 |
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Outline 28P2C-B (DRV) |
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MITSUBISHI ELECTRIC
1
'97.4.7 MITSUBISHI LSIs
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DP,FP,VP,RV is determined by a combination of the device control inputs /S, /W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W overlaps with the low level /S. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated.
A read cycle is executed by setting /W at a high level and /OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by /S. The power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
/S |
/W |
/OE |
Mode |
DQ |
Icc |
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H |
X |
X |
Non selection |
High-impedance |
Stand-by |
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L |
L |
X |
Write |
DIN |
Active |
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L |
H |
L |
Read |
DOUT |
Active |
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L |
H |
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High-impedance |
Active |
BLOCK DIAGRAM |
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A 8 |
25 |
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11 |
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DQ1 |
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A 13 |
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32768 WORD |
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26 |
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12 |
DQ2 |
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A 14 |
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X 8BIT |
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1 |
INPUTADDRESS |
BUFFER |
DECODERROW |
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ANPLIFIERSENSE |
BUFFEROUTPUT |
18 |
DQ7 |
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13 |
DQ3 |
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A 12 |
2 |
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2 |
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15 |
DQ4 |
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A 7 |
3 |
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16 |
DATA I/O |
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(512 ROWS X |
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DQ5 |
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A 6 |
4 |
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17 |
DQ6 |
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A 5 |
5 |
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512 COLUMNS) |
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A 4 |
6 |
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19 |
DQ8 |
ADDRESS |
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A 3 |
7 |
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INPUT |
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A 2 |
8 |
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A 1 |
9 |
INPUTADDRESS |
BUFFER |
COLUMN |
DECODER |
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INPUTDATA BUFFER |
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A 0 |
10 |
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A 10 |
21 |
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CLOCK |
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A 11 |
23 |
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GENERATOR |
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A 9 |
24 |
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WRITE CONTROL |
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INPUT |
/W |
27 |
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28 |
VCC |
CHIP SELECT |
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(5V) |
/S |
20 |
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INPUT |
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14 |
GND |
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OUTPUT ENABLE |
/OE |
22 |
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(0V) |
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INPUT |
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MITSUBISHI |
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ELECTRIC |
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2
'97.4.7 MITSUBISHI LSIs
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
Vcc |
Supply voltage |
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-0.3*~7.0 |
V |
VI |
Input voltage |
With respect to GND |
-0.3*~Vcc+0.3 |
V |
(Max 7.0) |
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VO |
Output voltage |
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0~Vcc |
V |
Pd |
Power dissipation |
Ta=25°C |
700 |
mW |
Topr |
Operating temperature |
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0~70 |
°C |
Tstg |
Storage temperature |
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-65~150 |
°C |
* -3.0V in case of AC ( Pulse width ≤ 30ns )
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Symbol |
Parameter |
Test conditions |
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Limits |
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Min |
Typ |
Max |
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VIH |
High-level input voltage |
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2.2 |
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Vcc |
V |
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+0.3 |
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VIL |
Low-level input voltage |
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-0.3 |
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0.8 |
V |
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VOH1 |
High-level output voltage 1 |
IOH=-1mA |
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2.4 |
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V |
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VOH2 |
High-level output voltage 2 |
IOH=-0.1mA |
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Vcc |
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V |
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-0.5 |
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VOL |
Low-level output voltage |
IOL=2mA |
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0.4 |
V |
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II |
Input current |
VI=0~Vcc |
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±1 |
uA |
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IO |
Output current in off-state |
/S=VIH or or /OE=VIH, |
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±1 |
uA |
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VI/O=0~Vcc |
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Icc1 |
Active supply current |
/S£0.2V, |
45ns |
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35 |
50 |
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Other inputs<0.2V or >Vcc-0.2V |
55ns |
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30 |
45 |
mA |
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(AC, MOS level ) |
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Output-open Min. cycle |
70ns |
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25 |
40 |
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Active supply current |
/S=VIL, |
45ns |
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35 |
55 |
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Icc2 |
other inputs=VIH or VIL |
55ns |
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30 |
50 |
mA |
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(AC, TTL level ) |
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Output-open Min. cycle |
70ns |
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25 |
45 |
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Icc3 |
Stand-by current |
/S³Vcc-0.2V, |
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-LL |
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20 |
uA |
other inputs=0~Vcc |
-XL |
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0.1 |
5 |
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Icc4 |
Stand-by current |
/S=VIH,other inputs=0~Vcc |
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3 |
mA |
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* -3.0V in case of AC ( Pulse width ≤ 30ns )
CAPACITANCE (Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Symbol |
Parameter |
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Test conditions |
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Limits |
Unit |
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Min |
Typ |
Max |
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CI |
Input capacitance |
I |
I |
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6 |
pF |
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V |
=GND, V =25mVrms, f=1MHz |
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CO |
Output capacitance |
VO=GND,VO=25mVrms, f=1MHz |
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8 |
pF |
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Note 0: Direction for current flowing into an IC is positive (no mark).
1:Typical value is one at Ta = 25°C.
2:CI, CO are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
3
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