Mitsubishi M5M51008DVP-70H, M5M51008DVP-55H, M5M51008DRV-70H, M5M51008DRV-55H, M5M51008DKV-70H Datasheet

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

DESCRIPTION

The M5M51008DP,FP,VP,RV,KV are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM.

They are low standby current and low operation current and ideal for the battery back-up application.

The M5M51008DVP,RV,KV are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD). Two types of devices are available. M5M51008DVP(normal lead bend type package), M5M51008DRV(reverse lead bend type package).Using both types of devices, it becomes very easy to design a printed circuit board.

FEATURES

	Access	Power supply current
Type name
	time	Active	stand-by
	(max)	(1MHz)
			(max)
		(max)
M5M51008DFP,VP,RV,KV-55H	55ns	15mA	20µA
M5M51008DFP,VP,RV,KV-70H	70ns	(1MHz)	(Vcc=5.5V)

Directly TTL compatible : All inputs and outputs

Easy memory expansion and power down by S1,S2

Data hold on +2V power supply

Three-state outputs : OR - tie capability OE prevents data contention in the I/O bus

Common data I/O
Package
M5M51008DFP	············ 32pin	525mil SOP
M5M51008DVP,RV ············ 32pin		8 X 20 mm2	TSOP
M5M51008DKV	············ 32pin	2	TSOP
		8 X 13.4 mm

APPLICATION

Small capacity memory units

PIN CONFIGURATION (TOP VIEW)

								NC					VCC
									1		32							ADDRESS
								A16
									2		31		A15 INPUT
								A14					S2					CHIP SELECT
									3		30							INPUT
								A12										INPUTWRITE CONTROL
									4		29		W
								A7					A13
									5		28
								A6					A8
									6		27							ADDRESS
ADDRESS								A5					A9					INPUTS
									7		26
		INPUTS						A4					A11
									8		25
								A3									INPUTOUTPUT ENABLE
									9		24			OE
								A2					A10 INPUTADDRESS
									10		23
								A1										CHIP SELECT
									11		22		S1					INPUT
								A0					DQ8
									12		21
								DQ1					DQ7
				DATA					13		20
								DQ2					DQ6					DATA
		INPUTS/							14		19							INPUTS/
OUTPUTS								DQ3					DQ5
									15		18							OUTPUTS
								GND					DQ4
									16		17
								Outline 32P2M-A(FP)
		A11
						1													32			OE
		A9																				A10
						2													31
		A8																					1
																						S
						3													30
		A13																				DQ8
						4													29
		W				5													28			DQ7
		S2																				DQ6
						6													27
		A15																				DQ5
						7													26
		VCC							M5M51008DVP,KV													DQ4
						8													25
		NC																				GND
						9													24
		A16																				DQ3
						10													23
		A14																				DQ2
						11													22
		A12																				DQ1
						12													21
		A7																				A0
						13													20
		A6																				A1
						14													19
		A5																				A2
						15													18
		A4																				A3
						16													17
							Outline 32P3H-E(VP), 32P3K-B(KV)
	A4																					A3
						16													17
	A5																					A2
						15													18
	A6																					A1
						14													19
	A7																					A0
						13													20
	A12																					DQ1
						12													21
	A14																					DQ2
						11													22
	A16																					DQ3
						10													23
	NC																					GND
						9				M5M51008DRV									24
	VCC
						8													25			DQ4
	A15																					DQ5
						7													26
	S2																					DQ6
						6													27
																						DQ7
	W					5													28
	A13																					DQ8
						4													29
	A8																							1
						3													30			S
	A9																					A10
						2													31
	A11
						1													32			OE

Outline 32P3H-F(RV)

NC : NO CONNECTION

MITSUBISHI	1
ELECTRIC

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

FUNCTION

The operation mode of the M5M51008D series are determined by a combination of the device control inputs S1,S2,W and OE.

Each mode is summarized in the function table.

A write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated.

A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H).

When setting S1 at a high level or S2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode.

FUNCTION TABLE

S

1

S2

W

OE

Mode

DQ

ICC

X

L

X

X

Non selection

High-impedance

Stand-by

H

X

X

X

Non selection

High-impedance

Stand-by

L

H

L

X

Write

Din

Active

L

H

H

L

Read

Dout

Active

L

H

H

H

High-impedance

Active

	BLOCK DIAGRAM
			*		*
	A3	9	17		21	13	DQ1
					22	14	DQ2
	A2 10		18
				131072 WORDS	23	15	DQ3
	A5	7	15
				X 8 BITS	25	17	DQ4	DATA
	A6	6	14	(512 ROWS
					26	18	DQ5	INPUTS/
	A7	5	13	X128 COLUMNS				OUTPUTS
				X 16BLOCKS)	27	19	DQ6
	A12	4	12
					28	20	DQ7
	A14	3	11
					29	21 DQ8
	A16	2	10
	A15	31	7
	ADDRESS
	INPUTS
	A13	28	4	CLOCK
				GENERATOR
	A8	27
			3
	A9	26	2
	A11	25	1
							WRITE
					5	29	W CONTROL
							INPUT
	A4	8	16		30	22	S1	CHIP
	A1	11	19		6	30	S2	SELECT
	A0							INPUTS
		12	20
								OUTPUT
	A10	23	31		32	24	OE ENABLE
								INPUT
					8	32	VCC
					24	16	GND
							(0V)
	* Pin numbers inside dotted line show those of TSOP

MITSUBISHI	2
ELECTRIC

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Conditions	Ratings	Unit
Vcc	Supply voltage		– 0.3*~7	V
VI	Input voltage	With respect to GND	– 0.3*~Vcc + 0.3	V
VO	Output voltage		0~Vcc	V
Pd	Power dissipation	Ta=25°C	700	mW
Topr	Operating temperature		0~70	°C
Tstg	Storage temperature		– 65~150	°C

* –3.0V in case of AC ( Pulse width ≤ 50ns )

DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)

Symbol

Parameter

Test conditions

Limits

Unit

Min

Typ

Max

VIH

High-level input voltage

2.2

Vcc + 0.3

V

VIL

Low-level input voltage

–0.3*

0.8

V

VOH

High-level output voltage

IOH= –1.0mA

2.4

V

IOH= –0.1mA

Vcc – 0.5

V

VOL

Low-level output voltage

IOL=2mA

0.4

V

II

Input current

VI=0~Vcc

±1

µA

1=VIH or S2=VIL or

IO

Output current in off-state

S

OE=VIH

±1

µA

VI/O=0~VCC

55ns

39

80

Active supply current

S1 £ 0.2V, S2 ³ VCC–0.2V

mA

ICC1

(AC, MOS level)

other inputs £ 0.2V or ³ VCC–0.2V

70ns

34

70

Output-open(duty 100%)

1MHz

4

15

55ns

42

85

ICC2

Active supply current

S1=VIL,S2=VIH,

mA

other inputs=VIH or VIL

70ns

37

70

(AC, TTL level)

Output-open(duty 100%)

1MHz

5

15

1) S2 £ 0.2V,

~25°C

2

other inputs=0~VCC

ICC3

Stand-by current

2) S1

³

VCC–0.2V,

-H

~40°C

6

µA

S2

³

VCC–0.2V,

~70°C

20

other inputs=0~VCC

1=VIH or S2=VIL,

ICC4

Stand-by current

S

3

mA

other inputs=0~VCC

* –3.0V in case of AC ( Pulse width ≤ 50ns )

CAPACITANCE (Ta=0~70°C, Vcc=5V±10% unless otherwise noted)

Symbol	Parameter		Test conditions		Limits		Unit
				Min	Typ	Max
CI	Input capacitance	FP,VP,RV,KV	VI=GND, VI=25mVrms, f=1MHz			8	pF
CO	Output capacitance	FP,VP,RV,KV	VO=GND,VO=25mVrms, f=1MHz			10	pF

Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc = 5V, Ta = 25°C

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ELECTRIC