Mitsubishi M5M4V64S40ATP-8L, M5M4V64S40ATP-8A, M5M4V64S40ATP-8, M5M4V64S40ATP-10L, M5M4V64S40ATP-10 Datasheet

	SDRAM (Rev.1.3)	MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

Some of contents are subject to change without notice.

	DESCRIPTION	PIN CONFIGURATION
		(TOP VIEW)

The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit

Synchronous DRAM, with LVTTL interface. All inputs and	Vdd
	DQ0
outputs are referenced to the rising edge of CLK. The	VddQ
	DQ1
M5M4V64S40ATP achieves very high speed data rate up to
	DQ2
125MHz, and is suitable for main memory or graphic memory	VssQ
	DQ3
in computer systems.	DQ4
	VddQ
	DQ5
FEATURES	DQ6
	VssQ
	DQ7

-Single 3.3v±0.3v power supply

-Clock frequency 125MHz /100MHz

-Fully synchronous operation referenced to clock rising edge

-4 bank operation controlled by BA0, BA1 (Bank Address)

-/CAS latency- 2/3 (programmable)

-Burst length- 1/2/4/8/Full Page (programmable)

-Burst typesequential / interleave (programmable)

-Column access - random

-Burst Write / Single Write (programmable)

-Auto precharge / All bank precharge controlled by A10

-Auto refresh and Self refresh

-4096 refresh cycles /64ms

-Column address A0-A7

-LVTTL Interface

-400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch

	Max.	CLK Access
	Frequency	Time
M5M4V64S40ATP-8A	125MHz	6ns
M5M4V64S40ATP-8	100MHz	6ns
M5M4V64S40ATP-10	100MHz	8ns

Vdd DQML /WE /CAS /RAS /CS

BA0(A13) BA1(A12) A10 A0 A1 A2

A3

Vdd

CLK

CKE /CS /RAS /CAS /WE DQ0-15 DQML/U A0-11 BA0,1 Vdd VddQ Vss VssQ

	1		54	Vss
	2		53	DQ15
	3		52	VssQ
	4		51	DQ14
	5		50	DQ13
	6		49	VddQ
	7	TSOP(II)	48	DQ12
	8		47	DQ11
	9		46	VssQ
	10		45	DQ10
	11		44	DQ9
	12		43	VddQ
	13	54pin	42	DQ8
	16		39	DQMU
	14		41	Vss
	15		40	NC (Vref)
	17	400mil	38	CLK
	18		37	CKE
	19		36	NC
	20		35	A11
	21		34	A9
	22		33	A8
	23		32	A7
	24		31	A6
	25		30	A5
	26		29	A4
	27		28	Vss

:Master Clock

:Clock Enable

:Chip Select

:Row Address Strobe

:Column Address Strobe

:Write Enable

:Data I/O

:Output Disable/ Write Mask

:Address Input

:Bank Address

:Power Supply

:Power Supply for Output

:Ground

:Ground for Output

MITSUBISHI ELECTRIC	1

MITSUBISHI LSIs

SDRAM (Rev.1.3)

Mar'98	M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
BLOCK DIAGRAM		DQ0-15
		I/O Buffer
Memory Array Memory Array Memory Array Memory Array
Bank #0	Bank #1		Bank #2	Bank #3
Mode
Register
	Control Circuitry
Address Buffer			Control Signal Buffer
A0-11 BA0,1	Clock Buffer		/CS /RAS /CAS /WE DQM
	CLK	CKE

Type Designation Code

This rule is applied to only Synchronous DRAM family.

M 5M 4 V 64 S 4 0 A TP - 8

Access Item

Package Type TP: TSOP(II)

Process Generation

Function 0: Random Column, 1: 2N-rule

Organization 2n 2: x4, 3: x8, 4: x16

Synchronous DRAM

Density 64:64M bits

Interface S: SSTL, V:LVTTL

Memory Style (DRAM)

Use, Recommended Operating Conditions, etc

Mitsubishi Main Designation

MITSUBISHI ELECTRIC	2

	SDRAM (Rev.1.3)		MITSUBISHI LSIs
			M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
PIN FUNCTION
	CLK	Input	Master Clock: All other inputs are referenced to the rising edge of CLK.
			Clock Enable: CKE controls internal clock. When CKE is low, internal clock
	CKE	Input	for the following cycle is ceased. CKE is also used to select auto / self
			refresh. After self refresh mode is started, CKE becomes asynchronous
			input. Self refresh is maintained as long as CKE is low.
	/CS	Input	Chip Select: When /CS is high, any command means No Operation.
	/RAS, /CAS, /WE	Input	Combination of /RAS, /CAS, /WE defines basic commands.
			A0-11 specify the Row / Column Address in conjunction with BA0,1. The
			Row Address is specified by A0-11. The Column Address is specified by
	A0-11	Input	A0-7 . A10 is also used to indicate precharge option. When
			A10 is high at a read / write command, an auto precharge is performed.
			When A10 is high at a precharge command, all banks are precharged.
	BA0,1	Input	Bank Address: BA0,1 specifies one of four banks to which a command is
			applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
	DQ0-15	Input / Output	Data In and Data out are referenced to the rising edge of CLK.
			Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the
	DQMU/L	Input	current cycle is masked. When DQMU/L is high in burst read,
			Dout is disabled at the next but one cycle.
	Vdd, Vss	Power Supply	Power Supply for the memory array and peripheral circuitry.
	VddQ, VssQ	Power Supply	VddQ and VssQ are supplied to the Output Buffers only.

MITSUBISHI ELECTRIC

3

	SDRAM (Rev.1.3)	MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

BASIC FUNCTIONS

The M5M4V64S40ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh.

Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively.

To know the detailed definition of commands, please see the command truth table.

CLK

/CS				Chip Select : L=select, H=deselect
				Command
/RAS
				Command
/CAS					define basic commands
				Command
/WE
				Refresh Option @refresh command
CKE
				Precharge Option @precharge or read/write command
A10

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge,

READA).

Write (WRITE) [/RAS =H, /CAS =/WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (autoprecharge, WRITEA).

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated (precharge all, PREA).

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]

REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.

MITSUBISHI ELECTRIC

4

	SDRAM (Rev.1.3)	MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

COMMAND TRUTH TABLE

COMMAND

MNEMONIC

CKE

CKE

/CS

/RAS

/CAS

/WE

BA0,1

A11

A10

A0-9

n-1

n

Deselect

DESEL

H

X

H

X

X

X

X

X

X

X

No Operation

NOP

H

X

L

H

H

H

X

X

X

X

Row Address Entry &

ACT

H

X

L

L

H

H

V

V

V

V

Bank Activate

Single Bank Precharge

PRE

H

X

L

L

H

L

V

X

L

X

Precharge All Banks

PREA

H

X

L

L

H

L

X

X

H

X

Column Address Entry

WRITE

H

X

L

H

L

L

V

X

L

V

& Write

Column Address Entry

& Write with Auto-

WRITEA

H

X

L

H

L

L

V

X

H

V

Precharge

Column Address Entry

READ

H

X

L

H

L

H

V

X

L

V

& Read

Column Address Entry

& Read with Auto-

READA

H

X

L

H

L

H

V

X

H

V

Precharge

Auto-Refresh

REFA

H

H

L

L

L

H

X

X

X

X

Self-Refresh Entry

REFS

H

L

L

L

L

H

X

X

X

X

Self-Refresh Exit

REFSX

L

H

H

X

X

X

X

X

X

X

L

H

L

H

H

H

X

X

X

X

Burst Terminate

TBST

H

X

L

H

H

L

X

X

X

X

Mode Register Set

MRS

H

X

L

L

L

L

L

L

L

V*1

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1. A7-A9 =0, A0-A6 =Mode Address

MITSUBISHI ELECTRIC	5

SDRAM (Rev.1.3)									MITSUBISHI LSIs
						M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
			64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE
	Current State	/CS	/RAS	/CAS		/WE	Address	Command	Action
	IDLE	H	X	X		X	X	DESEL	NOP
		L	H	H		H	X	NOP	NOP
		L	H	H		L	BA	TBST	ILLEGAL*2
		L	H	L		X	BA, CA, A10	READ / WRITE	ILLEGAL*2
		L	L	H		H	BA, RA	ACT	Bank Active, Latch RA
		L	L	H		L	BA, A10	PRE / PREA	NOP*4
		L	L	L		H	X	REFA	Auto-Refresh*5
		L	L	L		L	Op-Code,	MRS	Mode Register Set*5
							Mode-Add
	ROW ACTIVE	H	X	X		X	X	DESEL	NOP
		L	H	H		H	X	NOP	NOP
		L	H	H		L	BA	TBST	NOP
		L	H	L		H	BA, CA, A10	READ / READA	Begin Read, Latch CA,
									Determine Auto-Precharge
		L	H	L		L	BA, CA, A10	WRITE /	Begin Write, Latch CA,
								WRITEA	Determine Auto-Precharge
		L	L	H		H	BA, RA	ACT	Bank Active / ILLEGAL*2
		L	L	H		L	BA, A10	PRE / PREA	Precharge / Precharge All
		L	L	L		H	X	REFA	ILLEGAL
		L	L	L		L	Op-Code,	MRS	ILLEGAL
							Mode-Add
	READ	H	X	X		X	X	DESEL	NOP (Continue Burst to END)
		L	H	H		H	X	NOP	NOP (Continue Burst to END)
		L	H	H		L	BA	TBST	Terminate Burst
									Terminate Burst, Latch CA,
		L	H	L		H	BA, CA, A10	READ / READA	Begin New Read, Determine
									Auto-Precharge*3
								WRITE /	Terminate Burst, Latch CA,
		L	H	L		L	BA, CA, A10		Begin Write, Determine Auto-
								WRITEA
									Precharge*3
		L	L	H		H	BA, RA	ACT	Bank Active / ILLEGAL*2
		L	L	H		L	BA, A10	PRE / PREA	Terminate Burst, Precharge
		L	L	L		H	X	REFA	ILLEGAL
		L	L	L		L	Op-Code,	MRS	ILLEGAL
							Mode-Add
						MITSUBISHI ELECTRIC			6

SDRAM (Rev.1.3)								MITSUBISHI LSIs
					M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
			64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
	Current State	/CS	/RAS	/CAS	/WE	Address	Command	Action
	WRITE	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
		L	H	H	H	X	NOP	NOP (Continue Burst to END)
		L	H	H	L	BA	TBST	Terminate Burst
								Terminate Burst, Latch CA,
		L	H	L	H	BA, CA, A10	READ / READA	Begin Read, Determine Auto-
								Precharge*3
							WRITE /	Terminate Burst, Latch CA,
		L	H	L	L	BA, CA, A10		Begin Write, Determine Auto-
							WRITEA
								Precharge*3
		L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
		L	L	H	L	BA, A10	PRE / PREA	Terminate Burst, Precharge
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
	READ with	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
	AUTO	L	H	H	H	X	NOP	NOP (Continue Burst to END)
	PRECHARGE
		L	H	H	L	BA	TBST	ILLEGAL
		L	H	L	H	BA, CA, A10	READ / READA	ILLEGAL
		L	H	L	L	BA, CA, A10	WRITE /	ILLEGAL
							WRITEA
		L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
		L	L	H	L	BA, A10	PRE / PREA	ILLEGAL*2
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
	WRITE with	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
	AUTO	L	H	H	H	X	NOP	NOP (Continue Burst to END)
	PRECHARGE
		L	H	H	L	BA	TBST	ILLEGAL
		L	H	L	H	BA, CA, A10	READ / READA	ILLEGAL
		L	H	L	L	BA, CA, A10	WRITE /	ILLEGAL
							WRITEA
		L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
		L	L	H	L	BA, A10	PRE / PREA	ILLEGAL*2
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
					MITSUBISHI ELECTRIC			7

	SDRAM (Rev.1.3)							MITSUBISHI LSIs
					M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
			64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
	Current State	/CS	/RAS	/CAS	/WE	Address	Command	Action
	PRE -	H	X	X	X	X	DESEL	NOP (Idle after tRP)
	CHARGING	L	H	H	H	X	NOP	NOP (Idle after tRP)
		L	H	H	L	BA	TBST	ILLEGAL*2
		L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL*2
		L	L	H	H	BA, RA	ACT	ILLEGAL*2
		L	L	H	L	BA, A10	PRE / PREA	NOP*4 (Idle after tRP)
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
	ROW	H	X	X	X	X	DESEL	NOP (Row Active after tRCD)
	ACTIVATING	L	H	H	H	X	NOP	NOP (Row Active after tRCD)
		L	H	H	L	BA	TBST	ILLEGAL*2
		L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL*2
		L	L	H	H	BA, RA	ACT	ILLEGAL*2
		L	L	H	L	BA, A10	PRE / PREA	ILLEGAL*2
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
	WRITE RE-	H	X	X	X	X	DESEL	NOP
	COVERING	L	H	H	H	X	NOP	NOP
		L	H	H	L	BA	TBST	ILLEGAL*2
		L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL*2
		L	L	H	H	BA, RA	ACT	ILLEGAL*2
		L	L	H	L	BA, A10	PRE / PREA	ILLEGAL*2
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add

MITSUBISHI ELECTRIC

8

	SDRAM (Rev.1.3)									MITSUBISHI LSIs
							M5M4V64S40ATP-8A,-8L,-8, -10L, -10
		Mar'98
					64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
	FUNCTION TRUTH TABLE(continued)
		Current State		/CS	/RAS	/CAS	/WE	Address	Command	Action
		RE-		H	X	X	X	X	DESEL	NOP (Idle after tRC)
		FRESHING		L	H	H	H	X	NOP	NOP (Idle after tRC)
				L	H	H	L	BA	TBST	ILLEGAL
				L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL
				L	L	H	H	BA, RA	ACT	ILLEGAL
				L	L	H	L	BA, A10	PRE / PREA	ILLEGAL
				L	L	L	H	X	REFA	ILLEGAL
				L	L	L	L	Op-Code,	MRS	ILLEGAL
								Mode-Add
		MODE		H	X	X	X	X	DESEL	NOP (Idle after tRSC)
		REGISTER		L	H	H	H	X	NOP	NOP (Idle after tRSC)
		SETTING		L	H	H	L	BA	TBST	ILLEGAL
				L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL
				L	L	H	H	BA, RA	ACT	ILLEGAL
				L	L	H	L	BA, A10	PRE / PREA	ILLEGAL
				L	L	L	H	X	REFA	ILLEGAL
				L	L	L	L	Op-Code,	MRS	ILLEGAL
								Mode-Add
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration

NOTES:

1.All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2.ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

3.Must satisfy bus contention, bus turn around, write recovery requirements.

4.NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5.ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

MITSUBISHI ELECTRIC	9

SDRAM (Rev.1.3)

MITSUBISHI LSIs

M5M4V64S40ATP-8A,-8L,-8, -10L, -10

Mar'98

64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

FUNCTION TRUTH TABLE for CKE

Current State

CKE

CKE

/CS

/RAS

/CAS

/WE

Add

Action

n-1

n

SELF-

H

X

X

X

X

X

X

INVALID

REFRESH*1

L

H

H

X

X

X

X

Exit Self-Refresh (Idle after tRC)

L

H

L

H

H

H

X

Exit Self-Refresh (Idle after tRC)

L

H

L

H

H

L

X

ILLEGAL

L

H

L

H

L

X

X

ILLEGAL

L

H

L

L

X

X

X

ILLEGAL

L

L

X

X

X

X

X

NOP (Maintain Self-Refresh)

POWER

H

X

X

X

X

X

X

INVALID

DOWN

L

H

X

X

X

X

X

Exit Power Down to Idle

L

L

X

X

X

X

X

NOP (Maintain Self-Refresh)

ALL BANKS

H

H

X

X

X

X

X

Refer to Function Truth Table

IDLE*2

H

L

L

L

L

H

X

Enter Self-Refresh

H

L

H

X

X

X

X

Enter Power Down

H

L

L

H

H

H

X

Enter Power Down

H

L

L

H

H

L

X

ILLEGAL

H

L

L

H

L

X

X

ILLEGAL

H

L

L

L

X

X

X

ILLEGAL

L

X

X

X

X

X

X

Refer to Current State =Power Down

ANY STATE

H

H

X

X

X

X

X

Refer to Function Truth Table

other than

H

L

X

X

X

X

X

Begin CLK Suspend at Next Cycle*3

listed above

L

H

X

X

X

X

X

Exit CLK Suspend at Next Cycle*3

L

L

X

X

X

X

X

Maintain CLK Suspend

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

NOTES:

1.CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

2.Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

3.Must be legal command.

MITSUBISHI ELECTRIC

10

	SDRAM (Rev.1.3)	MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

SIMPLIFIED STATE DIAGRAM

SELF

REFRESH

REFS

REFSX

		MODE	MRS			REFA	AUTO
		REGISTER		IDLE
							REFRESH
		SET
						CKEL
		CLK			CKEH
		SUSPEND		ACT
							POWER
				CKEL			DOWN
			CKEH
		TBST (for Full Page)		ROW		TBST (for Full Page)
				ACTIVE
			WRITE			READ
		CKEL		WRITEA	READA		CKEL
	WRITE			READ
		WRITE				READ
	SUSPEND			WRITE
		CKEH					CKEH
		WRITEA					READA
			WRITEA		READA
	WRITEA	CKEL					CKEL
		WRITEA		PRE		READA
	SUSPEND
		CKEH					CKEH
				PRE	PRE

READ

SUSPEND

READA

SUSPEND

POWER
APPLIED	POWER	PRE	PRE
	ON		CHARGE

Automatic Sequence

Command Sequence

MITSUBISHI ELECTRIC

11

	SDRAM (Rev.1.3)	MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM

from damaged or malfunctioning.

1.Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.

2.Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.

3.Issue precharge commands for all banks. (PRE or PREA)

4.After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5.Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be programmed by	CLK
setting the mode register (MRS). The mode register stores these data	/CS
until the next MRS command, which may be issued when both banks
are inÅ@idle state. After tRSC from a MRS command, the SDRAM is	/RAS

ready for new command.

/CAS

/WE BA0,1 A11-A0

V

BA0

BA1

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

0

0

0

0

WM

0

0

LTMODE

BT

BL

					BL	BT= 0		BT= 1
	CL	/CAS LATENCY
					0 0 0	1		1
	0 0 0	R
	0 0 1	R			0 0 1	2		2
LATENCY	0 1 0	2		BURST	0 1 0	4		4
	0 1 1	3			0 1 1	8		8
MODE				LENGTH
					1 0 0	R		R
	1 0 0	R
					1 0 1	R		R
	1 0 1	R
					1 1 0	R		R
	1 1 0	R
	1 1 1	R			1 1 1	FP		R
WRITE	0	BURST		BURST	0	SEQUENTIAL
MODE	1	SINGLE BIT		TYPE	1	INTERLEAVED

R: Reserved for Future Use

FP: Full Page

MITSUBISHI ELECTRIC	12

	SDRAM (Rev.1.3)							MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
	CLK
	Command	Read				Write
	Address	Y				Y
	DQ	Q0	Q1	Q2	Q3	D0	D1	D2	D3
	CL= 3	/CAS Latency	Burst Length				Burst Length
	BL= 4
					Burst Type

Initial Address			BL								Column Addressing
A2	A1	A0					Sequential									Interleaved
0	0	0		0	1	2	3	4		5	6	7	0	1	2		3	4		5	6	7
0	0	1		1	2	3	4	5		6	7	0	1	0	3		2	5		4	7	6
0	1	0		2	3	4	5	6		7	0	1	2	3	0		1	6		7	4	5
0	1	1	8	3	4	5	6	7		0	1	2	3	2	1		0	7		6	5	4
1	0	0		4	5	6	7	0		1	2	3	4	5	6		7	0		1	2	3
1	0	1		5	6	7	0	1		2	3	4	5	4	7		6	1		0	3	2
1	1	0		6	7	0	1	2		3	4	5	6	7	4		5	2		3	0	1
1	1	1		7	0	1	2	3		4	5	6	7	6	5		4	3		2	1	0
-	0	0		0	1	2	3						0	1	2		3
-	0	1	4	1	2	3	0						1	0	3		2
-	1	0		2	3	0	1						2	3	0		1
-	1	1		3	0	1	2						3	2	1		0
-	-	0	2	0	1								0	1
-	-	1		1	0								1	0

MITSUBISHI ELECTRIC	13

	SDRAM (Rev.1.3)	MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

[ /CAS LATENCY ]

/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the speed of CLK determines which CL should be used. First output data is available after CL cycles from READ command.

/CAS Latency Timing(BL=4)

CLK
Command	ACT	READ
		tRCD
Address	X	Y
DQ		CL=2	Q2	Q3
		Q0 Q1			CL=2
DQ		CL=3	Q1	Q2 Q3
		Q0			CL=3

[ BURST LENGTH ]

The burst length, BL, determines the number of consecutive writes or reads that will be automatically

performed after the initial write or read command. For BL=1,2,4,8, the output data is tristated (Hi-Z)

after the last read. For BL=FP (Full Page), the TBST (Burst Terminate) command must be used to stop the output of data.

Burst Length Timing( CL=2 )

tRCD

CLK

Command

ACT

READ

Address

X

Y

DQ

Q0

BL=1

DQ

Q0

Q1

BL=2

DQ

Q0

Q1

Q2

Q3

BL=4

DQ

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

BL=8

DQ

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Qm Q0 Q1

BL=FP

M5M4V64S20A : m=1023 M5M4V64S30A : m=511 M5M4V64S40A : m=255

Full Page counter rolls over and continues to count.

14

MITSUBISHI ELECTRIC

	SDRAM (Rev.1.3)	MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM

OPERATIONAL DESCRIPTION

BANK ACTIVATE

The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A11-0. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC, although the number of banks which are active concurrently is not limited.

PRECHARGE

The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued.

Bank Activation and Precharge All (BL=4, CL=3)

CLK

2 ACT command / tRCmin

				tRCmin
Command	ACT	ACT	READ	PRE	ACT
		tRRD		tRAS	tRP
A0-9	Xa	Xb	Y		Xb
		tRCD
A10	Xa	Xb	0	1	Xb
A11	Xa	Xb			Xb
BA0,1	00	01	00		01

DQ Qa0 Qa1 Qa2 Qa3

Precharge all

READ

After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A7-0(X16), and the address sequence of burst data is defined by the

Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA.

MITSUBISHI ELECTRIC

15

	SDRAM (Rev.1.3)	MITSUBISHI LSIs
		M5M4V64S40ATP-8A,-8L,-8, -10L, -10
	Mar'98
		64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
		Multi Bank Interleaving READ (BL=4, CL=3)

CLK

Command	ACT	READ ACT		READ	PRE
		tRCD
A0-9	Xa	Y	Xb	Y
A10	Xa	0	Xb	0	0
A11	Xa		Xb
BA0,1	00	00	10	10	00
DQ			Qa0	Qa1	Qa2 Qa3 Qb0 Qb1 Qb2
			/CAS latency	Burst Length

READ with Auto-Precharge (BL=4, CL=3)

CLK

			BL + tRP
Command	ACT	READ		ACT
		tRCD	BL	tRP
A0-9	Xa	Y		Xa
A10	Xa	1		Xa
A11	Xa			Xa
BA0,1	00	00		00
DQ			Qa0 Qa1	Qa2 Qa3

Internal precharge start

READ Auto-Precharge Timing (BL=4)

CLK

Command		ACT	READ
			BL
CL=3	DQ		Qa0	Qa1	Qa2 Qa3
CL=2	DQ		Qa0 Qa1	Qa2	Qa3
			Internal Precharge Start Timing
			MITSUBISHI ELECTRIC		16