TEXAS INSTRUMENTS CD54HC540F3A, CD54HC541F3A, CD54HCT541F3A, CD74HC540E, CD74HC540M Technical data

Data sheet acquired from Harris Semiconductor SCHS189C

January 1998 - Revised July 2004

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

High-Speed CMOS Logic

Octal Buffer and Line Drivers, Three-State

[ /Title (CD74 HC540

,

CD74

HCT54

0,

CD74

HC541

,

CD74

HCT54

Features

• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting

• ’HC541, ’HCT541 . . . . . . . . . . . . . . . . . . . . . . Non-Inverting

•Buffered Inputs

•Three-State Outputs

•Bus Line Driving Capability

•Typical Propagation Delay = 9ns at VCC = 5V, CL = 15pF, TA = 25oC

•Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

•Balanced Propagation Delay and Transition Times

•Significant Power Reduction Compared to LSTTL Logic ICs

•HC Types

-2V to 6V Operation

-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

•HCT Types

-4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)

-CMOS Input Compatibility, Il ≤ 1 A at VOL, VOH

Description

The ’HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are NonInverting Octal Buffers and Line Drivers with Three-State Outputs that can drive 15 LSTTL loads. The Output Enables (OE1) and (OE2) control the Three-State Outputs. If either OE1 or OE2 is HIGH the outputs will be in the high impedance state. For data output OE1 and OE2 both must be LOW.

Ordering Information

	TEMP. RANGE
PART NUMBER	(oC)	PACKAGE
CD54HC540F3A	-55 to 125	20 Ld CERDIP
CD54HC541F3A	-55 to 125	20 Ld CERDIP
CD54HCT541F3A	-55 to 125	20 Ld CERDIP
CD74HC540E	-55 to 125	20 Ld PDIP
CD74HC540M	-55 to 125	20 Ld SOIC
CD74HC540M96	-55 to 125	20 Ld SOIC
CD74HC541E	-55 to 125	20 Ld PDIP
CD74HC541M	-55 to 125	20 Ld SOIC
CD74HC541M96	-55 to 125	20 Ld SOIC
CD74HC541PW	-55 to 125	20 Ld TSSOP
CD74HC541PWR	-55 to 125	20 Ld TSSOP
CD74HCT540E	-55 to 125	20 Ld PDIP
CD74HCT540M	-55 to 125	20 Ld SOIC
CD74HCT540M96	-55 to 125	20 Ld SOIC
CD74HCT541E	-55 to 125	20 Ld PDIP
CD74HCT541M	-55 to 125	20 Ld SOIC
CD74HCT541M96	-55 to 125	20 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright © 2004, Texas Instruments Incorporated

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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Pinouts

CD54HC540

(CERDIP) CD74HC540, CD74HCT540

(PDIP, SOIC)

TOP VIEW

OE

1

20 VCC

A0

2

19 OE2

A1

3

18

Y0

A2

4

17

Y1

A3

5

16

Y2

A4

6

15

Y3

A5

7

14

Y4

A6

8

13

Y5

A7

9

12

Y6

GND

10

11 Y7

CD54HC541, CD54HCT541 (CERDIP)

CD74HC541

(PDIP, SOIC, TSSOP)

CD74HCT541

(PDIP, SOIC)

TOP VIEW

OE1

1

20 VCC

A0

2

19 OE2

A1	3	18	Y0
A2	4	17	Y1
A3	5	16	Y2

A4	6	15	Y3
A5	7	14	Y4
A6	8	13	Y5
A7	9	12	Y6

GND

10

11 Y7

Functional Diagram

OEA	OEB
	540	541
D0	Y0	Y0
D1	Y1	Y1
D2	Y2	Y2
D3	Y3	Y3
D4	Y4	Y4
D5	Y5	Y5
D6	Y6	Y6
D7	Y7	Y7

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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

TRUTH TABLE

			INPUTS					OUTPUTS
						An	540		541
	OE1			OE2
	L			L		H	L		H
	H			X		X	Z		Z
	X			H		X	Z		Z
	L			L		L	H		L

H = HIGH Voltage Level

L = LOW Voltage Level

X= Don’t Care

Z = High Impedance

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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 7V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±20mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Drain Current, per Output, IO	±35mA
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±25mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . .	. . . .±50mA

Thermal Information

Thermal Resistance (Typical, Note 1) θ JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS		VCC
PARAMETER	SYMBOL	VI (V)	IO (mA)	(V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
HC TYPES
High Level Input	VIH	-	-	2	1.5	-	-	1.5	-	1.5	-	V
Voltage
				4.5	3.15	-	-	3.15	-	3.15	-	V
				6	4.2	-	-	4.2	-	4.2	-	V
Low Level Input	VIL	-	-	2	-	-	0.5	-	0.5	-	0.5	V
Voltage
				4.5	-	-	1.35	-	1.35	-	1.35	V
				6	-	-	1.8	-	1.8	-	1.8	V
High Level Output	VOH	VIH or VIL	-0.02	2	1.9	-	-	1.9	-	1.9	-	V
Voltage
			-0.02	4.5	4.4	-	-	4.4	-	4.4	-	V
CMOS Loads
			-0.02	6	5.9	-	-	5.9	-	5.9	-	V
High Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			-6	4.5	3.98	-	-	3.84	-	3.7	-	V
TTL Loads
			-7.8	6	5.48	-	-	5.34	-	5.2	-	V
Low Level Output	VOL	VIH or VIL	0.02	2	-	-	0.1	-	0.1	-	0.1	V
Voltage
			0.02	4.5	-	-	0.1	-	0.1	-	0.1	V
CMOS Loads
			0.02	6	-	-	0.1	-	0.1	-	0.1	V
Low Level Output			-	-	-	-	-	-	-	-	-	V
Voltage
			6	4.5	-	-	0.26	-	0.33	-	0.4	V
TTL Loads
			7.8	6	-	-	0.26	-	0.33	-	0.4	V
Input Leakage	II	VCC or	-	6	-	-	±0.1	-	±1	-	±1	µA
Current		GND

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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

DC Electrical Specifications (Continued)

		TEST				25oC		-40oC TO 85oC		-55oC TO 125oC
		CONDITIONS		VCC
PARAMETER	SYMBOL	VI (V)	IO (mA)	(V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNITS
Quiescent Device	ICC	VCC or	0	6	-	-	8	-	80	-	160	A
Current		GND
ThreeState Leakage	IOZ	VIL or VIH	VO =	6	-	-	±0.5	-	±5.0	-	±10	A
Current			VCC or
			GND
HCT TYPES
High Level Input	VIH	-	-	4.5 to	2	-	-	2	-	2	-	V
Voltage				5.5
Low Level Input	VIL	-	-	4.5 to	-	-	0.8	-	0.8	-	0.8	V
Voltage				5.5
High Level Output	VOH	VIH or VIL	-0.02	4.5	4.4	-	-	4.4	-	4.4	-	V
Voltage
CMOS Loads
High Level Output			-6	4.5	3.98	-	-	3.84	-	3.7	-	V
Voltage
TTL Loads
Low Level Output	VOL	VIH or VIL	0.02	4.5	-	-	0.1	-	0.1	-	0.1	V
Voltage
CMOS Loads
Low Level Output			6	4.5	-	-	0.26	-	0.33	-	0.4	V
Voltage
TTL Loads
Input Leakage	II	VCC and	0	5.5	-		±0.1	-	±1	-	±1	A
Current		GND
Quiescent Device	ICC	VCC or	0	5.5	-	-	8	-	80	-	160	A
Current		GND
ThreeState Leakage	IOZ	VIL or VIH	VO =	5.5	-	-	±0.5	-	±5.0	-	±10	A
Current			VCC or
			GND
Additional Quiescent	∆ ICC	VCC	-	4.5 to	-	100	360	-	450	-	490	A
Device Current Per	(Note 2)	-2.1		5.5
Input Pin: 1 Unit Load
NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

				UNIT LOADS
INPUT			HCT540		HCT541
A0 - A7			1		0.4
			0.75		0.75
	OE2
			1.15		1.15
	OE1

NOTE: Unit Load is ∆ ICC limit specific in DC Electrical Specifications

Table, e.g., 360 A max. at 25oC.

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