DYNEX MAS28151LS, MAS28151LE, MAS28151LD, MAS28151LC, MAS28151LB Datasheet

MA28151

Radiation hard Programmable

Communication Interface

Replaces Jone 1999 version, DS3574-4.0

DS3574-5.0 January 2000

The MA28151 is based on the industry standard 8251A Universal Synchronous Asynchronous Receiver/Transmitter (USART), modified for data communications with the MAS281 microprocessor.

The MA28151 is used as a peripheral device and is programmed by the CPU to operate using virtually any serial data transmission technique presently in use (including IBM “bi-sync”). The USART accepts data characters from the CPU in parallel format and then converts them into a continuous serial data stream for transmission.

Simultaneously, it can receive serial data streams and convert them into parallel data characters for the CPU. The USART signals the CPU whenever it receives a character for transmission or whenever it receives a character for the CPU. The CPU can read the complete status of the USART at any time, including data transmission errors and control signals such as SYNDET and TxEMPTY.

FEATURES

■Radiation Hard to 1MRad(Si)

■Latch Up Free, High SEU Immunity

■Silicon-on-Sapphire Technology

■Synchronous 5 - 8 Bit Characters; Internal or External Character Synchronisation; Automatic Sync Insertion

■Asynchronous 5 - 8 Bit Characters; Clock Rate - 1, 16 or 64 Times Baud Rate; Break Character Generation, 1 1⁄2 or 2 Stop Bits

■All Inputs and Outputs are TTL Compatible

■Compatible with the MAS281 (MIL-STD-1750A) Microprocessor

The MA28151 is based on the industry standard 8251A USART, modified for use with the MAS281 processor, incorporating the following features:

1.MA28151 has double-buffered data paths with separate l/O registers for control status, data in and data out, which considerably simplifies control programming and minimizes CPU overhead.

2.In synchronous operations, the Receiver detects and handles “break” automatically, relieving the CPU of this task.

3.A refined Rx initialisation prevents the Receiver from starting when in the “break” state, preventing unwanted interrupts from the disconnected USART.

4.At the conclusion of a transmission, the TxD line will always return to the marking state unless SBRK is programmed.

5.Tx Enable logic enhancement prevents a Tx Disable command from prematurely halting transmission of the previously written data before completion. The logic also

Figure 1: MA28151 Block Diagram

prevents the transmitter from turning off in the middle of a word.

6.When external Sync Detect is programmed, Internal Sync Detect is disabled and an External Sync Detect status is provided via a flip-flop, which clears itself upon a status read.

7.The possibility of a false sync detect is minimized in two ways: by ensuring that if double character sync is programmed, the characters will be continuously detected and by clearing the Rx register to all 1’s whenever Enter-Hunt command is issued in Sync mode.

8.When the MA28151 is not selected, the RDWN and DSN lines do not affect the internal operation of the device.

9.The MA28151 Status can be read at any time but the status update will be inhibited during status read.

10.The MA28151 is free from extraneous glitches, providing higher speed and better operating margins.

11.Synchronous Baud rate is from DC to 64K.

12.Asynchronous Baud rate is from DC to 19.2K.

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MA28151

1. FUNCTIONAL DESCRIPTION

1.1 GENERAL

The MA28151 is a Universal Synchronous/Asynchronous Receiver/Transmitter designed for use with the MAS281 microprocessor. Like other l/O devices in a microcomputer system, its functional configuration is programmed by the system’s software for maximum flexibility. The MA28151 can support most serial data techniques in use, including IBM bisync.

In a communication environment, an interface device must convert parallel format system data into serial format for transmission, and convert incoming serial data into parallel system data for reception. The interface device must also delete or insert bits or characters that are functionally unique to the communication technique. In essence, the interface should appear transparent to the CPU for the simple input or output of byte-oriented system data.

1.2 DATA BUS BUFFER

This 3-state, bidirectional, 8-bit buffer is used to interface the MA28151 to the system data bus. Data is transmitted or received by the buffer upon execution of OUTput or INput instructions from the CPU.

Control word, Command words and Status information are also transferred through the Data Bus Buffer. The Command Status, Data-in and Data-out registers are separate 8-bit registers, communicating with the system bus through the Data Bus Buffer.

This functional block accepts inputs from the system control bus and generates control signals for overall device operation. It contains the Control Word Register and Command Word Register, which store the various control formats for the device’s functional definition.

1.3 RESET

A high on this input forces the MA28151 into idle mode. The MA28151 will remain at idle until its functional definition is programmed with a new set of control words. Minimum RESET pulse width is 6 tcy (clock must be running).

The device can also be put into the idle state by a command reset operation .

1.4CLOCK (CLK)

The CLK input is used to generate internal device timing

and is normally connected to the clock generator (OSC) of the system.

Please note: None of the external inputs or outputs are referenced to CLK but the frequency of CLK must be greater than 30 times the Receiver or Transmitter data bit rates.

1.5DATA STROBE (DSN)

This input indicates that a data transfer is taking place.

During a CPU write operation the MA28151 reads data from the bus on the rising edge of DSN. During a read operation the MA28151 can output data while DSN is low. Data is valid on the rising edge of DSN.

1.6READ/WRITE SELECT (RDWN)

A high on the RDWN input indicates a read of data or

status information from the MA28151. A low on this input indicates a transfer of data or control words into the MA28151. The RDWN line is valid only when DSN is low. Figure 2 summarises the MAS28151 read/write operati ons.

1.7 CONTROL/DATA (CDN)

This input, in conjunction with the DSN and RDWN inputs, informs the MA28151 that the word on the Data Bus is either a data character, control word or status information.

1 = CONTROL/STATUS; 0= DATA

CDN	RDWN	DSN	CSN	ACTION
0	1	0	0	28151 TO CPU
0	0	0	0	CPU TO 28151
1	1	0	0	STATUS TO CPU
1	0	0	0	CPU TO CONTROL
x	x	1	0	BUS TRISTATE
x	x	x	1	BUS TRISTATE

Figure 2: Read/Write Control

1.8CHIP SELECT (CSN)

A low on this input selects the MA28151. No reading or

writing will occur unless the device is selected. When CSN is high, the Data Bus is in the float state and the DSN and RDWN lines have no effect on the chip.

1.9 MODEM CONTROL

The MA28151 has a set of control inputs and outputs which can be used to simplify the interface to almost any modem. The modem control signals are general purpose in nature and can be used for functions other than modem control, if necessary.

1.10 DATA SET READY (DSR)

The DSR input signal is a general-purpose, 1-bit inverting input port. Its condition can be tested by the CPU using a Status Read operation. The DSR input is normally used to test modem conditions such as Data Set Ready.

1.11 DATA TERMINAL READY (DTR)

The DTR output signal is a general purpose, 1-bit inverting output port. It can be set low by programming the appropriate bit in the Command instruction word. The DTR output signal is normally used for modem control such as Data Terminal Ready.

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MA28151

1.12 REQUEST TO SEND (RTS)

The RTS output signal is a general purpose, 1-bit inverting output port. It can be set low by programming the appropriate bit in the Command instruction word. The RTS output signal is normally used for modem control such as Request To Send.

1.13 CLEAR TO SEND (CTS)

A low on this input enables the MA28151 to transmit serial data if the Tx Enable bit in the Command byte is set to a high. If either a Tx Enable off or CTS off condition occurs while the Tx is in operation, the Tx will transmit all the data in the USART, written prior to Tx disable command, before shutting down.

1.14 TRANSMITTER BUFFER

The Transmitter Buffer accepts parallel data from the Data Bus Buffer, converts it to a serial bit stream, inserts the appropriate characters or bits (based on the communication technique) and outputs a composite serial stream of data on the TxD output pin on the falling edge of TxC. The transmitter will begin transmission upon being enabled if CTS = 0. The TxD line will be held in the marking state immediately upon a master Reset, or when Tx Enable or CTS = 1, or the transmitter is empty.

1.15 TRANSMITTER CONTROL

The Transmitter Control manages all activities associated with the transmission of serial data. It accepts and issues signals both externally and internally to accomplish this function.

1.16 TRANSMITTER READY (TxRDY)

This output signals the CPU that the transmitter is ready to accept a data character. The TxRDY output pin can be used as an interrupt to the system since it is masked by TxEnable; or, for Polled operation, the CPU can check TxRDY using a Status Read operation. TxRDY is automatically reset by the falling edge of DSN (with RDWN low) when a data character is loaded from the CPU.

Note that when using the polled operation, the TxRDY status bit is not masked by TxEnable, but will only indicate the Empty/Full Status of the Tx Data input Register.

1.17 TRANSMITTER EMPTY (TxE)

When the MA28151 has no characters to send, the TxEMPTY output will go high. It resets upon receiving a character from CPU if the transmitter is enabled. TxEMPTY remains high when the transmitter is disabled. TxEMPTY can be used to indicate the end of transmission mode, so that the CPU can turn the line around in the half-duplex operational mode.

In the Synchronous mode, a high on the TxEMPTY output indicates that a character has not been loaded and the SYNC character or characters are about to be or are being

automatically transmitted as fillers. TxEMPTY does not go low when the SYNC characters are being shifted out.

1.18 TRANSMITTER CLOCK (TxC)

The Transmitter Clock controls the rate at which the character is to be transmitted. In the Synchronous transmission mode, the Baud Rate (1x) is equal to the TxC frequency. In Asynchronous transmission mode, the baud rate is a fraction of the actual TxC frequency. A portion of the mode instruction selects this factor; it can be 1,1/16 or 1/64 the TxC.

For Example:

If Baud Rate equals 110 Baud

TxC equals 110Hz in the 1x mode

TxC equals 1 72KHz in the 16x mode

TxC equals 7.04KHz in the 64x mode

The falling edge of TxC shifts the serial data out of the MA28151.

1.19 RECEIVER BUFFER

The Receiver accepts serial data, converts the data to parallel format, checks for bits or characters that are unique to the communications techniques and sends an assembled character to the CPU. Serial data is input to the RxD pin and is clocked in on the rising edge of RxC.

1.20 RECEIVER CONTROL

This functional block manages all receiver-related activities which consist of the following features:

The RxD initialisation circuit prevents the MA28151 from mistaking an unused input line for an active low data line in the break condition. Before starting to receive serial characters on the RxD line, a valid 1 must first be detected after a chip master Reset. Once this has been determined, a search for a valid low (start bit) is enabled. This feature is only active in the asynchronous mode and is only done once for each master Reset.

The False Start bit detection circuit prevents false starts as the result of a transient noise spike by first detecting the falling edge and then strobing the nominal center of the Start bit (RxD = low).

Parity error detection sets the corresponding status bit. The Framing Error status bit is set if the Stop bit is absent

at the end of the data byte (asynchronous mode).

1.21 RxRDY (RECEIVER READY)

This output indicates that the MA28151 contains a character that is ready to be input to the CPU. RxRDY can be connected to the interrupt structure of the CPU or, for polled operation, the CPU can check the condition of RxRDY using a Status Read operation. RxEnable, when off holds RxRDY in the Reset Condition. For Asynchronous mode, to set RxRDY, the Receiver must be enabled to sense a Start Bit and a complete character must be assembled and transferred to the Data Output Register. For Synchronous mode, to set RxRDY,

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MA28151

the Receiver must be enabled and a character must finish assembly and be transferred to the Data Output Register

Failure to read the received character from the Rx Data Output Register prior to the assembly of the next Rx Data character will set overrun condition error and the previous character will be written over and lost. If the Rx Data is being read by the CPU when the internal transfer is occurring, the overrun error will be set and the old character will be Iost.

1.22 RxC (RECEIVER CLOCK)

The Receiver Clock controls the rate at which the character is to be received. In Synchronous Mode the Baud Rate (1x) is equal to the actual frequency of RxC. In Asynchronous Mode, the Baud Rate is a fraction of the actual RxC frequency. A portion of the mode instruction selects this factor: 1,1⁄16 or 1⁄64 of the Receiver Clock.

For example:

Baud Rate equals 300 Baud, if

RxC equals 300 Hz in the 1 x mode:

RxC equals 4800 Hz in the 16x mode

RxC equals 19.2 KHz in the 64x mode.

Baud Rate equals 2400 Baud if

RxC equals 2400Hz in the 1x mode RxC equals 38.4 KHz in the 16x mode; RxC equals 153.6 KHz in the 64x mode.

Data is sampled into the MA28151 on the rising edge of RxC.

Note: In most communications systems, the MA28151 will be handling both the transmission and reception operations of a single link. Consequently the Receive and Transmit Baud Rates will be the same. Both TxC and RxC will require identical frequencies for this operation and can be tied together and connected to a single frequency source (Baud Rate Generator) to simplify the interface.

1.23 SYNC/BREAK DETECT (SYNDET/BRKDET)

This pin is used in Synchronous Mode for SYNDET and may be used as either input or output, programmable through the Control Word. It is reset to output mode, low upon RESET. When used as an output (internal Sync mode), the SYNDET pin will go high to indicate that the MA28151 has located the SYNC character in the Receive mode. If the MA28151 is programmed to use double Sync characters (bi-sync), the SYNDET will go high in the middle of the last bit of the second Sync character.

SYNDET is automatically reset upon a Status Read operation.

When used as an input (external SYNC detect mode), a positive going signal will cause the MA28151 to start assembling data characters on the rising edge of the next RxC. Once in SYNC, the high input signal can be removed. When External SYNC Detect is programmed, Internal SYNC Detect is disabled.

1.24 BREAK (ASYNC MODE ONLY)

This output will go high whenever the receiver remains low through two consecutive stop bit sequences including the start bits, data bits, and parity bits. Break Detect may also be read as a Status bit. It is reset only upon a master chip Reset or Rx Data returning to a “one” state.

C/D	ACTION
1	MODE INSTRUCTION
1	SYNC CHARACTER 1 (SYNC ONLY) *
1	SYNC CHARACTER 2 (SYNC ONLY) *
1	COMMAND INSTRUCTION
0	DATA
1	COMMAND INSTRUCTION
0	DATA
1	COMMAND INSTRUCTION

Note: The second sync character is skipped if mode instruction has programmed the MA28151 to single character mode. Both sync characters are skipped if mode instruction has programmed the MA28151 to async mode

Figure 3: Typical data block

2. OPERATION DESCRIPTION

2.1GENERAL

The complete functional definition of the MA28151 is

programmed by the system’s software. A set of control words must be sent out by the CPU to initialize the MA28151 to support the desired communications format. These control words will program the: Baud Rate, Character Length, Number of Stop Bits, Synchronous or Asynchronous Operation, Even/ Odd/Off Parity, etc. In the Synchronous Mode, options are also provided to select either internal or external character synchronization.

Once programmed, the MA28151 is ready to perform its communication functions. The TxRDY output is raised high to signal the CPU that the MA28151 is ready to receive a data character from the CPU. This output (TxRDY) is reset automatically when the CPU writes a character into the MA28151. Alternatively, the MA28151 receives serial data from the MODEM or l/O device. Upon receiving an entire character, the RxRDY output is raised high to signal the CPU that the MA28151 has a complete character ready for the CPU to fetch. RxRDY is reset automatically upon the CPU data read operation.

The MA28151 cannot begin transmission until the TxEnable (Transmitter Enable) bit is set in the Command instruction and it has received a Clear To Send (CTS) input. The TxD output will be held in the marking state upon Reset.

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MA28151

3. PROGRAMMING THE MA28151

3.1 MODE AND COMMAND INSTRUCTIONS

Prior to starting data transmission or reception, the MA28151 must be loaded with a set of control words generated by the CPU. These control signals define the complete functional definition of the MA28151 and must immediately follow a Reset operation (internal or external).

The control words are split into two formats:

1.Mode Instruction

2.Command Instruction

3.1.1 Mode Instruction

This instruction defines the general operational characteristics of the MA28151. It must follow a Reset operation (internal or external). Once the Mode instruction has been written into the MA28151 by the CPU, SYNC characters or Command Instructions may be written.

3.1.2 Command Instruction

This instruction defines a word that is used to control the actual operation of the MA28151.

Both the Mode and Command Instruction must conform to a specified sequence for proper device operation. The Mode instruction must be written immediately following a Reset operation, prior to using the MA28151 for data communications.

All control words written into the MA28151 after the Mode Instruction will load the Command Instruction. Command Instructions can be written into the MA28151 at any time in the data block during the operation of the MA28151. To return to the Mode Instruction format, the master Reset bit in the Command Instruction word can be set to initiate an internal Reset operation. This automatically places the MA28151 back into the Mode Instruction format. Command Instructions must follow the Mode Instructions or Sync characters.

3.2MODE INSTRUCTION DEFINITION

The MA28151 can be used for either Asynchronous or

Synchronous data communications. To understand how the Mode Instruction defines the functional operation of the MA28151, the designer can best view the device as two separate components, one Asynchronous and the other Synchronous, sharing the same package. The format definition can be changed only after a master chip Reset. For explanation purposes the two formats will be isolated.

NOTE: When parity is enabled it is not considered as one of the data bits for the purpose of programming the word length. The actual parity bit received on the Rx Data line cannot be read on the Data Bus. In the case of a programmed character length of less than 8 bits, the least significant data bus bits will hold the data; unused bits are ‘don’t care’ when writing data to the MA28151, and will be zeros when reading the data from the MA28151.

3.3TEST MODE

The Mode Instruction can be used to select a scan path

test facility. In this mode a test vector is read in through RxD and read out in TxD. For further information of test mode please contact GEC Plessey Semiconductors.

3.4ASYNCHRONOUS MODE (TRANSMISSION)

Whenever a data character is sent by the CPU the

MA28151 automatically adds a Start bit (low level), followed by the data bits (least significant bit first,) and the programmed number of Stop bits to each character. Also, an even or odd Parity bit is inserted prior to the Stop bit(s), as defined by the Mode Instruction. The Character is then transmitted as a serial data stream on the TxD output. The serial data is shifted out on

the falling edge of TxC at a rate equal to 1, 1⁄16 or 1⁄64 times that of the TxC, as defined by the Mode Instruction. BREAK characters can be continuously sent to the TxD if commanded to do so.

When no data characters have been loaded into the MA28151 the TxD output remains high (marking) unless a Break (continuously low) has been programmed.

3.5ASYNCHRONOUS MODE (RECEIVE)

The RxD line is normally high. A falling edge on this line

triggers the beginning of a START bit. The validity of this START bit is checked by again strobing this bit at its nominal center (16x or 64X mode only). If a low is detected again, it is a valid START bit, and the bit counter will start counting. The bit counter thus locates the center of the data bits, the parity bit (if it exists) and the stop bits. If a parity error occurs, the parity error flag is set. Data and parity bits are sampled on the RxD pin with the rising edge of RxC. If a low level is detected as the STOP bit, the Framing Error flag will be set. The STOP bit signals the end of a character. Note that the receiver requires only one stop bit, regardless of the number of stop bits programmed. This character is then loaded into the parallel l/O buffer of the MA28151. The RxRDY pin is raised to signal the CPU that a character is ready to be fetched.

If a previous character has not been fetched by the CPU, the present character replaces it in the l/O buffer, and the OVERRUN Error flag is raised (thus the previous character is lost). All of the error flags can be reset by an Error Reset Instruction. The occurrence of any of these errors will not affect the operation of the MA28151.

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MA28151

D7 D6 D5 D4 D3 D2 D1 D0
S2 S1 EP PEN L2 L1 B2 B1
										BAUD RATE FACTOR
										0	0		1	1
										0	0		1	1
										SYNC	(1x)		(16x)	(64x)
										MODE
										CHARACTER LENGTH
										0	1		0	1
										0	0		1	1
										5	6		7	8
										BITS	BITS		BITS	BITS
										PARITY ENABLE AND SENSE
										1 = ENABLE		0 = DISABLE
										1 = EVEN 0 = ODD
										NUMBER OF STOP BITS
										0	1		0	1
										0	0		1	1
										NOT	1		1 1/2	2
										VALID	BIT		BITS	BITS

Figure 4: Mode Instruction Format, Asynchronous Mode

				DATA BITS D0-Dx	GENERATED BY MA28151
TxD	MARKING					PARITY BIT	STOP
							BITS
				DATA BITS D0-Dx	DOES NOT APPEAR ON DBUS
RxD				PROGRAMMED CHAR. LENGTH		PARITY BIT	STOP
							BITS

Figure 5: Asynchronous Mode

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MA28151

CPU BYTE (5-8 BITS/CHARACTER)

DATA CHARACTER

ASSEMBLED SERIAL DATA OUTPUT (TxD)

START BIT	DATA CHARACTER	PARITY BIT	STOP BITS

Figure 6: Transmission Format

SERIAL DATA INPUT (RxD)

START BIT	DATA CHARACTER	PARITY BIT	STOP BITS

CPU BYTE (5-8 BITS/CHARACTER) (See Note Below)

DATA CHARACTER

NOTE: If character length is defined as 5, 6 or 7 bits the unused bits are set to zero.

Figure 7: Receive Format

3.6 SYNCHRONOUS MODE (TRANSMISSION)

The TxD output is continuously high until the CPU sends its first character to the MA28151 which usually is a SYNC character. When the CTS line goes low, the first character is serially transmitted out. All characters are shifted out on the falling edge of TxC. Data is shifted out at the same rate as the

TxC.

Once transmission has started, the data stream at the TxD output must continue at the TxC rate. If the CPU does not provide the MA28151 with a data character before the MA28151 Transmitter Buffers become empty, the SYNC characters (or character if in single SYNC character mode) will be automatically inserted in the TxD data stream. In this case, the TxEMPTY does not go low when the SYNC is being shifted out (see figure 8). The TxEMPTY pin is internally reset by a data character being written into the MA28151.

3.7 SYNCHRONOUS MODE (RECEIVER)

In this mode character synchronisation can be internally or externally achieved. If the SYNC mode has been programmed, ENTER-HUNT command should be included in the first command instruction word written. Data on the RxD pin is then sampled on the rising edge of RxC. The content of the Rx buffer is compared to every bit boundary with the first SYNC character until a match occurs.

If the MA28151 has been programmed for two SYNC characters, the subsequent received character is also compared; when both SYNC characters have been detected, the USART ends the HUNT mode and is in character

synchronization. The SYNDET pin is then set high, and is reset automatically by a STATUS READ. If parity is programmed, SYNDET will not be set until the middle of the parity bit, instead of the middle of the last data bit.

In the external SYNC mode, synchronization is achieved by applying a high level on the SYNDET pin, thus forcing the MA28151 out of the HUNT mode. The high level can be removed after one RxC cycle. An ENTER HUNT command has no effect in the asynchronous mode of operation.

Figure 8: Sync Character Insertion

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