Texas Instruments BQ4010MA-70, BQ4010MA-200, BQ4010MA-150, BQ4010YMA-85N, BQ4010YMA-85 Datasheet

Features

Data retention in the absence of power

Automatic write-protection during power-up/power-down cycles

Industry-standard 28-pin 8K x 8 pinout

Conventional SRAM operation; unlimited write cycles

10-year minimum data retention in absence of power

Battery internally isolated until power is applied

bq4010/bq4010Y

8Kx8 Nonvolatile SRAM

General Description

The CMOS bq4010 is a nonvolatile 65,536-bit static RAM organized as 8,192 words by 8 bits. The integral control circuitry and lithium energy source provide reliable nonvolatility coupled with the unlimited write cycles of standard SRAM.

The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC falls out of tolerance, the SRAM is unconditionally write-protected to prevent inadvertent write operation.

At this time the integral energy source is switched on to sustain the memory until after VCC returns valid.

The bq4010 uses an extremely low standby current CMOS SRAM, coupled with a small lithium coin cell to provide nonvolatility without long write-cycle times and the writecycle limitations associated with EEPROM.

The bq4010 requires no external circuitry and is socket-compatible with industry-standard SRAMs and most EPROMs and EEPROMs.

Pin Connections		Pin Names			Block Diagram
		A0 –A 12 Address inputs
		DQ0–DQ 7 Data input/output
		CE	Chip enable input
		OE	Output enable input
		WE	Write enable input
		NC	No connect
		VCC	+5 volt supply input
		VSS	Ground
Selection Guide
	Maximum		Negative		Maximum	Negative
Part	Access		Supply	Part	Access	Supply
Number	Time (ns)	Tolerance		Number	Time (ns)	Tolerance
				bq4010Y -70	70	-10%
bq4010 -85	85		-5%	bq4010Y -85	85	-10%
bq4010 -150	150		-5%	bq4010Y -150	150	-10%
bq4010 -200	200		-5%	bq4010Y -200	200	-10%

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bq4010/bq4010Y

	Functional Description							As VCC falls past VPFD and approaches 3V, the control
								circuitry switches to the internal lithium backup supply,
	When power is valid, the bq4010 operates as a standard							which provides data retention until valid VCC is applied.
	CMOS SRAM. During power-down and power-up cycles,							When VCC returns to a level above the internal backup
	the bq4010 acts as a nonvolatile memory, automatically
								cell voltage, the supply is switched back to VCC. After
	protecting and preserving the memory contents.
								VCC ramps above the VPFD threshold, write-protection
	Power-down/power-up	control circuitry constantly						continues for a time tCER (120ms maximum) to allow for
								processor stabilization. Normal memory operation may
	monitors the VCC supply for a power-fail-detect threshold
								resume after this time.
	VPFD. The bq4010 monitors for VPFD = 4.62V typical for
	use in systems with 5% supply tolerance. The bq4010Y							The internal coin cell used by the bq4010 has an
	monitors for VPFD = 4.37V typical for use in systems with
								extremely long shelf life and provides data retention for
	10% supply tolerance.
								more than 10 years in the absence of system power.
	When VCC falls below the VPFD threshold, the SRAM							As shipped from Benchmarq, the integral lithium cell is
	automatically write-protects the				data. All outputs
								electrically isolated from the memory. (Self-discharge in
	become high impedance, and all inputs are treated as
								this condition is approximately 0.5% per year.) Following
	“don’t care.” If a valid access is in process at the time of							the first application of VCC, this isolation is broken, and
	power-fail detection, the memory cycle continues to com-
								the lithium	backup cell provides	data retention on
	pletion. If the memory	cycle fails			to terminate within
								subsequent power-downs.
	time tWPT, write-protection takes place.
	Truth Table
	Mode							OE	I/O Operation	Power
			CE			WE
	Not selected		H			X		X	High Z	Standby
	Output disable		L			H		H	High Z	Active
	Read		L			H		L	DOUT	Active
	Write		L			L		X	DIN	Active

Absolute Maximum Ratings

Symbol	Parameter	Value		Unit	Conditions
VCC	DC voltage applied on VCC relative to VSS	-0.3 to 7.0		V
VT	DC voltage applied on any pin excluding VCC	-0.3 to 7.0		V	VT ≤ VCC + 0.3
	relative to VSS
TOPR	Operating temperature	0 to +70		°C	Commercial
		-40 to +85		°C	Industrial “N”
TSTG	Storage temperature	-40 to +70		°C	Commercial
		-40 to +85		°C	Industrial “N”
TBIAS	Temperature under bias	-10 to +70		°C	Commercial
		-40 to +85		°C	Industrial “N”
TSOLDER	Soldering temperature	+260		°C	For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.

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								bq4010/bq4010Y
	Recommended DC Operating Conditions (TA = TOPR)
	Symbol	Parameter	Minimum	Typical	Maximum	Unit		Notes
	VCC	Supply voltage	4.5	5.0	5.5	V		bq4010Y/bq4010Y-xxxN
			4.75	5.0	5.5	V		bq4010
	VSS	Supply voltage	0	0	0	V
	VIL	Input low voltage	-0.3	-	0.8	V
	VIH	Input high voltage	2.2	-	VCC + 0.3	V
	Note:	Typical values indicate operation at TA = 25°C.
	DC Electrical Characteristics (TA = TOPR, VCCmin £ VCC £ VCCmax)
	Symbol	Parameter	Minimum	Typical	Maximum	Unit		Conditions/Notes

ILI	Input leakage current	-	-	± 1
ILO	Output leakage current	-	-	± 1
VOH	Output high voltage	2.4	-	-
VOL	Output low voltage	-	-	0.4
ISB1	Standby supply current	-	4	7
ISB2	Standby supply current	-	2.5	4

	mA	VIN = VSS to VCC
			= VIH or		= VIH or
	mA	CE		OE
		WE = VIL
	V	IOH = -1.0 mA
	V	IOL = 2.1 mA
	mA		= VIH
		CE
			³ VCC - 0.2V,
	mA	CE
		0V £ VIN £ 0.2V,
		or VIN ³ VCC - 0.2V

	ICC	Operating supply current	-	65	75	mA	Min. cycle, duty = 100%,
							CE = VIL, II/O = 0mA
	VPFD	Power-fail-detect voltage	4.55	4.62	4.75	V	bq4010
			4.30	4.37	4.50	V	bq4010Y
	VSO	Supply switch-over voltage	-	3	-	V
	Note:	Typical values indicate operation at TA = 25°C, VCC = 5V.
	Capacitance (TA = 25°C, F = 1MHz, V CC = 5.0V)
	Symbol	Parameter	Minimum	Typical	Maximum	Unit			Conditions
	CI/O	Input/output capacitance	-	-	10	pF			Output voltage = 0V
	CIN
		Input capacitance	-	-	10	pF			Input voltage = 0V

Note: These parameters are sampled and not 100% tested.

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bq4010/bq4010Y

AC Test Conditions

Parameter									Test Conditions
Input pulse levels									0V to 3.0V
Input rise and fall times									5 ns
Input and output timing reference levels									1.5 V (unless otherwise specified)
Output load (including scope and jig)									See Figures 1 and 2

	Figure 1. Output Load A						Figure 2. Output Load B
Read Cycle (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
		-70/-70N		-85/-85N		-150/-150N			-200
Symbol	Parameter	Min.	Max.	Min.	Max.	Min.	Max.		Min.	Max.	Unit	Conditions
tRC	Read cycle time	70	-	85	-	150	-		200	-	ns
tAA	Address access time	-	70	-	85	-	150		-	200	ns	Output load A
tACE	Chip enable access time	-	70	-	85	-	150		-	200	ns	Output load A
tOE	Output enable to output	-	35	-	45	-	70		-	90	ns	Output load A
	valid
tCLZ	Chip enable to output	5	-	5	-	10	-		10	-	ns	Output load B
	in low Z
tOLZ	Output enable to output	5	-	5	-	5	-		5	-	ns	Output load B
	in low Z
tCHZ	Chip disable to output	0	25	0	40	0	60		0	70	ns	Output load B
	in high Z
tOHZ	Output disable to	0	25	0	30	0	50		0	70	ns	Output load B
	output in high Z
tOH	Output hold from	10	-	10	-	10	-		10	-	ns	Output load A
	address change
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