Texas Instruments 74AC11138PWR, 74AC11138PWLE, 74AC11138N, 74AC11138DR, 74AC11138D Datasheet

0 (0)

74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

SCAS042B ± MAY 1988 ± REVISED APRIL 1996

D Designed Specifically for High-Speed

D, N, OR PW PACKAGE

Memory Decoders and Data Transmission

 

 

(TOP VIEW)

 

 

Systems

Y1

 

 

 

 

 

Y0

 

1

16

 

 

D Incorporates Three Enable Inputs to

 

 

 

Y2

 

2

15

 

 

A

Simplify Cascading and/or Data Reception

 

 

 

Y3

 

3

14

 

 

B

D Center-Pin VCC and GND Configurations

 

 

 

GND

 

4

13

 

 

C

 

 

 

Minimize High-Speed Switching Noise

 

 

 

Y4

 

5

12

 

 

VCC

 

 

 

D EPIC (Enhanced-Performance Implanted

 

 

 

 

 

Y5

 

6

11

 

 

G1

CMOS) 1- m Process

 

 

 

Y6

 

7

10

 

 

G2A

D 500-mA Typical Latch-Up Immunity at

 

 

 

 

 

 

 

 

 

 

Y7

 

8

9

 

 

G2B

125°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D Package Options Include Plastic

 

 

 

 

 

 

 

Small-Outline (D) and Thin Shrink

 

 

 

 

 

 

 

Small-Outline (PW) Packages, and

 

 

 

 

 

 

 

Standard Plastic 300-mil DIPs (N)

 

 

 

 

 

 

 

description

The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The 74AC11138 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE

ENABLE INPUTS

SELECT INPUTS

 

 

 

OUTPUTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G1

 

 

 

C

B

A

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

G2A

 

G2B

 

X

H

X

X

X

X

H

H

H

H

H

H

H

H

X

X

H

X

X

X

H

H

H

H

H

H

H

H

L

X

X

X

X

X

H

H

H

H

H

H

H

H

H

L

L

L

L

L

L

H

H

H

H

H

H

H

H

L

L

L

L

H

H

L

H

H

H

H

H

H

H

L

L

L

H

L

H

H

L

H

H

H

H

H

H

L

L

L

H

H

H

H

H

L

H

H

H

H

H

L

L

H

L

L

H

H

H

H

L

H

H

H

H

L

L

H

L

H

H

H

H

H

H

L

H

H

H

L

L

H

H

L

H

H

H

H

H

H

L

H

H

L

L

H

H

H

H

H

H

H

H

H

H

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

 

Copyright 1996, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments

 

 

standard warranty. Production processing does not necessarily include

 

 

testing of all parameters.

 

 

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

1

POST OFFICE BOX 1443

HOUSTON, TEXAS 77251±1443

 

Texas Instruments 74AC11138PWR, 74AC11138PWLE, 74AC11138N, 74AC11138DR, 74AC11138D Datasheet

74AC11138

3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

SCAS042B ± MAY 1988 ± REVISED APRIL 1996

logic symbols (alternatives)²

15

 

BIN/OCT

0

16

Y0

15

 

DMUX

0

16

Y0

 

A

 

 

1

 

 

 

A

 

 

0

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

1

 

14

 

 

0

 

1

 

 

B

 

 

2

 

 

1

 

Y1

B

 

 

 

G

7

1

 

Y1

 

 

 

 

2

 

 

2

13

 

 

 

 

 

13

 

 

 

 

 

 

C

 

 

4

 

 

2

3

Y2

C

 

 

2

 

 

2

3

Y2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

Y3

 

 

 

 

 

 

 

3

Y3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

&

 

5

11

&

 

 

5

 

 

 

 

 

 

 

 

 

G1

 

 

 

 

4

 

Y4

G1

 

 

 

 

4

 

Y4

 

 

 

 

 

 

 

 

 

 

 

10

 

 

EN

 

6

 

 

 

10

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

G2A

 

 

5

 

Y5

G2A

 

 

 

5

 

Y5

 

 

 

 

 

 

 

 

 

 

9

 

 

 

6

7

Y6

 

9

 

 

 

6

7

Y6

G2B

 

 

 

8

G2B

 

 

 

8

 

 

 

 

 

 

 

 

7

Y7

 

 

 

 

 

 

 

7

Y7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

² These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

 

 

 

16

Y0

 

 

 

 

 

A

15

 

 

 

 

 

 

 

 

 

1

Y1

 

 

 

 

 

 

 

2

 

Select

 

14

 

Y2

B

 

 

Inputs

 

 

 

 

 

3

 

 

 

 

Y3

 

 

 

 

 

 

 

 

Data

 

 

 

5

Outputs

 

 

 

Y4

 

 

13

 

 

C

 

 

 

 

 

 

 

 

 

6

Y5

 

 

 

 

 

 

 

7

Y6

 

 

 

 

 

G2A

10

8

 

Enable

9

Y7

 

 

G2B

 

 

Inputs

 

 

 

 

11

 

 

 

G1

 

 

 

 

 

 

2

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

 

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251±1443

74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

SCAS042B ± MAY 1988 ± REVISED APRIL 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . ±0.5 V to 7

V

Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±0.5 V to VCC + 0.5

V

Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±0.5 V to VCC + 0.5

V

Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±20 mA

Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±50 mA

Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±50 mA

Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . ±200 mA

Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . .

. . . . . . . . . . . . . 1.3 W

N package . . . . . . .

. . . . . . . . . . . . . 1.1 W

PW package . . . . . .

. . . . . . . . . . . . . 0.5 W

Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . ±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

recommended operating conditions

 

 

 

MIN

NOM

MAX

UNIT

 

 

 

 

 

 

 

VCC

Supply voltage

 

3

5

5.5

V

 

 

VCC = 3 V

2.1

 

 

 

VIH

High-level input voltage

VCC = 4.5 V

3.15

 

 

V

 

 

VCC = 5.5 V

3.85

 

 

 

 

 

VCC = 3 V

 

 

0.9

 

VIL

Low-level input voltage

VCC = 4.5 V

 

 

1.35

V

 

 

VCC = 5.5 V

 

 

1.65

 

VI

Input voltage

 

0

 

VCC

V

VO

Output voltage

 

0

 

VCC

V

 

 

VCC = 3 V

 

 

±4

 

IOH

High-level output current

VCC = 4.5 V

 

 

±24

mA

 

 

VCC = 5.5 V

 

 

±24

 

 

 

VCC = 3 V

 

 

12

 

IOL

Low-level output current

VCC = 4.5 V

 

 

24

mA

 

 

VCC = 5.5 V

 

 

24

 

t/ v

Input transition rise or fall rate

 

0

 

10

ns/V

 

 

 

 

 

 

 

TA

Operating free-air temperature

 

±40

 

85

°C

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

3

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251±1443

 

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