74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B ± MAY 1988 ± REVISED APRIL 1996
D Designed Specifically for High-Speed |
D, N, OR PW PACKAGE |
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Memory Decoders and Data Transmission |
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(TOP VIEW) |
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Systems |
Y1 |
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Y0 |
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1 |
16 |
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D Incorporates Three Enable Inputs to |
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Y2 |
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2 |
15 |
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A |
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Simplify Cascading and/or Data Reception |
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Y3 |
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3 |
14 |
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B |
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D Center-Pin VCC and GND Configurations |
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GND |
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4 |
13 |
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C |
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Minimize High-Speed Switching Noise |
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Y4 |
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5 |
12 |
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VCC |
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D EPIC (Enhanced-Performance Implanted |
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Y5 |
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6 |
11 |
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G1 |
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CMOS) 1- m Process |
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Y6 |
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7 |
10 |
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G2A |
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D 500-mA Typical Latch-Up Immunity at |
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Y7 |
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8 |
9 |
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G2B |
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125°C |
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D Package Options Include Plastic |
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Small-Outline (D) and Thin Shrink |
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Small-Outline (PW) Packages, and |
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Standard Plastic 300-mil DIPs (N) |
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description
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 74AC11138 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE
ENABLE INPUTS |
SELECT INPUTS |
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OUTPUTS |
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G1 |
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C |
B |
A |
Y0 |
Y1 |
Y2 |
Y3 |
Y4 |
Y5 |
Y6 |
Y7 |
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G2A |
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G2B |
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X |
H |
X |
X |
X |
X |
H |
H |
H |
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X |
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H |
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L |
X |
X |
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H |
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H |
L |
L |
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H |
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H |
L |
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H |
H |
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H |
L |
L |
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H |
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H |
L |
L |
H |
H |
H |
H |
H |
H |
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H |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. |
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Copyright 1996, Texas Instruments Incorporated |
Products conform to specifications per the terms of Texas Instruments |
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standard warranty. Production processing does not necessarily include |
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testing of all parameters. |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
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POST OFFICE BOX 1443 |
•HOUSTON, TEXAS 77251±1443 |
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74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B ± MAY 1988 ± REVISED APRIL 1996
logic symbols (alternatives)²
15 |
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BIN/OCT |
0 |
16 |
Y0 |
15 |
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DMUX |
0 |
16 |
Y0 |
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A |
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1 |
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A |
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0 |
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14 |
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1 |
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14 |
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0 |
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1 |
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B |
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2 |
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1 |
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Y1 |
B |
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G |
7 |
1 |
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Y1 |
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2 |
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2 |
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13 |
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13 |
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C |
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4 |
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2 |
3 |
Y2 |
C |
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2 |
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2 |
3 |
Y2 |
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3 |
Y3 |
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3 |
Y3 |
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11 |
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& |
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5 |
11 |
& |
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5 |
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G1 |
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4 |
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Y4 |
G1 |
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4 |
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Y4 |
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10 |
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EN |
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6 |
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10 |
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6 |
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G2A |
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5 |
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Y5 |
G2A |
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5 |
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Y5 |
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9 |
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6 |
7 |
Y6 |
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9 |
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6 |
7 |
Y6 |
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G2B |
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8 |
G2B |
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8 |
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7 |
Y7 |
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7 |
Y7 |
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² These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
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16 |
Y0 |
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A |
15 |
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1 |
Y1 |
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2 |
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Select |
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14 |
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Y2 |
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B |
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Inputs |
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3 |
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Y3 |
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Data |
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5 |
Outputs |
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Y4 |
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13 |
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C |
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6 |
Y5 |
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7 |
Y6 |
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G2A |
10 |
8 |
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Enable |
9 |
Y7 |
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G2B |
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Inputs |
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11 |
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G1 |
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2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
|
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443 |
74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B ± MAY 1988 ± REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.5 V to 7 |
V |
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±20 mA |
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Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . ±200 mA |
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Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . |
. . . . . . . . . . . . . 1.3 W |
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N package . . . . . . . |
. . . . . . . . . . . . . 1.1 W |
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PW package . . . . . . |
. . . . . . . . . . . . . 0.5 W |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . ±65°C to 150°C |
²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
recommended operating conditions
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MIN |
NOM |
MAX |
UNIT |
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VCC |
Supply voltage |
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3 |
5 |
5.5 |
V |
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VCC = 3 V |
2.1 |
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VIH |
High-level input voltage |
VCC = 4.5 V |
3.15 |
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V |
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VCC = 5.5 V |
3.85 |
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VCC = 3 V |
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0.9 |
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VIL |
Low-level input voltage |
VCC = 4.5 V |
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1.35 |
V |
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VCC = 5.5 V |
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1.65 |
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VI |
Input voltage |
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0 |
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VCC |
V |
VO |
Output voltage |
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0 |
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VCC |
V |
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VCC = 3 V |
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±4 |
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IOH |
High-level output current |
VCC = 4.5 V |
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±24 |
mA |
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VCC = 5.5 V |
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±24 |
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VCC = 3 V |
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12 |
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IOL |
Low-level output current |
VCC = 4.5 V |
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24 |
mA |
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VCC = 5.5 V |
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24 |
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t/ v |
Input transition rise or fall rate |
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0 |
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10 |
ns/V |
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TA |
Operating free-air temperature |
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±40 |
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85 |
°C |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443 |
|