Texas Instruments 74ACT16841DLR, 74ACT16841DL, 74ACT16841DGGR Datasheet

	54ACT16841, 74ACT16841
	20-BIT BUS-INTERFACE D-TYPE LATCHES
	WITH 3-STATE OUTPUTS
	SCAS174A ± MAY 1991 ± REVISED APRIL 1996
D Members of the Texas Instruments	54ACT16841 . . . WD PACKAGE
Widebus Family	74ACT16841 . . . DGG OR DL PACKAGE
	(TOP VIEW)

DInputs Are TTL-Voltage Compatible

D 3-State Outputs Drive Bus Lines Directly
	1OE				1	56		1LE
D Provide Extra Bus Driving/Latches
	1Q1				2	55		1D1
Necessary for Wider Address/Data Paths or	1Q2				3	54		1D2
Buses With Parity	GND				4	53		GND
D Flow-Through Architecture Optimizes	1Q3				5	52		1D3
PCB Layout	1Q4				6	51		1D4
D Distributed VCC and GND Pin Configuration	VCC				7	50		VCC
Minimizes High-Speed Switching Noise	1Q5				8	49		1D5
D EPIC (Enhanced-Performance Implanted	1Q6				9	48		1D6
	1Q7				10	47		1D7
CMOS) 1- m Process
D 500-mA Typical Latch-Up Immunity at	GND				11	46		GND
	1Q8				12	45		1D8
125°C
	1Q9				13	44		1D9
D Package Options Include Plastic Thin
	1Q10				14	43		1D10
Shrink Small-Outline (DGG) Packages,	2Q1				15	42		2D1
300-mil Shrink Small-Outline (DL) Packages	2Q2				16	41		2D2
Using 25-mil Center-to-Center Pin
	2Q3				17	40		2D3
Spacings, and 380-mil Fine-Pitch Ceramic
	GND				18	39		GND
Flat (WD) Packages Using 25-mil
	2Q4				19	38		2D4
Center-to-Center Pin Spacings
	2Q5				20	37		2D5
description	2Q6				21	36		2D6
	VCC				22	35		VCC
These 20-bit latches feature 3-state outputs	2Q7				23	34		2D7
designed specifically for driving highly capacitive	2Q8				24	33		2D8
or relatively low-impedance loads. They are	GND				25	32		GND
particularly suitable for implementing buffer	2Q9				26	31		2D9
registers, I/O ports, bidirectional bus drivers, and	2Q10				27	30		2D10
working registers.
	2OE				28	29		2LE

The 'ACT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

54ACT16841, 74ACT16841

20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCAS174A ± MAY 1991 ± REVISED APRIL 1996

description (continued)

The 74ACT16841 is packaged in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16841 is characterized for operation over the full military temperature range of ±55°C to 125°C. The 74ACT16841 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each 10-bit latch)

		INPUTS		OUTPUT
		LE	D	Q
	OE
	L	H	H	H
	L	H	L	L
	L	L	X	Q0
	H	X	X	Z

logic symbol²

		1		EN2
1OE
56
1LE				C1
		28		EN4
2OE
29
2LE				C3
55								2
1D1				1D		2			1Q1
54								3
1D2									1Q2
52								5
1D3									1Q3
51								6
1D4									1Q4
49								8
1D5									1Q5
48								9
1D6									1Q6
47								10
1D7									1Q7
45								12
1D8									1Q8
44								13
1D9									1Q9
43								14
1D10									1Q10
42								15
2D1				3D		4			2Q1
41								16
2D2									2Q2
40								17
2D3									2Q3
38								19
2D4									2Q4
37								20
2D5									2Q5
36								21
2D6									2Q6
								23
34									2Q7
2D7
33								24
2D8									2Q8
31								26
2D9									2Q9
30								27
2D10									2Q10

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265