Texas Instruments 74AC11244DBR, 74AC11244DBLE, 74AC11244PWR, 74AC11244PWLE, 74AC11244NT Datasheet

74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

SCAS171B ± MARCH 1987 ± REVISED SEPTEMBER 1998

D EPIC (Enhanced-Performance Implanted	DB, DW, NT, OR PW PACKAGE
CMOS ) 1-μm Process			(TOP VIEW)
D 3-State Outputs Drive Bus Lines or Buffer	1Y1
			1	24	1OE
Memory Address Registers
	1Y2		2	23	1A1
D Flow-Through Architecture Optimizes PCB
	1Y3		3	22	1A2
Layout
	1Y4		4	21	1A3
D Center-Pin VCC and GND Pin
	GND		5	20	1A4
Configurations Minimize High-Speed	GND		6	19	VCC
Switching Noise
	GND		7	18	VCC
D 500-mA Typical Latch-Up Immunity at
	GND		8	17	2A1
125°C	2Y1		9	16	2A2
D Package Options Include Plastic	2Y2		10	15	2A3
Small-Outline (DW), Shrink Small-Outline	2Y3		11	14	2A4
	2Y4
(DB), and Thin Shrink Small-Outline (PW)			12	13	2OE
Packages, and Standard Plastic DIPs (NT)

description

The 74AC11244 is an octal buffer or line driver designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as two 4-bit buffers or one 8-bit buffer, with active-low output-enable (OE) inputs.

When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 74AC11244 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each driver)

	INPUTS		OUTPUT
		A	Y
	OE
	L	H	H
	L	L	L
	H	X	Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

74AC11244

OCTAL BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCAS171B ± MARCH 1987 ± REVISED SEPTEMBER 1998

logic symbol²

			24								13
1OE				EN			1		2OE				EN			9
			23					1Y1	17								2Y1
1A1									2A1
			22				2		16							10
1A2								1Y2	2A2								2Y2
			21				3		15							11
1A3								1Y3	2A3								2Y3
			20				4		14							12
1A4								1Y4	2A4								2Y4

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

	1OE	24			13
				2OE
	1A1	23	1		17	9
			1Y1	2A1
						2Y1
	1A2	22	2		16	10
			1Y2	2A2		2Y2
		21	3		15	11
	1A3		1Y3	2A3
						2Y3
	1A4	20	4		14	12
			1Y4	2A4
						2Y4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . 104°C/W
DW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . 120°C/W
NT package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265