74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS214A ± JULY 1987 ± REVISED APRIL 1996
D Eight D-Type Flip-Flops in a Single Package |
DB, DW, OR NT PACKAGE |
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D 3-State Bus-Driving True Outputs |
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(TOP VIEW) |
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D Full Parallel Access for Loading |
1Q |
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1 |
24 |
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OE |
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D |
Flow-Through Architecture Optimizes |
2Q |
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2 |
23 |
1D |
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PCB Layout |
3Q |
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3 |
22 |
2D |
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D Center-Pin VCC and GND Configurations |
4Q |
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4 |
21 |
3D |
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GND |
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5 |
20 |
4D |
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Minimize High-Speed Switching Noise |
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GND |
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6 |
19 |
VCC |
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D |
EPICt (Enhanced-Performance Implanted |
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GND |
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CMOS) 1-mm Process |
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7 |
18 |
VCC |
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GND |
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D 500-mA Typical Latch-Up Immunity at |
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8 |
17 |
5D |
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5Q |
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9 |
16 |
6D |
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125°C |
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6Q |
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10 |
15 |
7D |
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D Package Options Include Plastic |
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7Q |
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11 |
14 |
8D |
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Small-Outline (DW) and Shrink |
8Q |
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12 |
13 |
CLK |
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Small-Outline (DB) Packages, and Standard |
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Plastic 300-mil DIPs (NT) |
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description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the 74AC11374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels set up at the D inputs.
The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines signigicantly. The high-impedance third state provides the capability to drive the bus lines in a bus-organized system without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The 74AC11374 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE (each flip-flop)
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INPUTS |
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OUTPUT |
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CLK |
D |
Q |
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OE |
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L |
↑ |
H |
H |
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L |
↑ |
L |
L |
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L |
L |
X |
Q0 |
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L |
H |
X |
Q0 |
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L |
↓ |
X |
Q0 |
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H |
X |
X |
Z |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS214A ± JULY 1987 ± REVISED APRIL 1996
logic symbol²
OE |
24 |
EN |
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CLK |
13 |
C1 |
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23 |
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1 |
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1D |
1D |
1Q |
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22 |
2 |
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2D |
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2Q |
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21 |
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3 |
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3D |
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3Q |
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20 |
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4 |
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4D |
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4Q |
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17 |
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9 |
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5D |
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5Q |
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16 |
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10 |
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6D |
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6Q |
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15 |
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11 |
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7D |
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7Q |
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14 |
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12 |
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8D |
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8Q |
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² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
OE
13
CLK |
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C1 |
1 |
1D |
23 |
1Q |
1D |
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C1 |
2 |
2D |
22 |
2Q |
1D |
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C1 |
3 |
3D |
21 |
3Q |
1D |
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C1 |
4 |
4D |
20 |
4Q |
1D |
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C1 |
9 |
5D |
17 |
5Q |
1D |
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C1 |
10 |
6D |
16 |
6Q |
1D |
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C1 |
11 |
7D |
15 |
7Q |
1D |
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C1 |
12 |
8D |
14 |
8Q |
1D |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS
SCAS214A ± JULY 1987 ± REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.5 V to 7 |
V |
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±20 mA |
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Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . ±200 mA |
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Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . |
. . . . . . . . . . . . 0.65 W |
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DW package . . . . . |
. . . . . . . . . . . . . 1.7 W |
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NT package . . . . . . |
. . . . . . . . . . . . . 1.3 W |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . ±65°C to 150°C |
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²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero.
recommended operating conditions
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MIN |
NOM |
MAX |
UNIT |
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VCC |
Supply voltage |
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3 |
5 |
5.5 |
V |
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VCC = 3 V |
2.1 |
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VIH |
High-level input voltage |
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VCC = 4.5 V |
3.15 |
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V |
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VCC = 5.5 V |
3.85 |
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VCC = 3 V |
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0.9 |
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VIL |
Low-level input voltage |
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VCC = 4.5 V |
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1.35 |
V |
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VCC = 5.5 V |
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1.65 |
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VI |
Input voltage |
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0 |
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VCC |
V |
VO |
Output voltage |
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0 |
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VCC |
V |
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VCC = 3 V |
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±4 |
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IOH |
High-level output current |
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VCC = 4.5 V |
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±24 |
mA |
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VCC = 5.5 V |
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±24 |
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VCC = 3 V |
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12 |
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IOL |
Low-level output current |
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VCC = 4.5 V |
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24 |
mA |
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VCC = 5.5 V |
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24 |
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Dt/Dv Input transition rise or fall rate |
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Data |
0 |
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10 |
ns/V |
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OE |
0 |
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5 |
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TA |
Operating free-air temperature |
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±40 |
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85 |
°C |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
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