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74ACT11373 |
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OCTAL TRANSPARENT D-TYPE LATCH |
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WITH 3-STATE OUTPUTS |
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SCAS015B ± JUNE 1987 ± REVISED APRIL 1996 |
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D Eight Latches in a Single Package |
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D 3-State Bus Driving True Outputs |
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D Full Parallel Access for Loading |
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1Q |
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OE |
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D Buffered Input and Output-Enable Pins |
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2Q |
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D Inputs Are TTL-Voltage Compatible |
3Q |
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D Flow-Through Architecture Optimizes |
4Q |
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3D |
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PCB Layout |
GND |
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4D |
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D Center-Pin VCC and GND Configurations |
GND |
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VCC |
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GND |
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VCC |
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Minimize High-Speed Switching Noise |
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GND |
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5D |
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D EPICt (Enhanced-Performance Implanted |
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5Q |
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6D |
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CMOS) 1-mm Process |
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6Q |
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7D |
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D 500-mA Typical Latch-Up Immunity at |
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7Q |
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8D |
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125°C |
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DPackage Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT)
description
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the 74ACT11373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impendance third state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
The 74ACT11373 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE (each latch)
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INPUTS |
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OUTPUT |
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LE |
D |
Q |
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OE |
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L |
H |
H |
H |
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L |
H |
L |
L |
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L |
L |
X |
Q0 |
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H |
X |
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Z |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SCAS015B ± JUNE 1987 ± REVISED APRIL 1996
logic symbol²
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24 |
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OE |
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EN |
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13 |
C1 |
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LE |
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1 |
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1D |
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1Q |
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22 |
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2 |
2Q |
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2D |
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21 |
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3 |
3Q |
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3D |
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20 |
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4 |
4Q |
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4D |
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17 |
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9 |
5Q |
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5D |
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16 |
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10 |
6Q |
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6D |
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7Q |
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14 |
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12 |
8Q |
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8D |
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² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
OE
13
LE |
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23 |
C1 |
1 |
1D |
1D |
1Q |
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22 |
C1 |
2 |
2D |
1D |
2Q |
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21 |
C1 |
3 |
3D |
1D |
3Q |
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20 |
C1 |
4 |
4D |
1D |
4Q |
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17 |
C1 |
9 |
5D |
1D |
5Q |
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16 |
C1 |
10 |
6D |
1D |
6Q |
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15 |
C1 |
11 |
7D |
1D |
7Q |
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14 |
C1 |
12 |
8D |
1D |
8Q |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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