Texas Instruments 74ACT11032PWR, 74ACT11032PWLE, 74ACT11032N, 74ACT11032DR, 74ACT11032DBR Datasheet

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Texas Instruments 74ACT11032PWR, 74ACT11032PWLE, 74ACT11032N, 74ACT11032DR, 74ACT11032DBR Datasheet

74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES

SCAS008C ± JULY 1987 ± REVISED APRIL 1996

DInputs Are TTL-Voltage Compatible

DCenter-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise

DEPICt (Enhanced-Performance Implanted CMOS) 1-mm Process

D500-mA Typical Latch-Up Immunity at 125°C

DPackage Options Include Plastic Small-Outline Packages (D), Plastic Shrink Small-Outline Packages (DB), Plastic Thin Shrink Small-Outline Packages (PW), and Standard Plastic 300-mil DIPs (N)

D, DB, N, OR PW PACKAGE

(TOP VIEW)

1A

 

1

16

 

1B

 

 

1Y

 

2

15

 

2A

 

 

2Y

 

3

14

 

2B

 

 

GND

 

4

13

 

VCC

 

 

GND

 

5

12

 

VCC

 

 

3Y

 

 

 

6

11

 

3A

4Y

 

7

10

 

3B

 

 

4B

 

8

9

 

4A

 

 

 

 

 

 

 

 

description

This device contains four independent 2-input OR gates. It performs the Boolean function Y = A + B or Y + A B in positive logic.

The 74ACT11032 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each gate)

INPUTS

OUTPUT

 

 

Y

A

B

 

 

 

 

H

X

H

X

H

H

L

L

L

 

 

 

logic symbol²

 

 

 

logic diagram (positive logic)

1

 

 

 

 

 

 

 

 

 

 

 

 

1A

 

 

1A

2

 

 

 

 

 

 

 

1Y

16

 

 

1Y

1B

 

 

 

 

 

 

 

 

 

1B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

 

2A

 

 

 

 

 

 

 

 

 

 

 

2A

 

 

3

 

 

 

 

 

 

 

 

 

 

14

 

 

2Y

2B

 

 

 

2Y

 

 

 

 

 

 

 

2B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3A

 

 

6

 

3A

 

 

 

 

 

 

10

 

 

3Y

 

 

 

 

3Y

3B

 

 

 

 

3B

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4A

 

 

7

 

4A

 

 

 

 

 

 

 

 

 

 

 

8

 

 

4Y

 

 

 

 

 

 

 

 

4Y

 

 

 

 

 

 

 

 

 

4B

 

 

 

4B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

1

74ACT11032

QUADRUPLE 2-INPUT POSITIVE-OR GATES

SCAS008C ± JULY 1987 ± REVISED APRIL 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . ±0.5 V to 6V

Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±0.5 V to VCC + 0.5 V

Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±0.5 V to VCC + 0.5 V

Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . ±20 mA

Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . ±50 mA

Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . ±50 mA

Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±100 mA

Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . .

. . . . . . . . . . . . . . 1.3 W

DB package . . . . .

. . . . . . . . . . . . . 0.55 W

N package . . . . . .

. . . . . . . . . . . . . . 1.1 W

PW package . . . . .

. . . . . . . . . . . . . . 0.5 W

Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . ± 65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

recommended operating conditions

 

 

MIN

MAX

UNIT

 

 

 

 

 

VCC

Supply voltage

4.5

5.5

V

VIH

High-level input voltage

2

 

V

VIL

Low-level input voltage

 

0.8

V

VI

Input voltage

0

VCC

V

VO

Output voltage

0

VCC

V

IOH

High-level output current

 

± 24

mA

IOL

Low-level output current

 

24

mA

Dt /Dv

Input transition rise or fall rate

0

10

ns/ V

 

 

 

 

 

TA

Operating free-air temperature

±40

85

°C

2

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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