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74ACT11074 |
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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP |
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WITH CLEAR AND PRESET |
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SCAS498A ± DECEMBER 1986 ± REVISED APRIL 1996 |
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D Inputs Are TTL-Voltage Compatible |
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D, DB, OR N PACKAGE |
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D Center-Pin VCC and GND Configurations to |
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(TOP VIEW) |
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Minimize High-Speed Switching Noise |
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D EPICt (Enhanced-Performance Implanted |
1PRE |
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1 |
14 |
1CLK |
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1Q |
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2 |
13 |
1D |
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CMOS) 1-mm Process |
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1Q |
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3 |
12 |
1CLR |
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D 500-mA Typical Latch-Up Immunity |
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GND |
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4 |
11 |
VCC |
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at 125°C |
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2Q |
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5 |
10 |
2CLR |
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D Package Options Include Plastic |
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2Q |
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6 |
9 |
2D |
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Small-Outline (D) and Shrink Small-Outline |
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7 |
8 |
2CLK |
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2PRE |
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(DB) Packages, and Standard Plastic |
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300-mil DIPs (N) |
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description
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
The 74ACT11074 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
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CLK |
D |
Q |
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PRE |
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CLR |
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Q |
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L |
H |
X |
X |
H |
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L |
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H |
L |
X |
X |
L |
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H |
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L |
L |
X |
X |
H{ |
H{ |
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H |
H |
↑ |
H |
H |
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L |
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H |
H |
↑ |
L |
L |
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H |
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H |
H |
L |
X |
Q0 |
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Q |
0 |
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²This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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74ACT11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCAS498A ± DECEMBER 1986 ± REVISED APRIL 1996
logic symbol²
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1 |
S |
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1PRE |
2 |
1Q |
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14 |
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1CLK |
C1 |
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13 |
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1D |
1D |
3 |
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12 |
1Q |
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1CLR |
R |
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7 |
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2PRE |
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6 |
2Q |
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8 |
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2CLK |
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9 |
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2D |
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5 |
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10 |
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2Q |
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2CLR |
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² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.5 V to 6 |
V |
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±20 mA |
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Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . ±100 mA |
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Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . |
. . . . . . . . . . . . 1.25 W |
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DB package . . . . . . |
. . . . . . . . . . . . . 0.5 W |
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N package . . . . . . . |
. . . . . . . . . . . . . 1.1 W |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . ±65°C to 150°C |
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²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
recommended operating conditions
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MIN |
MAX |
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VCC |
Supply voltage |
4.5 |
5.5 |
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VIH |
High-level input voltage |
2 |
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V |
VIL |
Low-level input voltage |
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0.8 |
V |
VI |
Input voltage |
0 |
VCC |
V |
VO |
Output voltage |
0 |
VCC |
V |
IOH |
High-level output current |
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±24 |
mA |
IOL |
Low-level output current |
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24 |
mA |
Dt/Dv |
Input transition rise or fall rate |
0 |
10 |
ns/V |
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TA |
Operating free-air temperature |
±40 |
85 |
°C |
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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