74ACT11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
SCAS175A ± SEPTEMBER 1991 ± REVISED APRIL 1996
DInputs Are TTL-Voltage Compatible
DDesigned Specifically for High-Speed Memory Decoders and Data Transmission Systems
DIncorporates Two Enable Inputs to Simplify Cascading and/or Data Reception
DFully Synchronous Operation for Counting
DCenter-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
DEPIC (Enhanced-Performance Implanted CMOS) 1- m Process
D, N, OR PW PACKAGE
(TOP VIEW)
1Y1 |
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1 |
16 |
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1Y0 |
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1Y2 |
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2 |
15 |
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1A |
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1Y3 |
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3 |
14 |
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1B |
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GND |
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4 |
13 |
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1G |
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2Y0 |
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5 |
12 |
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VCC |
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2Y1 |
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6 |
11 |
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2G |
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2Y2 |
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7 |
10 |
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2A |
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2Y3 |
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8 |
9 |
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2B |
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D500-mA Typical Latch-Up Immunity at
125°C
DPackage Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)
description
The 74ACT11139 is designed for use in high-performance memory-decoding or data-routing applications that require very short propagation delay times. In high-performance memory systems, this decoder is used to minimize the effects of system decoding.
The 74ACT11139 is composed of two individual 2-line to 4-line decoders in a single package. The active-low enables (1G or 2G) can be used as data lines in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.
The 74ACT11139 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
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B |
A |
Y0 |
Y1 |
Y2 |
Y3 |
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G |
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H |
X |
X |
H |
H |
H |
H |
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L |
L |
L |
L |
H |
H |
H |
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L |
L |
H |
H |
L |
H |
H |
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L |
H |
L |
H |
H |
L |
H |
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L |
H |
H |
H |
H |
H |
L |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
74ACT11139
DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
SCAS175A ± SEPTEMBER 1991 ± REVISED APRIL 1996
logic symbol²
15 |
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DMUX |
0 |
16 |
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1Y0 |
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1A |
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1 |
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0 |
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1 |
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14 |
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G |
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1 |
1Y1 |
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3 |
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1B |
2 |
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2 |
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13 |
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2 |
1Y2 |
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1G |
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3 |
3 |
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1Y3 |
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10 |
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5 |
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2Y0 |
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2A |
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6 |
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9 |
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2Y1 |
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2B |
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7 |
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11 |
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2Y2 |
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2G |
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8 |
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2Y3 |
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² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
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16 |
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1Y0 |
1G |
13 |
1 |
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1Y1 |
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2 |
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15 |
1Y2 |
1A |
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14 |
3 |
1B |
1Y3 |
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5 |
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2Y0 |
2G |
11 |
6 |
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2Y1 |
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7 |
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10 |
2Y2 |
2A |
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9 |
8 |
2B |
2Y3 |
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2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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