AMD Advanced Micro Devices AM29F400BT-90DWI1, AM29F400BT-90DWE1, AM29F400BT-90DWC1, AM29F400BT-90DTI1, AM29F400BT-90DPI1 Datasheet

SUPPLEMENT

Am29F400B Known Good Die

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory—Die Revision 1

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

—5.0 volt-only operation for read, erase, and program operations

—Minimizes system level requirements

■Manufactured on 0.35 µm process technology

—Compatible with 0.5 µm Am29F400 device

■High performance

—Acess time as fast as 70 ns

■Low power consumption (typical values at 5 MHz)

—1 µA standby mode current

—20 mA read current (byte mode)

—28 mA read current (word mode)

—30 mA program/erase current

■Flexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)

—One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)

—Supports full chip erase

—Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sector

Sectors can be locked via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

■Top or bottom boot block configurations available

■Embedded Algorithms

—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors

—Embedded Program algorithm automatically writes and verifies data at specified addresses

■Minimum 1,000,000 write cycle per sector guaranteed

■Compatibility with JEDEC standards

—Pinout and software compatible with single- power-supply Flash

—Superior inadvertent write protection

■Data# Polling and toggle bits

—Provides a software method of detecting program or erase operation completion

■Ready/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completion

■Erase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation

■Hardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

Publication# 21258 Rev: B Amendment/+1

Issue Date: April 1998

S U P P L E M E N T

GENERAL DESCRIPTION

The Am29F400B in Known Good Die (KGD) form is a 4 Mbit, 5.0 volt-only Flash memory. AMD defines KGD as standard product in die form, tested for functionality and speed. AMD KGD products have the same reliability and quality as AMD products in packaged form.

Am29F400B Features

The Am29F400B is a 4 Mbit, 5.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers.

This device is manufactured using AMD’s 0.35 µm process technology, and offers all the features and benefits of the Am29F400, which was manufactured using 0.5 µm process technology.

To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The system can place the device into the standby mode. Power consumption is greatly reduced in this mode.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

ELECTRICAL SPECIFICATIONS

Refer to the Am29F400B data sheet, document number 21505, for full electrical specifications on the Am29F400B in KGD form.

2	Am29F400B Known Good Die

S U P P L E M E N T

PRODUCT SELECTOR GUIDE

Family Part Number				Am29F400B KGD
Speed Option	VCC = 5.0 V ± 5%		-75
	VCC = 5.0 V ± 10%			-90	-120
Max access time, ns (tACC)			70	90	120
Max CE# access time, ns (tCE)			70	90	120
Max OE# access time, ns (tOE)			30	35	50
DIE PHOTOGRAPH		DIE PAD LOCATIONS

Orientation relative to leading edge of tape and reel

9	8	7	6	5	4	3	2	1	43 42 41 40 39 38 37 36	35
10									34
11									33
12									32

AMD logo location

13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Orientation relative to top left corner of

Gel-Pak

Am29F400B Known Good Die

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