FINAL
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS EPROM
■ Fast access time |
■ Single +5 V power supply |
— Speed options as fast as 90 ns |
■ ±10% power supply tolerance standard |
■ Low power consumption |
■ 100% Flashrite programming |
— 100 µA maximum CMOS standby current |
— Typical programming time of 32 seconds |
■ JEDEC-approved pinout |
■ Latch-up protected to 100 mA from –1 V to |
— Plug-in upgrade of 1 Mbit and 2 Mbit EPROMs |
VCC + 1 V |
— 40-pin DIP/PDIP |
■ High noise immunity |
|
|
— 44-pin PLCC |
|
|
|
The Am27C4096 is a 4 Mbit, ultraviolet erasable programmable read-only memory. It is organized as 256 Kwords, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The Am27C4096 is ideal for use in 16-bit microprocessor systems. The device is available in windowed ceramic DIP packages, and plastic one time programmable (OTP) PDIP and PLCC packages.
Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus microprocessor system.
AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 125 mW in active mode, and 125 µW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 µs pulses), resulting in a typical programming time of 32 seconds.
VCC
VSS
VPP
OE# Output Enable
Chip Enable
CE#/PGM# and
Prog Logic
Y
Decoder
A0–A17
Address
Inputs X
Decoder
Data Outputs
DQ0–DQ15
Output
Buffers
Y
Gating
4,194,304 Bit Cell Matrix
11408F-1
Publication# 11408 Rev: F Amendment/0
Issue Date: May 1998
Family Part Number |
|
|
Am27C4096 |
|
|
||
|
|
|
|
|
|
|
|
Speed Options |
VCC = 5.0 V ± 5% |
-95 |
-105 |
|
|
|
-255 |
|
|
|
|
|
|
|
|
VCC = 5.0 V ± 10% |
|
-100 |
-120 |
-150 |
-200 |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
Max Access Time (ns) |
90 |
100 |
120 |
150 |
200 |
250 |
|
|
|
|
|
|
|
|
|
CE# (E#) Access (ns) |
90 |
100 |
120 |
150 |
200 |
250 |
|
|
|
|
|
|
|
|
|
OE# (G#) Access (ns) |
50 |
50 |
50 |
65 |
75 |
75 |
|
|
|
|
|
|
|
|
|
Top View
DIP
VPP |
|
1 |
40 |
VCC |
|
|
|
|
|
CE# (E#)/PGM# (P#) |
|
2 |
39 |
A17 |
|
|
|
|
|
DQ15 |
|
3 |
38 |
A16 |
|
|
|
|
|
DQ14 |
|
4 |
37 |
A15 |
|
|
|
|
|
DQ13 |
|
5 |
36 |
A14 |
|
|
|
|
|
DQ12 |
|
6 |
35 |
A13 |
|
|
|
|
|
DQ11 |
|
7 |
34 |
A12 |
|
|
|
|
|
DQ10 |
|
8 |
33 |
A11 |
DQ9 |
|
|
|
A10 |
|
9 |
32 |
||
DQ8 |
|
|
|
A9 |
|
10 |
31 |
||
VSS |
|
|
|
VSS |
|
11 |
30 |
||
DQ7 |
|
|
|
A8 |
|
12 |
29 |
||
DQ6 |
|
|
|
A7 |
|
13 |
28 |
||
DQ5 |
|
|
|
A6 |
|
14 |
27 |
||
DQ4 |
|
|
|
A5 |
|
15 |
26 |
||
DQ3 |
|
|
|
A4 |
|
16 |
25 |
||
DQ2 |
|
|
|
A3 |
|
17 |
24 |
||
DQ1 |
|
|
|
A2 |
|
18 |
23 |
||
DQ0 |
|
|
|
A1 |
|
19 |
22 |
||
OE# (G#) |
|
|
|
A0 |
|
20 |
21 |
|
|
|
|
|
PLCC |
|
|
|
|
|
||
|
|
|
|
(P#) |
|
|
|
|
|
|
|
|
|
DQ13 |
DQ14 |
DQ15 |
CE#(E#)/PGM# |
V |
DU(Note 2) |
V |
A17 |
A16 |
A15 |
A14 |
|
|
|
|
|
|
PP |
|
CC |
|
|
|
|
|
|
6 |
5 |
4 |
3 |
2 |
1 |
44 43 42 41 40 |
|
||||
DQ12 |
7 |
|
|
|
|
|
|
|
|
|
39 |
A13 |
DQ11 |
8 |
|
|
|
|
|
|
|
|
|
38 |
A12 |
DQ10 |
9 |
|
|
|
|
|
|
|
|
|
37 |
A11 |
DQ9 |
10 |
|
|
|
|
|
|
|
|
|
36 |
A10 |
DQ8 |
11 |
|
|
|
|
|
|
|
|
|
35 |
A9 |
VSS |
12 |
|
|
|
|
|
|
|
|
|
34 |
VSS |
NC |
13 |
|
|
|
|
|
|
|
|
|
33 |
NC |
DQ7 |
14 |
|
|
|
|
|
|
|
|
|
32 |
A8 |
DQ6 |
15 |
|
|
|
|
|
|
|
|
|
31 |
A7 |
DQ5 |
16 |
|
|
|
|
|
|
|
|
|
30 |
A6 |
DQ4 |
17 |
|
|
|
|
|
|
|
|
|
29 |
A5 |
|
18 19 20 21 22 23 24 25 26 27 28 |
|
||||||||||
11408F-2 |
DQ3 |
DQ2 |
DQ1 |
DQ0 |
OE# (G#) |
DU (Note 2) |
A0 |
A1 |
A2 |
A3 |
A4 |
11408F-3 |
Notes:
1.JEDEC nomenclature is in parenthesis.
2.Don’t use (DU) for PLCC.
PIN DESIGNATIONS |
LOGIC SYMBOL |
|||||||||
A0–A17 |
= |
Address Inputs |
18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
CE# (E#)/ |
= |
Chip Enable Input/ |
|
|
|
|
|
|
||
|
|
|
|
A0–A17 |
|
|
|
|||
|
|
|
|
|
|
|
||||
PGM#/ (P#) |
|
Program Enable Input |
|
|
|
|
|
|
|
|
DQ0–DQ15 |
= |
Data Input/Outputs |
|
|
|
|
|
16 |
||
|
|
|
|
DQ0–DQ15 |
|
|
|
|||
OE# (G#) |
= |
Output Enable Input |
|
|
|
|
|
|
|
|
|
|
|
|
CE# (E#)/PGM# (P#) |
|
|
|
|||
VCC |
= |
VCC Supply Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|||
VPP |
= |
Program Voltage Input |
|
|
|
|
OE# (G#) |
|
|
|
VSS |
= Ground |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
11408F-4
2 |
Am27C4096 |
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27C4096 |
-95 |
D |
C |
B |
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
D = 40-Pin Ceramic DIP (CDV040)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS UV EPROM
Valid Combinations
AM27C4096-95 |
DC, DCB |
|
VCC = 5.0 V ± 5% |
||
|
||
AM27C4096-100 |
|
|
|
DC, DCB, DI, DIB |
|
AM27C4096-105 |
||
|
||
VCC = 5.0 V ± 5% |
|
|
AM27C4096-120 |
|
|
|
|
|
AM27C4096-150 |
DC, DCB, DE, DEB, DI, DIB |
|
|
|
|
AM27C4096-200 |
|
|
|
|
|
AM27C4096-255 |
DC, DCB, DI, DIB |
|
VCC = 5.0 V ± 5% |
||
|
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am27C4096 |
3 |
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27C4096 |
-105 |
P |
C |
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
P = 40-Pin Plastic DIP (PD 040)
J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS OTP EPROM
Valid Combinations
AM27C4096-105 |
PC, JC |
|
VCC = 5.0 V ± 5% |
||
|
||
AM27C4096-120 |
|
|
|
|
|
AM27C4096-150 |
|
|
|
PC, PI, JC, JI |
|
AM27C4096-200 |
||
|
||
|
|
|
AM27C4096-255 |
|
|
VCC = 5.0 V ± 5% |
|
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4 |
Am27C4096 |