AMD Advanced Micro Devices Am29SL800CT150WBIB, Am29SL800CT150WBI, Am29SL800CT150WBCB, Am29SL800CT150WBC, Am29SL800CT150FIB Datasheet

PRELIMINARY

Am29SL800C

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 1.8 Volt-only Super Low Voltage Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

—1.8 to 2.2 V for read, program, and erase operations

—Ideal for battery-powered applications

■Manufactured on 0.32 µm process technology

—Compatible with 0.35 µm Am29SL800B device

■High performance

—Access times as fast as 100 ns

■Ultra low power consumption (typical values at 5 MHz)

—65 nA Automatic Sleep Mode current

—65 nA standby mode current

—5 mA read current

—10 mA program/erase current

■Flexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode)

—One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode)

—Supports full chip erase

—Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sector

Sectors can be locked in-system or via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

■Unlock Bypass Program Command

—Reduces overall programming time when issuing multiple program command sequences

■Top or bottom boot block configurations available

■Embedded Algorithms

—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors

—Embedded Program algorithm automatically writes and verifies data at specified addresses

■Minimum 1,000,000 write cycle guarantee per sector

■Package option

—48-pin TSOP

—48-ball FBGA

■Compatibility with JEDEC standards

—Pinout and software compatible with singlepower supply Flash

—Superior inadvertent write protection

■Data# Polling and toggle bits

—Provides a software method of detecting program or erase operation completion

■Ready/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completion

■Erase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation

■Hardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

This document contains information on a product under development at Advanced Micro Devices. The information	Publication# 22230 Rev: A Amendment/0
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed	Issue Date: August 1998
product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29SL800C is an 8 Mbit, 1.8 V volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-pin TSOP and 48ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt VCC supply. No VPP is for write or erase operations. The device can also be programmed in standard EPROM programmers.

The standard device offers access times of 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algo- rithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

2	Am29SL800C

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number		Am29SL800C
Speed Options	100	120	150
Max access time, ns (tACC)	100	120	150
Max CE# access time, ns (tCE)	100	120	150
Max OE# access time, ns (tOE)	35	50	65

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

	RY/BY#					DQ0–DQ15 (A-1)
VCC		Sector Switches
VSS
RESET#		Erase Voltage				Input/Output
		Generator				Buffers
WE#	State
BYTE#	Control
	Command
	Register	PGM Voltage
		Generator
			Chip Enable		STB	Data
						Latch
CE#		Output Enable
OE#				Logic
		STB		Y-Decoder		Y-Gating
	VCC Detector	Timer	Latch
			Address	X-Decoder		Cell Matrix
A0–A18
						22230A-1

Am29SL800C

3

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A15 1

A14 2

A13 3

A12 4

A11 5

A10 6

A9 7

A8 8

NC 9

NC 10

WE# 11

RESET# 12

NC 13

NC 14

RY/BY# 15

A18 16

A17 17

A7 18

A6 19

A5 20

A4 21

A3 22

A2 23

A1 24

A16		1
BYTE#		2
VSS		3
DQ15/A-1		4
DQ7		5
DQ14		6
DQ6		7
DQ13		8
DQ5		9
DQ12		10
DQ4		11
VCC		12
DQ11		13
DQ3		14
DQ10		15
DQ2		16
DQ9		17
DQ1		18
DQ8		19
DQ0		20
OE#		21
VSS		22
CE#		23
A0		24

	48		A16
	47		BYTE#
	46		VSS
	45		DQ15/A-1
	44		DQ7
	43		DQ14
	42		DQ6
	41		DQ13
	40		DQ5
	39		DQ12
	38		DQ4
Standard TSOP	37		VCC
	36		DQ11
	35		DQ3
	34		DQ10
	33		DQ2
	32		DQ9
	31		DQ1
	30		DQ8
	29		DQ0
	28		OE#
	27		VSS
	26		CE#
	25		A0

	48		A15
	47		A14
	46		A13
	45		A12
	44		A11
	43		A10
	42		A9
	41		A8
	40		NC
	39		NC
	38		WE#
Reverse TSOP	37		RESET#
	36		NC
	35		NC
	34		RY/BY#
	33		A18
	32		A17
	31		A7
	30		A6
	29		A5
	28		A4
	27		A3
	26		A2
	25		A1

22230A-2

4	Am29SL800C

P R E L I M I N A R Y

CONNECTION DIAGRAMS

		48-Ball FBGA (Bottom View)
A1	B1	C1	D1	E1	F1	G1	H1
A3	A4	A2	A1	A0	CE#	OE#	VSS
A2	B2	C2	D2	E2	F2	G2	H2
A7	A17	A6	A5	DQ0	DQ8	DQ9	DQ1
A3	B3	C3	D3	E3	F3	G3	H3
RY/BY#	NC	A18	NC	DQ2	DQ10	DQ11	DQ3
A4	B4	C4	D4	E4	F4	G4	H4
WE#	RESET#	NC	NC	DQ5	DQ12	VCC	DQ4
A5	B5	C5	D5	E5	F5	G5	H5
A9	A8	A10	A11	DQ7	DQ14	DQ13	DQ6
A6	B6	C6	D6	E6	F6	G6	H6
A13	A12	A14	A15	A16	BYTE#	DQ15/A-1	VSS

22230A-3

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

Am29SL800C

5

BYTE#

CE#

OE#

WE#

RESET#

RY/BY# VCC VSS

NC

6

P R E L I M I N A R Y

PIN CONFIGURATION

A0–A18 = 19 addresses

DQ0–DQ14 = 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)

= Selects 8-bit or 16-bit mode = Chip enable

= Output enable = Write enable

= Hardware reset pin, active low = Ready/Busy# output

= 1.8–2.2 V single power supply = Device ground

= Pin not connected internally

LOGIC SYMBOL

	19			A0–A18		16 or 8
					DQ0–DQ15
				CE#	(A-1)
				OE#
				WE#
				RESET#
				BYTE#	RY/BY#

22230A-4

Am29SL800C

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29SL800C T

100

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I	= Industrial (–40°C to +85°C)
PACKAGE TYPE
E	= 48-Pin Thin Small Outline Package (TSOP)
	Standard Pinout (TS 048)
F	= 48-Pin Thin Small Outline Package (TSOP)
	Reverse Pinout (TSR048)

WB = 48-ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 9 mm package

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29SL800C

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations

Am29SL800CT100,

Am29SL800CB100

Am29SL800CT120,

EC, EI, FC, FI, WBC, WBI

Am29SL800CB120

Am29SL800CT150,

Am29SL800CB150

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am29SL800C

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P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Am29SL800C Device Bus Operations

								DQ8–DQ15
					Addresses	DQ0–	BYTE#	BYTE#
Operation	CE#	OE#	WE#	RESET#	(Note 1)	DQ7	= VIH	= VIL
Read	L	L	H	H	AIN	DOUT	DOUT	DQ8–DQ14 = High-Z,
Write	L	H	L	H	AIN	DIN	DIN	DQ15 = A-1
Standby	VCC ±	X	X	VCC ±	X	High-Z	High-Z	High-Z
	0.3 V			0.3 V
Output Disable	L	H	H	H	X	High-Z	High-Z	High-Z
Reset	X	X	X	L	X	High-Z	High-Z	High-Z
					Sector Address,
Sector Protect (Note 2)	L	H	L	VID	A6 = L, A1 = H,	DIN	X	X
					A0 = L
					Sector Address,
Sector Unprotect (Note 2)	L	H	L	VID	A6 = H, A1 = H,	DIN	X	X
					A0 = L
Temporary Sector Unprotect	X	X	X	VID	AIN	DIN	DIN	High-Z

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1.Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).

2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

8	Am29SL800C

P R E L I M I N A R Y

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

ICC3 in the DC Characteristics table represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 50 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws

CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the

reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data

tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Am29SL800C

9

P R E L I M I N A R Y

Table 2. Am29SL800CT Top Boot Block Sector Address Table

								Sector Size	Address Range (in hexadecimal)
								(Kbytes/	(x8)	(x16)
Sector	A18	A17	A16	A15	A14	A13	A12	Kwords)	Address Range	Address Range
SA0	0	0	0	0	X	X	X	64/32	00000h–0FFFFh	00000h–07FFFh
SA1	0	0	0	1	X	X	X	64/32	10000h–1FFFFh	08000h–0FFFFh
SA2	0	0	1	0	X	X	X	64/32	20000h–2FFFFh	10000h–17FFFh
SA3	0	0	1	1	X	X	X	64/32	30000h–3FFFFh	18000h–1FFFFh
SA4	0	1	0	0	X	X	X	64/32	40000h–4FFFFh	20000h–27FFFh
SA5	0	1	0	1	X	X	X	64/32	50000h–5FFFFh	28000h–2FFFFh
SA6	0	1	1	0	X	X	X	64/32	60000h–6FFFFh	30000h–37FFFh
SA7	0	1	1	1	X	X	X	64/32	70000h–7FFFFh	38000h–3FFFFh
SA8	1	0	0	0	X	X	X	64/32	80000h–8FFFFh	40000h–47FFFh
SA9	1	0	0	1	X	X	X	64/32	90000h–9FFFFh	48000h–4FFFFh
SA10	1	0	1	0	X	X	X	64/32	A0000h–AFFFFh	50000h–57FFFh
SA11	1	0	1	1	X	X	X	64/32	B0000h–BFFFFh	58000h–5FFFFh
SA12	1	1	0	0	X	X	X	64/32	C0000h–CFFFFh	60000h–67FFFh
SA13	1	1	0	1	X	X	X	64/32	D0000h–DFFFFh	68000h–6FFFFh
SA14	1	1	1	0	X	X	X	64/32	E0000h–EFFFFh	70000h–77FFFh
SA15	1	1	1	1	0	X	X	32/16	F0000h–F7FFFh	78000h–7BFFFh
SA16	1	1	1	1	1	0	0	8/4	F8000h–F9FFFh	7C000h–7CFFFh
SA17	1	1	1	1	1	0	1	8/4	FA000h–FBFFFh	7D000h–7DFFFh
SA18	1	1	1	1	1	1	X	16/8	FC000h–FFFFFh	7E000h–7FFFFh

10	Am29SL800C

P R E L I M I N A R Y

Table 3. Am29SL800CB Bottom Boot Block Sector Address Table

								Sector Size	Address Range (in hexadecimal)
								(Kbytes/	(x8)	(x16)
Sector	A18	A17	A16	A15	A14	A13	A12	Kwords)	Address Range	Address Range
SA0	0	0	0	0	0	0	X	16/8	00000h–03FFFh	00000h–01FFFh
SA1	0	0	0	0	0	1	0	8/4	04000h–05FFFh	02000h–02FFFh
SA2	0	0	0	0	0	1	1	8/4	06000h–07FFFh	03000h–03FFFh
SA3	0	0	0	0	1	X	X	32/16	08000h–0FFFFh	04000h–07FFFh
SA4	0	0	0	1	X	X	X	64/32	10000h–1FFFFh	08000h–0FFFFh
SA5	0	0	1	0	X	X	X	64/32	20000h–2FFFFh	10000h–17FFFh
SA6	0	0	1	1	X	X	X	64/32	30000h–3FFFFh	18000h–1FFFFh
SA7	0	1	0	0	X	X	X	64/32	40000h–4FFFFh	20000h–27FFFh
SA8	0	1	0	1	X	X	X	64/32	50000h–5FFFFh	28000h–2FFFFh
SA9	0	1	1	0	X	X	X	64/32	60000h–6FFFFh	30000h–37FFFh
SA10	0	1	1	1	X	X	X	64/32	70000h–7FFFFh	38000h–3FFFFh
SA11	1	0	0	0	X	X	X	64/32	80000h–8FFFFh	40000h–47FFFh
SA12	1	0	0	1	X	X	X	64/32	90000h–9FFFFh	48000h–4FFFFh
SA13	1	0	1	0	X	X	X	64/32	A0000h–AFFFFh	50000h–57FFFh
SA14	1	0	1	1	X	X	X	64/32	B0000h–BFFFFh	58000h–5FFFFh
SA15	1	1	0	0	X	X	X	64/32	C0000h–CFFFFh	60000h–67FFFh
SA16	1	1	0	1	X	X	X	64/32	D0000h–DFFFFh	68000h–6FFFFh
SA17	1	1	1	0	X	X	X	64/32	E0000h–EFFFFh	70000h–77FFFh
SA18	1	1	1	1	X	X	X	64/32	F0000h–FFFFFh	78000h–7FFFFh

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.

Am29SL800C

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P R E L I M I N A R Y

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition,

when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.

Table 4. Am29SL800C Autoselect Codes (High Voltage Method)

A18

A11

A8

A5

DQ8

DQ7

to

to

to

to

to

to

Description

Mode

CE#

OE#

WE#

A12

A10

A9

A7

A6

A2

A1

A0

DQ15

DQ0

Manufacturer ID: AMD

L

L

H

X

X

VID

X

L

X

L

L

X

01h

Device ID:

Word

L

L

H

22h

EAh

Am29SL800C

X

X

VID

X

L

X

L

H

Byte

L

L

H

X

EAh

(Top Boot Block)

Device ID:

Word

L

L

H

22h

6Bh

Am29SL800C

X

X

VID

X

L

X

L

H

Byte

L

L

H

X

6Bh

(Bottom Boot Block)

X

01h

(protected)

Sector Protection Verification

L

L

H

SA

X

VID

X

L

X

H

L

X

00h

(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods.

The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 1 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle.

The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 21622 contains further details. Contact

an AMD representative to request the document containing further details.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature.

12	Am29SL800C

			P R E L I M I N A R Y
		START		START
		PLSCNT = 1	Protect all sectors:	PLSCNT = 1
			The indicated portion
			of the sector protect
		RESET# = V	algorithm must be	RESET# = VID
		ID	performed for all
		Wait 1 μs	unprotected sectors	Wait 1 μs
			prior to issuing the
			first sector
	No		unprotect address	First Write	No
Temporary Sector		First Write
				Cycle = 60h?	Temporary Sector
Unprotect Mode		Cycle = 60h?			Unprotect Mode
		Yes		Yes
		Set up sector	No	All sectors
		address
				protected?
		Sector Protect:		Yes
		Write 60h to sector
		address with		Set up first sector
		A6 = 0, A1 = 1,
				address
		A0 = 0
		Wait 150 µs		Sector Unprotect:
				Write 60h to sector
				address with
		Verify Sector		A6 = 1, A1 = 1,
		Protect: Write 40h		A0 = 0
Increment		to sector address	Reset
		with A6 = 0,	PLSCNT = 1	Wait 15 ms
PLSCNT		A1 = 1, A0 = 0
		Read from		Verify Sector
				Unprotect: Write
		sector address
				40h to sector
		with A6 = 0,
				address with
		A1 = 1, A0 = 0	Increment
				A6 = 1, A1 = 1,
No
			PLSCNT
				A0 = 0
	No
PLSCNT		Data = 01h?		Read from
= 25?				sector address
				with A6 = 1,
Yes		Yes	No	A1 = 1, A0 = 0
					Set up
		Yes	No		next sector
					address
Device failed		Protect another	PLSCNT	Data = 00h?
		sector?	= 1000?
		No	Yes	Yes
		Remove VID			No
		from RESET#	Device failed	Last sector
				verified?
		Write reset		Yes
		command
Sector Protect			Sector Unprotect	Remove VID
		Sector Protect		from RESET#
Algorithm		complete	Algorithm
				Write reset
				command
				Sector Unprotect
				complete

22230A-5

Figure 1. In-System Sector Protect/Unprotect Algorithms

Am29SL800C

13