AMD Advanced Micro Devices AM29F800BT-90SEB, AM29F800BT-90SE, AM29F800BT-90SCB, AM29F800BT-90SC, AM29F800BT-90FIB Datasheet

PRELIMINARY

Am29F800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

—5.0 Volt-only operation for read, erase, and program operations

—Minimizes system level requirements

■Manufactured on 0.35 µm process technology

—Compatible with 0.5 µm Am29F800 device

■High performance

—Access times as fast as 55 ns

■Low power consumption (typical values at 5 MHz)

—1 µA standby mode current

—20 mA read current (byte mode)

—28 mA read current (word mode)

—30 mA program/erase current

■Flexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode)

—One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode)

—Supports full chip erase

—Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sector

Sectors can be locked via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

■Top or bottom boot block configurations available

■Embedded Algorithms

—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors

—Embedded Program algorithm automatically writes and verifies data at specified addresses

■Minimum 1,000,000 program/erase cycles per sector guaranteed

■Package option

—48-pin TSOP

—44-pin SO

■Compatibility with JEDEC standards

—Pinout and software compatible with single- power-supply Flash

—Superior inadvertent write protection

■Data# Polling and toggle bits

—Provides a software method of detecting program or erase operation completion

■Ready/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completion

■Erase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation

■Hardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

Publication# 21504 Rev: C Amendment/+1

Issue Date: April 1998

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29F800B is an 8 Mbit, 5.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7– DQ0. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers.

This device is manufactured using AMD’s 0.35 µm process technology, and offers all the features and benefits of the Am29F800, which was manufactured using 0.5 µm process technology.

The standard device offers access times of 55, 70, 90, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The system can place the device into the standby mode. Power consumption is greatly reduced in this mode.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all b i t s w i t h i n a s e c t o r s i m u l t a n e o u s l y v i a F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s programmed using hot electron injection.

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Am29F800B

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number				Am29F800B
Speed Option	VCC = 5.0 V ± 5%	-55
	VCC = 5.0 V ± 10%		-70	-90	-120	-150
Max access time, ns (tACC)		55	70	90	120	150
Max CE# access time, ns (tCE)		55	70	90	120	150
Max OE# access time, ns (tOE)		30	30	35	50	55

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

	RY/BY#					DQ0–DQ15 (A-1)
VCC			Sector Switches
VSS
RESET#			Erase Voltage			Input/Output
			Generator			Buffers
WE#	State
BYTE#	Control
	Command
	Register	PGM Voltage
		Generator
			Chip Enable		STB	Data
						Latch
CE#			Output Enable
OE#				Logic
			STB	Y-Decoder		Y-Gating
	VCC Detector	Timer	Latch
			Address	X-Decoder		Cell Matrix
A0–A18
						21504C-1

Am29F800B

3

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A15			1		48			A16
A14			2		47			BYTE#
A13			3		46			VSS
A12			4		45			DQ15/A-1
A11			5		44			DQ7
A10			6		43			DQ14
A9			7		42			DQ6
A8			8		41			DQ13
NC			9		40			DQ5
NC			10		39			DQ12
WE#			11		38			DQ4
RESET#			12		37			VCC
NC			13		36			DQ11
NC			14		35			DQ3
RY/BY#			15		34			DQ10
A18			16		33			DQ2
A17			17		32			DQ9
A7			18		31			DQ1
A6			19		30			DQ8
A5			20		29			DQ0
A4			21		28			OE#
A3			22		27			VSS
A2			23		26			CE#
A1			24		25			A0
					48-Pin TSOP—Standard Pinout
A16				1	48			A15
BYTE#				2	47			A14
VSS				3	46			A13
DQ15/A-1				4	45			A12
DQ7				5	44			A11
DQ14				6	43			A10
DQ6				7	42			A9
DQ13				8	41			A8
DQ5				9	40			NC
DQ12				10	39			NC
DQ4				11	38			WE#
VCC				12	37			RESET#
DQ11				13	36			NC
DQ3				14	35			NC
DQ10				15	34			RY/BY#
DQ2				16	33			A18
DQ9				17	32			A17
DQ1				18	31			A7
DQ8				19	30			A6
DQ0				20	29			A5
OE#				21	28			A4
VSS				22	27			A3
CE#				23	26			A2
A0				24	25			A1

48-Pin TSOP—Reverse Pinout

21504C-2

4

Am29F800B

P R E L I M I N A R Y

CONNECTION DIAGRAMS

SO

RY/BY#	1				44	RESET#
A18	2				43	WE#
A17	3				42	A8
A7	4				41	A9
A6	5				40	A10
A5	6				39	A11
A4	7				38	A12
A3	8				37	A13
A2	9				36	A14
A1	10				35	A15
A0	11				34	A16
CE# 12					33	BYTE#
VSS 13					32	VSS
OE# 14					31	DQ15/A-1
DQ0 15					30	DQ7
DQ8 16					29	DQ14
DQ1 17					28	DQ6
DQ9 18					27	DQ13
DQ2 19					26	DQ5
DQ10 20					25	DQ12
DQ3 21					24	DQ4
DQ11 22					23	VCC

21504C-3

PIN CONFIGURATION

A0–A18 = 19 addresses

DQ0–DQ14 = 15 data inputs/outputs

DQ15/A-1	= DQ15 (data input/output, word mode),
		A-1 (LSB address input, byte mode)
BYTE#	= Selects 8-bit or 16-bit mode
CE#	=	Chip enable
OE#	=	Output enable
WE#	=	Write enable
RESET#	= Hardware reset pin, active low
RY/BY#	=	Ready/Busy# output
VCC	= +5.0 V single power supply
		(see Product Selector Guide for
		device speed ratings and voltage
		supply tolerances)
VSS	=	Device ground
NC	= Pin not connected internally

LOGIC SYMBOL

	19			A0–A18		16 or 8
					DQ0–DQ15
				CE#	(A-1)
				OE#
				WE#
				RESET#
				BYTE#	RY/BY#

21504C-4

Am29F800B

5

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29F800B

T

-70

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I	= Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E	= 48-Pin Thin Small Outline Package (TSOP)
	Standard Pinout (TS 048)
F	= 48-Pin Thin Small Outline Package (TSOP)
	Reverse Pinout (TSR048)
S	= 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29F800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program, and Erase

Valid Combinations

	Am29F800BT-55,	EC, EI, FC, FI, SC, SI
	Am29F800BB-55
	Am29F800BT-70,
	Am29F800BB-70
	Am29F800BT-90,	EC, EI, EE,
	Am29F800BB-90
		FC, FI, FE,
	Am29F800BT-120,
		SC, SI, SE
	Am29F800BB-120
	Am29F800BT-150,
	Am29F800BB-150

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

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Am29F800B

P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Am29F800B Device Bus Operations

							DQ8–DQ15
							BYTE#	BYTE#
Operation	CE#	OE#	WE#	RESET#	A0–A18	DQ0–DQ7	= VIH	= VIL
Read	L	L	H	H	AIN	DOUT	DOUT	High-Z
Write	L	H	L	H	AIN	DIN	DIN	High-Z
CMOS Standby	VCC ± 0.5 V	X	X	VCC ± 0.5 V	X	High-Z	High-Z	High-Z
TTL Standby	H	X	X	H	X	High-Z	High-Z	High-Z
Output Disable	L	H	H	H	X	High-Z	High-Z	High-Z
Hardware Reset	X	X	X	L	X	High-Z	High-Z	High-Z
Temporary Sector Unprotect	X	X	X	VID	AIN	DIN	DIN	X
(See Note)

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In

Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

Am29F800B

7

P R E L I M I N A R Y

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Characteristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.

In the DC Characteristics tables, ICC3 represents the standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VIL, the device enters the TTL standby mode; if RESET# is held at VSS ± 0.5 V, the device enters the CMOS standby mode.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RE-

SET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# parameters and timing diagram.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

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Am29F800B

P R E L I M I N A R Y

Table 2. Am29F800BT Top Boot Block Sector Address Table

								Sector Size	Address Range (in hexadecimal)
								(Kbytes/	(x16)	(x8)
Sector	A18	A17	A16	A15	A14	A13	A12	Kwords)	Address Range	Address Range
SA0	0	0	0	0	X	X	X	64/32	00000h–07FFFh	00000h–0FFFFh
SA1	0	0	0	1	X	X	X	64/32	08000h–0FFFFh	10000h–1FFFFh
SA2	0	0	1	0	X	X	X	64/32	10000h–17FFFh	20000h–2FFFFh
SA3	0	0	1	1	X	X	X	64/32	18000h–1FFFFh	30000h–3FFFFh
SA4	0	1	0	0	X	X	X	64/32	20000h–27FFFh	40000h–4FFFFh
SA5	0	1	0	1	X	X	X	64/32	28000h–2FFFFh	50000h–5FFFFh
SA6	0	1	1	0	X	X	X	64/32	30000h–37FFFh	60000h–6FFFFh
SA7	0	1	1	1	X	X	X	64/32	38000h–3FFFFh	70000h–7FFFFh
SA8	1	0	0	0	X	X	X	64/32	40000h–47FFFh	80000h–8FFFFh
SA9	1	0	0	1	X	X	X	64/32	48000h–4FFFFh	90000h–9FFFFh
SA10	1	0	1	0	X	X	X	64/32	50000h–57FFFh	A0000h–AFFFFh
SA11	1	0	1	1	X	X	X	64/32	58000h–5FFFFh	B0000h–BFFFFh
SA12	1	1	0	0	X	X	X	64/32	60000h–67FFFh	C0000h–CFFFFh
SA13	1	1	0	1	X	X	X	64/32	68000h–6FFFFh	D0000h–DFFFFh
SA14	1	1	1	0	X	X	X	64/32	70000h–77FFFh	E0000h–EFFFFh
SA15	1	1	1	1	0	X	X	32/16	78000h–7BFFFh	F0000h–F7FFFh
SA16	1	1	1	1	1	0	0	8/4	7C000h–7CFFFh	F8000h–F9FFFh
SA17	1	1	1	1	1	0	1	8/4	7D000h–7DFFFh	FA000h–FBFFFh
SA18	1	1	1	1	1	1	X	16/8	7E000h–7FFFFh	FC000h–FFFFFh

Note:

Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.

Am29F800B

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P R E L I M I N A R Y

Table 3. Am29F800BB Bottom Boot Block Sector Address Table

								Sector Size	Address Range (in hexadecimal)
								(Kbytes/	(x16)	(x8)
Sector	A18	A17	A16	A15	A14	A13	A12	Kwords)	Address Range	Address Range
SA0	0	0	0	0	0	0	X	16/8	00000h–01FFFh	00000h–03FFFh
SA1	0	0	0	0	0	1	0	8/4	02000h–02FFFh	04000h–05FFFh
SA2	0	0	0	0	0	1	1	8/4	03000h–03FFFh	06000h–07FFFh
SA3	0	0	0	0	1	X	X	32/16	04000h–07FFFh	08000h–0FFFFh
SA4	0	0	0	1	X	X	X	64/32	08000h–0FFFFh	10000h–1FFFFh
SA5	0	0	1	0	X	X	X	64/32	10000h–17FFFh	20000h–2FFFFh
SA6	0	0	1	1	X	X	X	64/32	18000h–1FFFFh	30000h–3FFFFh
SA7	0	1	0	0	X	X	X	64/32	20000h–27FFFh	40000h–4FFFFh
SA8	0	1	0	1	X	X	X	64/32	28000h–2FFFFh	50000h–5FFFFh
SA9	0	1	1	0	X	X	X	64/32	30000h–37FFFh	60000h–6FFFFh
SA10	0	1	1	1	X	X	X	64/32	38000h–3FFFFh	70000h–7FFFFh
SA11	1	0	0	0	X	X	X	64/32	40000h–47FFFh	80000h–8FFFFh
SA12	1	0	0	1	X	X	X	64/32	48000h–4FFFFh	90000h–9FFFFh
SA13	1	0	1	0	X	X	X	64/32	50000h–57FFFh	A0000h–AFFFFh
SA14	1	0	1	1	X	X	X	64/32	58000h–5FFFFh	B0000h–BFFFFh
SA15	1	1	0	0	X	X	X	64/32	60000h–67FFFh	C0000h–CFFFFh
SA16	1	1	0	1	X	X	X	64/32	68000h–6FFFFh	D0000h–DFFFFh
SA17	1	1	1	0	X	X	X	64/32	70000h–77FFFh	E0000h–EFFFFh
SA18	1	1	1	1	X	X	X	64/32	78000h–7FFFFh	F0000h–FFFFFh

Note:

Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.

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P R E L I M I N A R Y

Table 4. Am29F800B Autoselect Codes (High Voltage Method)

A18

A11

A8

A5

DQ8

DQ7

to

to

to

to

to

to

Description

Mode

CE#

OE#

WE#

A12

A10

A9

A7

A6

A2

A1

A0

DQ15

DQ0

Manufacturer ID: AMD

L

L

H

X

X

VID

X

L

X

L

L

X

01h

Device ID:

Word

L

L

H

22h

D6h

Am29F800B

X

X

VID

X

L

X

L

H

Byte

L

L

H

X

D6h

(Top Boot Block)

Device ID:

Word

L

L

H

22h

58h

Am29F800B

X

X

VID

X

L

X

L

H

Byte

L

L

H

X

58h

(Bottom Boot Block)

X

01h

(protected)

Sector Protection Verification

L

L

H

SA

X

VID

X

L

X

H

L

X

00h

(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 20374. Contact an AMD representative to obtain a copy of the appropriate document.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram shows the timing waveforms, for this feature.

START

RESET# = VID

(Note 1)

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect

Completed (Note 2)

21504C-5

Notes:

1.All protected sectors unprotected.

2.All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

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P R E L I M I N A R Y

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the

proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.

The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame-

ters, and Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

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