AMD Advanced Micro Devices AM29LV004T-90RFIB, AM29LV004T-90RFEB, AM29LV004T-90RFCB, AM29LV004T-90RFC, AM29LV004T-90REIB Datasheet

PRELIMINARY

Am29LV004

4 Megabit (512 K x 8-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

—Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications

—Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors

■High performance

—Full voltage range: access times as fast as 100 ns

—Regulated voltage range: access times as fast as 90 ns

■Ultra low power consumption (typical values at 5 MHz)

—200 nA Automatic Sleep mode current

—200 nA standby mode current

—10 mA read current

—20 mA program/erase current

■Flexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors

—Supports full chip erase

—Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sector

Sectors can be locked via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

■Top or bottom boot block configurations available

■Embedded Algorithms

—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors

—Embedded Program algorithm automatically writes and verifies data at specified addresses

■Typical 1,000,000 write cycles per sector (100,000 cycles minimum guaranteed)

■Package option

—40-pin TSOP

■Compatibility with JEDEC standards

—Pinout and software compatible with singlepower supply Flash

—Superior inadvertent write protection

■Data# Polling and toggle bits

—Provides a software method of detecting program or erase operation completion

■Ready/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completion

■Erase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation

■Hardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

This document contains information on a product under development at Advanced Micro Devices. The information	Publication# 20510 Rev: D Amendment/+1
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed	Issue Date: March 1998
product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29LV004 is an 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes. The device is offered in a 40-pin TSOP package. The byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algo- rithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

2

Am29LV004

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number			Am29LV004
Speed Options	Regulated Voltage Range: VCC =3.0–3.6 V	-90R
	Full Voltage Range: VCC = 2.7–3.6 V		-100	-120	-150
Max access time, ns (tACC)		90	100	120	150
Max CE# access time, ns (tCE)		90	100	120	150
Max OE# access time, ns (tOE)		40	40	40	55

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

	RY/BY#					DQ0–DQ7
VCC		Sector Switches
VSS
RESET#		Erase Voltage				Input/Output
		Generator				Buffers
WE#	State
	Control
	Command
	Register	PGM Voltage
		Generator
			Chip Enable		STB	Data
CE#		Output Enable				Latch
OE#				Logic
		STB		Y-Decoder		Y-Gating
	VCC Detector	Timer	Latch
			Address	X-Decoder		Cell Matrix
A0–A18
						21522A-1

Am29LV004

3

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A16 1

A15 2

A14 3

A13 4

A12 5

A11 6

A9 7

A8 8

WE# 9 RESET# 10

NC 11 RY/BY# 12 A18 13 A7 14 A6 15 A5 16 A4 17 A3 18 A2 19 A1 20

A17 1

VSS 2

NC 3

NC 4

A10 5

DQ7 6

DQ6 7

DQ5 8

DQ4 9

VCC 10

VCC 11

NC 12

DQ3 13

DQ2 14

DQ1 15

DQ0 16

CE# 17

VSS 18

CE# 19

A0 20

Standard TSOP

Reverse TSOP

40 A17

39 VSS

38 NC

37 NC

36 A10

35 DQ7

34 DQ6

33 DQ5

32 DQ4

31 VCC

30 VCC

29 NC

28 DQ3

27 DQ2

26 DQ1

25 DQ0

24 OE#

23 VSS

22 CE#

21 A0

40 A16

39 A15

38 A14

37 A13

36 A12

35 A11

34 A9

33 A8

32 WE#

31 RESET#

30 NC

29 RY/BY#

28 A18

27 A7

26 A6

25 A5

24 A4

23 A3

22 A2

21 A1

21522A-2

4

Am29LV004

P R E L I M I N A R Y

PIN CONFIGURATION

A0–A18	=	19 addresses
DQ0–DQ7	=	8 data inputs/outputs
CE#	=	Chip enable
OE#	=	Output enable
WE#	=	Write enable
RESET#	= Hardware reset pin, active low
RY/BY#	=	Ready/Busy# output
VCC	= 3.0 volt-only single power supply
		(see Product Selector Guide for speed
		options and voltage supply tolerances)
VSS	=	Device ground
NC	= Pin not connected internally

LOGIC SYMBOL

19
A0–A18	8

DQ0–DQ7

CE#

OE#

WE#

RESET#

RY/BY#

21522A-3

Am29LV004

5

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29LV004

T

-90R

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I	= Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E	= 40-Pin Thin Small Outline Package (TSOP)
	Standard Pinout (TS 040)
F	= 40-Pin Thin Small Outline Package (TSOP)
	Reverse Pinout (TSR040)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV004

4 Megabit (512 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Am29LV004T-70R,

EC, EI, FC, FI

Am29LV004B-70R

Am29LV004T-80,

Am29LV004B-80

Am29LV004T-90,

EC, EI, EE, FC, FI, FE

Am29LV004B-90

Am29LV004T-120,

Am29LV004B-120

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

6

Am29LV004

P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the

register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Am29LV004 Device Bus Operations

Operation	CE#		OE#	WE#	RESET#	Addresses (See Note)	DQ0–DQ7
Read	L		L	H	H	AIN	DOUT
Write	L		H	L	H	AIN	DIN
Standby	VCC ±		X	X	VCC ±	X	High-Z
	0.3	V			0.3 V
Output Disable	L		H	H	H	X	High-Z
Reset	X		X	X	L	X	High-Z
Temporary Sector Unprotect	X		X	X	VID	AIN	DIN

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Note: Addresses are A18–A0.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 12 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.

Am29LV004

7

P R E L I M I N A R Y

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

In the DC Characteristics tables, ICC3 and ICC4 represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is

completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after

the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

8

Am29LV004

P R E L I M I N A R Y

Table 2. Am29LV004T Top Boot Block Sector Address Table

							Sector Size	Address Range
Sector	A18	A17	A16	A15	A14	A13	(Kbytes)	(in hexadecimal)
SA0	0	0	0	X	X	X	64	00000h-0FFFFh
SA1	0	0	1	X	X	X	64	10000h-1FFFFh
SA2	0	1	0	X	X	X	64	20000h-2FFFFh
SA3	0	1	1	X	X	X	64	30000h-3FFFFh
SA4	1	0	0	X	X	X	64	40000h-4FFFFh
SA5	1	0	1	X	X	X	64	50000h-5FFFFh
SA6	1	1	0	X	X	X	64	60000h-6FFFFh
SA7	1	1	1	0	X	X	32	70000h-77FFFh
SA8	1	1	1	1	0	0	8	78000h-79FFFh
SA9	1	1	1	1	0	1	8	7A000h-7BFFFh
SA10	1	1	1	1	1	X	16	7C000h-7FFFFh

Table 3. Am29LV004B Bottom Boot Block Sector Address Table

							Sector Size	Address Range
Sector	A18	A17	A16	A15	A14	A13	(Kbytes)	(in hexadecimal)
SA0	0	0	0	0	0	X	16	00000h-03FFFh
SA1	0	0	0	0	1	0	8	04000h-05FFFh
SA2	0	0	0	0	1	1	8	06000h-07FFFh
SA3	0	0	0	1	X	X	32	08000h-0FFFFh
SA4	0	0	1	X	X	X	64	10000h-1FFFFh
SA5	0	1	0	X	X	X	64	20000h-2FFFFh
SA6	0	1	1	X	X	X	64	30000h-3FFFFh
SA7	1	0	0	X	X	X	64	40000h-4FFFFh
SA8	1	0	1	X	X	X	64	50000h-5FFFFh
SA9	1	1	0	X	X	X	64	60000h-6FFFFh
SA10	1	1	1	X	X	X	64	70000h-7FFFFh

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sec-

tor address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.

Am29LV004

9

P R E L I M I N A R Y

Table 4. Am29LV004 Autoselect Codes (High Voltage Method)

A18

A12

A8

A5

DQ7

to

to

to

to

to

Description

CE#

OE#

WE#

A13

A10

A9

A7

A6

A2

A1

A0

DQ0

Manufacturer ID: AMD

L

L

H

X

X

VID

X

L

X

L

L

01h

Device ID: Am29LV004T

L

L

H

X

X

VID

X

L

X

L

H

B5h

(Top Boot Block)

Device ID: Am29LV004B

L

L

H

X

X

VID

X

L

X

L

H

B6h

(Bottom Boot Block)

01h

Sector Protection Verification

L

L

H

SA

X

VID

X

L

X

H

L

(protected)

00h

(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

Sector protection/unprotection must be implemented using programming equipment.The procedure requires a high voltage (VID) on address pin A9 and OE#. Details on this method are provided in a supplement, publication number 20874. Contact an AMD representative to request a copy.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RE-

SET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 19 shows the timing diagrams, for this feature.

START

RESET# = VID

(Note 1)

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

21522A-4

Notes:

1.All protected sectors unprotected.

2.All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

10

Am29LV004

P R E L I M I N A R Y

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.

The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

Am29LV004

11