AMD Advanced Micro Devices AM28F256-90JEB, AM28F256-90JE, AM28F256-90JCB, AM28F256-90JC, AM28F256-90FIB Datasheet

FINAL

Am28F256

256 Kilobit (32 K x 8-Bit)

CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

■High performance

—70 ns maximum access time

■CMOS Low power consumption

—30 mA maximum active current

—100 µA maximum standby current

—No data retention power consumption

■Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts

—32-pin PDIP

—32-pin PLCC

—32-pin TSOP

■10,000 write/erase cycles minimum

■Write and erase voltage 12.0 V ±5%

■Latch-up protected to 100 mA from –1 V to V CC +1 V

■Flasherase Electrical Bulk Chip-Erase

—One second typical chip-erase

■Flashrite Programming

—10 µs typical byte-program

—0.5 second typical chip program

■Command register architecture for microprocessor/microcontroller compatible write interface

■On-chip address and data latches

■Advanced CMOS flash memory technology

—Low cost single transistor memory cell

■Automatic write/erase pulse stop timer

GENERAL DESCRIPTION

The Am28F256 is a 256 K Flash memory organized as 32 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory. The Am28F256 is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F256 is erased when shipped from the factory.

The standard Am28F256 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F256 has separate chip enable (CE#) and output enable (OE#) controls.

AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F256 uses a command register to manage this functionality, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming.

AMD’s Flash technology reliably stores memory contents even after 10,000 erase and program cycles.

The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The Am28F256 uses a 12.0V ± 5% VPP high voltage input to perform the Flasherase and Flashrite algorithms.

The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from –1 V to VCC +1 V.

The Am28F256 is byte programmable using 10 µs programming pulses in accordance with AMD’s Flashrite programming algorithm. The typical room temperature programming time of the Am28F256 is a half a second. The entire chip is bulk erased using 10 ms erase pulses according to AMD’s Flasherase alrogithm. Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 15-20 minutes required for EPROM erasure using ultra-violet light are eliminated.

Publication# 11560 Rev: G Amendment/+2

Issue Date: January 1998

Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the Am28F256 is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occurs first. To simplify the fol-

lowing discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.

AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F256 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.

BLOCK DIAGRAM
			DQ0–DQ7
VCC
VSS		Erase	Input/Output
VPP
		Voltage
			Buffers
		Switch
	State		To Array
WE#
	Control

Command

Program

Register

Voltage

Chip Enable

Switch

Output Enable

CE#

Logic

Data

OE#

Latch

Low VCC

Y-Gating

Detector

Y-Decoder

Program/Erase

Pulse Timer

Address

262,144

A0–A14

Latch

X-Decoder

Bit

Cell Matrix

11560F-1

PRODUCT SELECTOR GUIDE

Family Part Number

Am28F256

Speed Options (VCC = 5.0 V ± 10%)

-70

-90

-120

-150

-200

Max Access Time (ns)

70

90

120

150

200

CE# (E#) Access (ns)

70

90

120

150

200

OE# (G#) Access (ns)

35

35

50

55

55

2

Am28F256

CONNECTION DIAGRAMS
		PDIP					PLCC
VPP	1	32	VCC							(W#)
NC	2	31	WE# (W#)		A12	NC	NC	V	V	WE#	NC
NC	3	30	NC
								PP	CC
A12	4	29	A14		4	3	2	1	32 31 30
A7	5	28	A13	A7	5						29	A14
A6	6	27	A8	A6	6						28	A13
A5	7	26	A9	A5	7						27	A8
A4	8	25	A11	A4	8						26	A9
A3	9	24	OE# (G#)	A3	9						25	A11
A2	10	23	A10	A2	10						24	OE# (G#)
				A1	11						23	A10
A1	11	22	CE# (E#)
				A0	12						22	CE# (E#)
A0	12	21	DQ7
				DQ0	13						21	DQ7
DQ0			DQ6
	13	20			14 15		16 17 18 19 20
DQ1	14	19	DQ5		DQ1	DQ2	SS	DQ3	DQ4	DQ5	DQ6
DQ2			DQ4
	15	18					V
VSS	16	17	DQ3
			11560F-2									11560F-3

Note: Pin 1 is marked for orientation.

Am28F256

3

CONNECTION DIAGRAMS (continued)

A11		1	32		OE#
A9		2	31		A10
A8		3	30		CE#
A13		4	29		D7
A14		5	28		D6
NC		6	27		D5
WE#		7	26		D4
VCC		8	25		D3
VPP		9	24		VSS
NC		10	23		D2
NC		11	22		D1
A12		12	21		D0
A7		13	20		A0
A6		14	19		A1
A5		15	18		A2
A4		16	17		A3
		32-Pin TSOP—Standard Pinout
OE#
		1	32		A11
A10		2	31		A9
CE#		3	30		A8
D7		4	29		A13
D6		5	28		A14
D5		6	27		NC
D4		7	26		WE#
D3		8	25		VCC
VSS
		9	24		VPP
D2		10	23		NC
D1		11	22		NC
D0		12	21		A12
A0		13	20		A7
A1		14	19		A6
A2		15	18		A5
A3		16	17		A4
		32-Pin TSOP—Reverse Pinout			11560G-4

LOGIC SYMBOL

15

A0–A14

8

DQ0–DQ7

CE# (E#)

OE# (G#)

WE# (W#)

11560F-5

4

Am28F256

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of:

AM28F256

-70

J

C

B

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am28F256

256 Kilobit (32 K x 8-Bit) CMOS Flash Memory

	Valid Combinations
AM28F256-70
		PC, PI, PE,
AM28F256-90
		JC, JI, JE,
AM28F256-120
		EC, EI, EE,
AM28F256-150		FC, FI, FE
AM28F256-200

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am28F256

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PIN DESCRIPTION

A0–A14

Address Inputs for memory locations. Internal latches hold addresses during write cycles.

CE# (E#)

Chip Enable active low input activates the chip’s control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles.

NC

No Connect-corresponding pin is not connected internally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. Output Enable is high during command sequencing and program/erase operations.

VCC

Power supply for device operation. (5.0 V ± 5% or 10%)

VPP

Program voltage input. VPP must be at high voltage in order to write to the command register. The command register controls all functions required to alter the memory array contents. Memory contents cannot be altered when VPP ≤ VCC +2 V.

VSS

Ground

WE# (W#)

Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device.

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Am28F256

BASIC PRINCIPLES

The device uses 100% TTL-level control inputs to manage the command register. Erase and reprogramming operations use a fixed 12.0 V ± 5% high voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high voltage is applied to the VPP pin. The erase and reprogramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The traditional read, standby, output disable, and Auto select modes are available via the register.

The device’s command register is written using standard microprocessor write timings. The register controls an internal state machine that manages all device operations. For system design simplification, the device is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.

Overview of Erase/Program Operations

Flasherase™ Sequence

A multiple step command sequence is required to erase the Flash device (a two-cycle Erase command and repeated one cycle verify commands).

Note: The Flash memory array must be completely programmed to 0’s prior to erasure. Refer to the Flashrite™ Programming Algorithm.

1.Erase Setup: Write the Setup Erase command to the command register.

2.Erase: Write the Erase command (same as Setup Erase command) to the command register again. The second command initiates the erase operation. The system software routines must now time-out the erase pulse width (10 ms) prior to issuing the Erase-verify command. An integrated stop timer prevents any possibility of overerasure.

3.Erase-Verify: Write the Erase-verify command to the command register. This command terminates the erase operation. After the erase operation, each byte of the array must be verified. Address in-

formation must be supplied with the Erase-verify command. This command verifies the margin and outputs the addressed byte in order to compare the a r ray da t a w it h F F h d a t a ( B yt e e r a se d ) . After successful data verification the Erase-verify command is written again with new address information. Each byte of the array is sequentially verified in this manner.

If data of the addressed location is not verified, the Erase sequence is repeated until the entire array is successfully verified or the sequence is repeated 1000 times.

Flashrite Programming Sequence

A three step command sequence (a two-cycle Program command and one cycle Verify command) is required to program a byte of the Flash array. Refer to the Flashrite Algorithm.

1.Program Setup: Write the Setup Program command to the command register.

2.Program: Write the Program command to the command register with the appropriate Address and Data. The system software routines must now timeout the program pulse width (10 µs) prior to issuing the Program-verify command. An integrated stop timer prevents any possibility of overprogramming.

3.Program-Verify: Write the Program-verify command to the command register. This command terminates the programming operation. In addition, this command verifies the margin and outputs the byte just programmed in order to compare the array data with the original data programmed. After successful data verification, the programming sequence is initiated again for the next byte address to be programmed.

If data is not verified successfully, the Program sequence is repeated until a successful comparison is verified or the sequence is repeated 25 times.

Data Protection

The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. The device powers up in its read only state. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting fromVCC powerup and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for

Am28F256

7

VCC < VLKO (see DC Characteristics section for voltages). When VCC < VLKO, the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. The device ignores all writes until VCC > VLKO. The user must ensure that the control pins are in the correct logic state when VCC > VLKO to prevent uninitentional writes.

Write Pulse “Glitch” Protection

Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = VIL and OE# = VIH will not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

FUNCTIONAL DESCRIPTION

Description Of User Modes

Table 1. Am28F256 Device Bus Operations (Notes 7 and 8)

			CE#	OE#	WE#	VPP
		Operation	(E#)	(G#)	(W#)	(Note 1)	A0	A9	I/O
		Read	VIL	VIL	X	VPPL	A0	A9	DOUT
		Standby	VIH	X	X	VPPL	X	X	HIGH Z
	Read-Only	Output Disable	VIL	VIH	VIH	VPPL	X	X	HIGH Z
		Auto-select Manufacturer	VIL	VIL	VIH	VPPL	VIL	VID	CODE
		Code (Note 2)						(Note 3)	(01h)
		Auto-select Device	VIL	VIL	VIH	VPPL	VIH	VID	CODE
		Code (Note 2)						(Note 3)	(A1h)
		Read	VIL	VIL	VIH	VPPH	A0	A9	DOUT
									(Note 4)
	Read/Write	Standby (Note 5)	VIH	X	X	VPPH	X	X	HIGH Z
		Output Disable	VIL	VIH	VIH	VPPH	X	X	HIGH Z
		Write	VIL	VIH	VIL	VPPH	A0	A9	D
									IN
									(Note 6)

Legend:

X = Don’t care, where Don’t Care is either VIL or VIH levels. VPPL = VPP < VCC + 2 V. See DC Characteristics for voltage levels of VPPH. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

Notes:

1.VPPL may be grounded, connected with a resistor to ground, or < VCC + 2.0 V. VPPH is the programming voltage specified for the device. Refer to the DC characteristics. When VPP = VPPL, memory contents can be read but not written or erased.

2.Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3.11.5 < VID < 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.

4.Read operation with VPP = VPPH may access array data or the Auto select codes.

5.With VPP at high voltage, the standby current is ICC + IPP (standby).

6.Refer to Table 3 for valid DIN during a write operation.

7.All inputs are Don’t Care unless otherwise stated, where Don’t Care is either VIL or VIH levels. In the Auto select mode all addresses except A9 and A0 must be held at VIL.

8.If VCC ≤ 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP rise time and fall time specification of 500 ns minimum.

8

Am28F256

READ ONLY MODE

When VPP is less than VCC + 2 V, the command register is inactive. The device can either read array or autoselect data, or be standby mode.

Read

The device functions as a read only memory when VPP < VCC + 2 V. The device has two control functions. Both must be satisfied in order to output data. CE# controls power to the device. This pin should be used for specific device selection. OE# controls the device outputs and should be used to gate data to the output pins if a device is selected.

Address access time tACC is equal to the delay from stable addresses to valid output data. The chip enable access time tCE is the delay from stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable at least tACC–tOE).

Output Disable

Output from the device is disabled when OE# is at a logic high level. When disabled, output pins are in a high impedance state.

Auto Select

Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board.

The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. This mode is intended for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

Standby Mode

The device has two standby modes. The CMOS standby mode (CE# input held at VCC ± 0.5 V), consumes less than 100 µA of current. TTL standby mode (CE# is held at VIH) reduces the current requirements to less than 1mA. When in the standby mode the outputs are in a high impedance state, independent of the OE# input.

If the device is deselected during erasure, programming, or program/erase verification, the device will draw active current until the operation is terminated.

Programming In A PROM Programmer

To activate this mode, the programming equipment must force VID (11.5 V to 13.0 V) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All other address lines must be held at VIL, and VPP must be less than or equal to VCC + 2.0 V while using this Auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the device these two bytes are given in Table 2 below. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit.

Table 2. Am28F256 Auto Select Code

		Code
Type	A0	(HEX)
Manufacturer Code	VIL	01
Device Code	VIH	A1

Am28F256

9

ERASE, PROGRAM, AND READ MODE

When VPP is equal to 12.0 V ± 5%, the command register is active. All functions are available. That is, the device can program, erase, read array or autoselect data, or be standby mode.

Write Operations

High voltage must be applied to the VPP pin in order to activate the command register. Data written to the register serves as input to the internal state machine. The output of the state machine determines the operational function of the device.

The command register does not occupy an addressable memory location. The register is a latch that stores the command, along with the address and data information needed to execute the command. The register is written by bringing WE# and CE# to VIL, while OE# is at VIH. Addresses are latched on the falling edge of WE#, while data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used.

The device requires the OE# pin to be VIH for write operations. This condition eliminates the possibility for bus contention during programming operations. In order to write, OE# must be VIH, and CE# and WE# must be VIL. If any pin is not in the correct state a write command will not be executed.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00h (Read Mode) in the absence of high voltage applied to the VPP pin. The device operates as a read only memory. High voltage on the VPP pin enables the command register. Device operations are selected by writing specific data codes into the command register. Table 3 defines these register commands.

Read Command

Memory contents can be accessed via the read command when VPP is high. To read from the device, write 00h into the command register. Standard microprocessor read cycles access data from the memory. The device will remain in the read mode until the command register contents are altered.

The command register defaults to 00h (read mode) upon VPP power-up. The 00h (Read Mode) register default helps ensure that inadvertent alteration of the memory contents does not occur during the VPP power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

Table 3. Am28F256 Command Definitions

	First Bus Cycle			Second Bus Cycle
	Operation	Address	Data	Operation	Address	Data
Command (Note 4)	(Note 1)	(Note 2)	(Note 3)	(Note 1)	(Note 2)	(Note 3)
Read Memory	Write	X	00h/FFh	Read	RA	RD
Read Auto select	Write	X	80h or 90h	Read	00h/01h	01h/A1h
Erase Set-up/Erase Write	Write	X	20h	Write	X	20h
Erase-Verify	Write	EA	A0h	Read	X	EVD
Program Setup/Program	Write	X	40h	Write	PA	PD
Program-Verify	Write	X	C0h	Read	X	PVD
Reset	Write	X	FFh	Write	X	FFh

Notes:

1.Bus operations are defined in Table 1.

2.RA = Address of the memory location to be read.

EA = Address of the memory location to be read during erase-verify. PA = Address of the memory location to be programmed.

X = Don’t care.

Addresses are latched on the falling edge of the WE# pulse.

3.RD = Data read from location RA during read operation. EVD = Data read from location EA during erase-verify.

PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.

PVD = Data read from location PA during program-verify. PA is latched on the Program command.

4.Refer to the appropriate section for algorithms and timing diagrams.

10

Am28F256

FLASHERASE ERASE SEQUENCE

Erase Setup

Erase Setup is the first of a two-cycle erase command. It is a command-only operation that stages the device for bulk chip erase. The array contents are not altered with this command. 20h is written to the command register in order to perform the Erase Setup operation.

Erase

The second two-cycle erase command initiates the bulk erase operation. You must write the Erase command (20h) again to the register. The erase operation begins with the rising edge of the WE# pulse. The erase operation must be terminated by writing a new command (Erase-verify) to the register.

This two step sequence of the Setup and Erase commands helps to ensure that memory contents are not accidentally erased. Also, chip erasure can only occur when high voltage is applied to the VPP pin and all control pins are in their proper state. In absence of this high voltage, memory contents cannot be altered. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.

Note: The Flash memory device must be fully programmed to 00h data prior to erasure. This equalizes the charge on all memory cells ensuring reliable erasure.

Erase-Verify Command

The erase operation erases all bytes of the array in parallel. After the erase operation, all bytes must be sequentially verified. The Erase-verify operation is initi-

ated by writing A0h to the register. The byte address to be verified must be supplied with the command. Addresses are latched on the falling edge of the WE# pulse or CE# pulse, whichever occurs later. The rising edge of the WE# pulse terminates the erase operation.

Margin Verify

During the Erase-verify operation, the device applies an inter nally generated margin voltage to the addressed byte. Reading FFh from the addressed byte indicates that all bits in the byte are properly erased.

Verify Next Address

You must write the Erase-verify command with the appropriate address to the register prior to verification of each address. Each new address is latched on the falling edge of WE# or CE# pulse, whichever occurs later. The process continues for each byte in the memory array until a byte does not return FFh data or all the bytes in the array are accessed and verified.

If an address is not verified to FFh data, the entire chip is erased again (refer to Erase Setup/Erase). Erase verification then resumes at the address that failed to verify. Erase is complete when all bytes in the array have been verified. The device is now ready to be programmed. At this point, the verification operation is terminated by writing a valid command (e.g. Program Setup) to the command register. Figure 1 and Table 4, the Flasherase electrical erase algorithm, illustrate how commands and bus operations are combined to perform electrical erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.

Am28F256

11