AMD Advanced Micro Devices AM29F080B, AM29F080B-120FCB, AM29F080B-120FC, AM29F080B-120EIB, AM29F080B-120EI Datasheet

PRELIMINARY

Am29F080B

8 Megabit (1 M x 8-Bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■5.0 V ± 10%, single power supply operation

—Minimizes system level power requirements

■Manufactured on 0.35 µm process technology

—Compatible with 0.5 µm Am29F080 device

■High performance

—Access times as fast as 70 ns

■Low power consumption

—25 mA typical active read current

—30 mA typical program/erase current

—1 µA typical standby current (standard access time to active mode)

■Flexible sector architecture

—16 uniform sectors of 64 Kbytes each

—Any combination of sectors can be erased.

—Supports full chip erase

—Group sector protection:

A hardware method of locking sector groups to prevent any program or erase operations within that sector group

Temporary Sector Group Unprotect allows code changes in previously locked sectors

■ Embedded Algorithms

■Minimum 1,000,000 program/erase cycles per sector guaranteed

■Package options

—40-pin TSOP

—44-pin SO

■Compatible with JEDEC standards

—Pinout and software compatible with

single-power-supply Flash standard

—Superior inadvertent write protection

■Data# Polling and toggle bits

—Provides a software method of detecting program or erase cycle completion

■Ready/Busy# output (RY/BY#)

—Provides a hardware method for detecting program or erase cycle completion

■Erase Suspend/Erase Resume

—Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation

■Hardware reset pin (RESET#)

—Resets internal state machine to the read mode

—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors

—Embedded Program algorithm automatically writes and verifies bytes at specified addresses

Publication# 21503 Rev: C Amendment/+1

Issue Date: April 1998

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29F080B is an 8 Mbit, 5.0 volt-only Flash memory organized as 1,048,576 bytes. The 8 bits of data appear on DQ0–DQ7. The Am29F080B is offered in 40-pin TSOP and 44-pin SO packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers.

This device is manufactured using AMD’s 0.35 µm process technology, and offers all the features and benefits of the Am29F080, which was manufactured using 0.5 µm process technology.

The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The system can place the device into the standby mode. Power consumption is greatly reduced in this mode.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all b i t s w i t h i n a s e c t o r s i m u l t a n e o u s l y v i a F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s programmed using hot electron injection.

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P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number				Am29F080B
Speed Option	VCC = 5.0 V ± 5%	-75
	VCC = 5.0 V ± 10%		-90		-120	-150
Max Access Time, ns (tACC)		70	90		120	150
Max CE# Access, ns (tCE)		70	90		120	150
Max OE# Access, ns (tOE)		40	40		50	75

Note: See the “AC Characteristics” section for more information.

BLOCK DIAGRAM

DQ0–DQ7

Sector Switches

VCC

VSS			Erase Voltage			Input/Output
RY/BY#
			Generator			Buffers
RESET#
WE#	State
	Control
	Command
	Register	PGM Voltage
		Generator
			Chip Enable		STB	Data
						Latch
CE#			Output Enable
OE#				Logic
			STB	Y-Decoder		Y-Gating
	VCC Detector	Timer	Latch
			Address	X-Decoder		Cell Matrix
A0–A19
						21503C-1

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P R E L I M I N A R Y

CONNECTION DIAGRAMS

A19 1

A18 2

A17 3

A16 4

A15 5

A14 6

A13 7

A12 8 CE# 9 VCC 10 NC 11

RESET# 12 A11 13 A10 14 A9 15 A8 16 A7 17 A6 18 A5 19 A4 20

NC 1 NC 2 WE# 3 OE# 4 RY/BY# 5 DQ7 6 DQ6 7 DQ5 8 DQ4 9 VCC 10 VSS 11 VSS 12 DQ3 13 DQ2 14 DQ1 15 DQ0 16 A0 17 A1 18 A2 19 A3 20

40 NC

39 NC

38 WE#

37 OE#

36 RY/BY#

35 DQ7

34 DQ6

33 DQ5

32 DQ4

40-Pin Standard TSOP 31 VCC

30 VSS

29 VSS

28 DQ3

27 DQ2

26 DQ1

25 DQ0

24 A0

23 A1

22 A2

21 A3

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40 A19

39 A18

38 A17

37 A16

36 A15

35 A14

34 A13

33 A12

32 CE#

31 VCC

30 NC

40-Pin Reverse TSOP 29 RESET# 28 A11

27 A10

26 A9

25 A8

24 A7

23 A6

22 A5

21 A4

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NC	1				44	VCC
RESET#	2				43	CE#
A11	3				42	A12
A10	4				41	A13
A9	5				40	A14
A8	6				39	A15
A7	7				38	A16
A6	8				37	A17
A5	9				36	A18
A4	10				35	A19
NC 11			SO		34	NC
NC 12					33	NC
A3	13				32	NC
A2	14				31	NC
A1	15				30	WE#
A0	16				29	OE#
DQ0 17					28	RY/BY#
DQ1 18					27	DQ7
DQ2 19					26	DQ6
DQ3 20					25	DQ5
VSS 21					24	DQ4
VSS 22					23	VCC

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P R E L I M I N A R Y

PIN CONFIGURATION

A0–A19	=	20 Addresses
DQ0–DQ7	=	8 Data Inputs/Outputs
CE#	=	Chip Enable
WE#	=	Write Enable
OE#	=	Output Enable
RESET#	= Hardware Reset Pin, Active Low
RY/BY#	=	Ready/Busy Output
VCC	= +5.0 V single power supply
		(see Product Selector Guide for
		device speed ratings and voltage
		supply tolerances)
VSS	=	Device Ground
NC	= Pin Not Connected Internally

LOGIC SYMBOL

	20
			A0–A19		8
				DQ0–DQ7
			CE#
			OE#
			WE#
			RESET#	RY/BY#

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ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

Am29F080B

-75

E

I

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 040)

F	=	40-Pin Thin Small Outline Package
		(TSOP) Reverse Pinout (TSR040)
S	=	44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29F080B

8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory 5.0 V Read, Program, and Erase

Valid Combinations

Am29F080B-75

EC, EI, FC, FI, SC, SI

Am29F080B-90

EC, EI, EE,

Am29F080B-120 FC, FI, FE,

SC, SI, SE

Am29F080B-150

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

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P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Am29F080B Device Bus Operations

Operation	CE#	OE#	WE#	RESET#	A0–A19	DQ0 –DQ7
Read	L	L	X	H	AIN	DOUT
Write	L	H	L	H	AIN	DIN
TTL Standby	H	X	X	H	X	HIGH Z
CMOS Standby	VCC ± 0.3 V	X	X	VCC ± 0.3 V	X	HIGH Z
Output Disable	L	H	H	H	X	HIGH Z
Hardware Reset	X	X	X	VIL	X	HIGH Z
Temporary Sector Group Unprotect (See Note)	X	X	X	VID	AIN	X
Legend:

L = Logic Low = VIL, H = Logic High = VIH, DOUT = Data Out, DIN = Data In, AIN = Address In, X = Don’t Care. See DC Characteristics for voltage levels.

Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the Command Definitions section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

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P R E L I M I N A R Y

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Characteristics section in the appropriate data sheet for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

In the DC Characteristics tables, ICC3 represents the standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the system

drives the RESET# pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VIL, the device enters the TTL standby mode; if RESET# is held at VSS ± 0.5 V, the device enters the CMOS standby mode.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RE-

SET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# parameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

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P R E L I M I N A R Y

Table 2. Am29F080B Sector Address Table

Sector	A19	A18	A17	A16	Address Range
SA0	0	0	0	0	000000h–00FFFFh
SA1	0	0	0	1	010000h–01FFFFh
SA2	0	0	1	0	020000h–02FFFFh
SA3	0	0	1	1	030000h–03FFFFh
SA4	0	1	0	0	040000h–04FFFFh
SA5	0	1	0	1	050000h–05FFFFh
SA6	0	1	1	0	060000h–06FFFFh
SA7	0	1	1	1	070000h–07FFFFh
SA8	1	0	0	0	080000h–08FFFFh
SA9	1	0	0	1	090000h–09FFFFh
SA10	1	0	1	0	0A0000h–0AFFFFh
SA11	1	0	1	1	0B0000h–0BFFFFh
SA12	1	1	0	0	0C0000h–0CFFFFh
SA13	1	1	0	1	0D0000h–0DFFFFh
SA14	1	1	1	0	0E0000h–0EFFFFh
SA15	1	1	1	1	0F0000h–0FFFFFh

Note: All sectors are 64 Kbytes in size.

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.

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P R E L I M I N A R Y

Table 3. Am29F080B Autoselect Codes (High Voltage Method)

A19

A11

A8

A5

DQ7

to

to

to

to

to

Description

CE#

OE#

WE#

A12

A10

A9

A7

A6

A2

A1

A0

DQ0

Manufacturer ID: AMD

L

L

H

X

X

VID

X

L

X

L

L

01h

Device ID: Am29F080B

L

L

H

X

X

VID

X

L

X

L

H

D5h

Sector Group

01h (protected)

L

L

H

SGA

X

VID

X

L

X

H

L

00h

Protection Verification

(unprotected)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SGA = Sector Group Address, X = Don’t care.

Note: The system may also autoselect information in-system via the command register. See Table 5.

Sector Group Protection/Unprotection

The hardware group sector protection feature disables both program and erase operations in any sector group. Each sector group consists of two adjacent sectors. Table 4 shows how the sectors are grouped, and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups.

Sector group protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, listed in publication number 19945. Contact an AMD representative to obtain a copy of the appropriate document.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector group is protected or unprotected. See “Autoselect Mode” for details.

Table 4. Sector Group Addresses

Sector
Group	A19	A18	A17	Sectors
SGA0	0	0	0	SA0–SA1
SGA1	0	0	1	SA2–SA3
SGA2	0	1	0	SA4–SA5
SGA3	0	1	1	SA6–SA7
SGA4	1	0	0	SA8–SA9
SGA5	1	0	1	SA10–SA11
SGA6	1	1	0	SA12–SA13
SGA7	1	1	1	SA14–SA15

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previously protected sector groups to change data in-sys- tem. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the p r ev i o u s l y p r o t e c t e d s e c t o r g r o u p s a r e protected again. Figure 1 shows the algorithm, and the Temporary Sector Group Unprotect diagram shows the timing waveforms, for this feature.

START

RESET# = VID

(Note 1)

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector Group

Unprotect

Completed (Note 2)

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Notes:

1.All protected sector groups unprotected.

2.All previously protected sector groups are protected once again.

Figure 1. Temporary Sector Group Unprotect

Operation

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P R E L I M I N A R Y

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the

proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

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COMMAND DEFINITIONS

Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/ Erase Resume Commands” for more information on this mode.

The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.

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