AMD Advanced Micro Devices AM29LV200BT-90FIB, AM29LV200BT-90FI, AM29LV200BT-90FEB, AM29LV200BB-80FC, AM29LV200BB-80EIB Datasheet

ADVANCE INFORMATION

Am29LV200B

2 Megabit (256 K x 8-Bit/128 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

—Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications

—Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors

■Manufactured on 0.35 μm process technology

—Compatible with 0.5 μm Am29LV200 device

■High performance

—Full voltage range: access times as fast as 80 ns

—Regulated voltage range: access times as fast as 70 ns

■Ultra low power consumption (typical values at 5 MHz)

—200 nA Automatic Sleep mode current

—200 nA standby mode current

—7 mA read current

—15 mA program/erase current

■Flexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors (byte mode)

—One 8 Kword, two 4 Kword, one 16 Kword, and three 32 Kword sectors (word mode)

—Supports full chip erase

—Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sector

Sectors can be locked in-system or via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

■ Unlock Bypass Program Command

■Top or bottom boot block configurations available

■Embedded Algorithms

—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors

—Embedded Program algorithm automatically writes and verifies data at specified addresses

■Minimum 1,000,000 write cycle guarantee per sector

■Package option

—48-pin TSOP

—44-pin SO

■Compatibility with JEDEC standards

—Pinout and software compatible with singlepower supply Flash

—Superior inadvertent write protection

■Data# Polling and toggle bits

—Provides a software method of detecting program or erase operation completion

■Ready/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completion

■Erase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation

■Hardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

—Reduces overall programming time when issuing multiple program command sequences

This document contains information on a product under development at Advanced Micro Devices. The information	Publication# 21521 Rev: A Amendment/0
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed	Issue Date: January 1998
product without notice. 1/23/98

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29LV200B is a 2 Mbit, 3.0 volt-only Flash memory organized as 262,144 bytes or 131,072 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7– DQ0. This device is designed to be programmed insystem using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers.

This device is manufactured using AMD’s 0.35 μm process technology, and offers all the features and benefits of the Am29LV200, which was manufactured using 0 . 5 μ m process technology. In addition, the Am29LV200B features unlock bypass programming and in-system sector protection/unprotection.

The standard device offers access times of 70, 80, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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Am29LV200B

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A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Family Part Number			Am29LV200B
Speed Options	Regulated Voltage Range: VCC =3.0–3.6 V	-70R
	Full Voltage Range: VCC = 2.7–3.6 V		-80	-90	-120
Max access time, ns (tACC)		70	80	90	120
Max CE# access time, ns (tCE)		70	80	90	120
Max OE# access time, ns (tOE)		30	30	35	50

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

	RY/BY#					DQ0–DQ15 (A-1)
VCC			Sector Switches
VSS
RESET#			Erase Voltage			Input/Output
			Generator			Buffers
WE#	State
BYTE#	Control
	Command
	Register	PGM Voltage
		Generator
			Chip Enable		STB	Data
						Latch
CE#			Output Enable
OE#				Logic
			STB	Y-Decoder		Y-Gating
	VCC Detector	Timer	Latch
			Address	X-Decoder		Cell Matrix
A0–A16
						21521A-1

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