AMD Advanced Micro Devices AM29F010B-70PIB, AM29F010B-70PI, AM29F010B-70PEB, AM29F010B-70PE, AM29F010B-70PCB Datasheet

FINAL

Am29F010

1 Megabit (128 K x 8-bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

—5.0 V ± 10% for read, erase, and program operations

—Simplifies system-level power requirements

■High performance

—45 ns maximum access time

■Low power consumption

—30 mA max active read current

—50 mA max program/erase current

—<25 μA typical standby current

■Flexible sector architecture

—Eight uniform sectors

—Any combination of sectors can be erased

—Supports full chip erase

■Sector protection

—Hardware-based feature that disables/reenables program and erase operations in any combination of sectors

—Sector protection/unprotection can be implemented using standard PROM programming equipment

■Embedded Algorithms

—Embedded Erase algorithm automatically pre-programs and erases the chip or any combination of designated sector

—Embedded Program algorithm automatically programs and verifies data at specified address

■Minimum 100,000 program/erase cycles guaranteed

■Package options

—32-pin PLCC

—32-pin TSOP

—32-pin PDIP

■Compatible with JEDEC standards

—Pinout and software compatible with

single-power-supply flash

—Superior inadvertent write protection

■Data# Polling and Toggle Bits

—Provides a software method of detecting program or erase cycle completion

Publication# 16736 Rev: G Amendment/+2

Issue Date: March 1998

GENERAL DESCRIPTION

The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory organized as 131,072 bytes. The Am29F010 is offered in 32-pin PLCC, TSOP, and PDIP packages. The bytewide data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed or erased in standard EPROM programmers.

The standard device offers access times of 45, 55, 70, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is erased when shipped from the factory.

The hardware data protection measures include a low VCC detector automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory, and is implemented using standard EPROM programmers.

The system can place the device into the standby mode. Power consumption is greatly reduced in this mode.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.

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Am29F010

PRODUCT SELECTOR GUIDE

Family Part Number				Am29F010
Speed Option	VCC = 5.0 V ± 5%	-45	-55 (P)
	VCC = 5.0 V ± 10%		-55 (J, E, F)	-70	-90	-120
Max Access Time (ns)		45	55	70	90	120
CE# Access (ns)		45	55	70	90	120
OE# Access (ns)		25	30	30	35	50

Note: See the AC Characteristics section for full specifications.

BLOCK DIAGRAM
						DQ0–DQ7
VCC			Erase Voltage			Input/Output
VSS
			Generator			Buffers
WE#	State
	Control
	Command
	Register	PGM Voltage
		Generator
			Chip Enable		STB	Data
						Latch
CE#			Output Enable
OE#				Logic
			STB	Y-Decoder		Y-Gating
	VCC Detector	Timer	Latch
			Address	X-Decoder		Cell Matrix
A0–A16

16736G-1

Am29F010

3

CONNECTION DIAGRAMS

NC		1	32	VCC
A16		2	31	WE#
A15		3	30	NC
A12		4	29	A14
A7		5	28	A13
A6		6	27	A8
A5		7	26	A9
A4		8	PDIP 25	A11
A3		9	24	OE#
A2		10	23	A10
A1		11	22	CE#
A0		12	21	DQ7
DQ0				DQ6
		13	20
DQ1		14	19	DQ5
DQ2		15	18	DQ4
VSS
		16	17	DQ3

A12

A15

A16

NC

V

WE#

NC

CC

3

2

1

32 31 30

4

A7

5

29

A14

A6

6

28

A13

A5

7

27

A8

A4

8

26

A9

A3

9

PLCC

25

A11

A2

10

24

OE#

A1

11

23

A10

A0

12

22

CE#

DQ0

13

21

DQ7

14 15 16 17 18 19 20

DQ1

DQ2

SS

DQ3

DQ4

DQ5

DQ6

V

16736G-2

16736G-3

A11			1
A9			2
A8			3
A13			4
A14			5
NC			6
WE#			7
VCC			8
NC			9
A16			10
A15			11
A12			12
A7			13
A6			14
A5			15
A4			16
OE#			1
A10			2
CE#			3
DQ7			4
DQ6			5
DQ5			6
DQ4			7
DQ3			8
VSS			9
DQ2			10
DQ1			11
DQ0			12
A0			13
A1			14
A2			15
A3			16

	32		OE#
	31		A10
	30		CE#
	29		DQ7
	28		DQ6
	27		DQ5
	26		DQ4
Standard TSOP	25		DQ3
	24		VSS
	23		DQ2
	22		DQ1
	21		DQ0
	20		A0
	19		A1
	18		A2
	17		A3
			16736G-4
	32		A11
	31		A9
	30		A8
	29		A13
	28		A14
	27		NC
	26		WE#
Reverse TSOP	25		VCC
	24		NC
	23		A16
	22		A15
	21		A12
	20		A7
	19		A6
	18		A5
	17		A4

16736G-5

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Am29F010

PIN CONFIGURATION

A0–A16	=	17 Addresses
DQ0–DQ7	=	8 Data Inputs/Outputs
CE#	=	Chip Enable
OE#	=	Output Enable
WE#	=	Write Enable
VCC	= +5.0 Volt Single Power Supply
		(See Product Selector Guide for speed
		options and voltage supply tolerances)
VSS	=	Device Ground
NC	= Pin Not Connected Internally

LOGIC SYMBOL

17

A0–A16

8

DQ0–DQ7

CE#

OE#

WE#

16736G-6

Am29F010

5

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29F010

-70

E

C

B

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

(Contact an AMD representative for more information.)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

P	=	32-Pin Plastic DIP (PD 032)
J	=	32-Pin Rectangular Plastic Leaded
		Chip Carrier (PL 032)
E	=	32-Pin Thin Small Outline Package
		(TSOP) Standard Pinout (TS 032)
F	=	32-Pin Thin Small Outline Package
		(TSOP) Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and

Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29F010

1 Megabit (128 K x 8-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program, and Erase

Valid Combinations

		PC, PI, PE,
	AM29F010-45	JC, JI, JE,
		EC, EI, EE,
		FC, FI, FE
	AM29F010-55	PC5, PI5, PE5
	VCC = 5.0 V ± 5%
	AM29F010-55	JC, JI, JE, EC, EI, EE, FC, FI, FE
	VCC = 5.0 V ± 10%
	AM29F010-70	PC, PI, PE,
	AM29F010-90	JC, JI, JE,
		EC, EI, EE,
	AM29F010-120
		FC, FI, FE

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

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Am29F010

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the

register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Am29F010 Device Bus Operations

				Addresses
Operation	CE#	OE#	WE#	(Note 1)	DQ0–DQ7
Read	L	L	H	AIN	DOUT
Write	L	H	L	AIN	DIN
Standby	VCC ± 0.5 V	X	X	X	High-Z
Output Disable	L	H	H	X	High-Z
Hardware Reset	X	X	X	X	High-Z
Temporary Sector Unprotect	X	X	X	AIN	DIN

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out

Notes:

1.Addresses are A16:A0.

2.The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Am29F010

7

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Characteristics section in the appropriate data sheet for timing diagrams.

The device enters the CMOS standby mode when the CE# pin is held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# is held at VIH. The device requires the standard access time (tCE) before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

ICC3 in the DC Characteristics tables represents the standby current specification.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Table 2. Am29F010 Sector Addresses Table

Sector	A16	A15	A14	Address Range
SA0	0	0	0	00000h-03FFFh
SA1	0	0	1	04000h-07FFFh
SA2	0	1	0	08000h-0BFFFh
SA3	0	1	1	0C000h-0FFFFh
SA4	1	0	0	10000h-13FFFh
SA5	1	0	1	14000h-17FFFh
SA6	1	1	0	18000h-1BFFFh
SA7	1	1	1	1C000h-1FFFFh

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.

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Am29F010

Table 3. Am29F010 Autoselect Codes (High Voltage Method)

A16

A13

A8

A5

DQ7

to

to

to

to

to

Description

CE#

OE#

WE#

A14

A10

A9

A7

A6

A2

A1

A0

DQ0

Manufacturer ID: AMD

L

L

H

X

X

VID

X

L

X

L

L

01h

Device ID: Am29F010

L

L

H

X

X

VID

X

L

X

L

H

20h

01h

Sector Protection Verification

L

L

H

SA

X

VID

X

L

X

H

L

(protected)

00h

(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 20495. Contact an AMD representative to obtain a copy of the appropriate document.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or pro-

gramming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

= VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE#

is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

Am29F010

9

COMMAND DEFINITIONS

Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data.

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence.

A read cycle at address XX00h or retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7or DQ6. See “Write Operation Status” for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

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Am29F010