PRELIMINARY
Am29F017B
16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■Optimized for memory card applications
—Backwards-compatible with the Am29F016C
■5.0 V ± 10%, single power supply operation
—Minimizes system level power requirements
■Manufactured on 0.35 µm process technology
■High performance
—Access times as fast as 70 ns
■Low power consumption
—25 mA typical active read current
—30 mA typical program/erase current
—1 μA typical standby current (standard access time to active mode)
■Flexible sector architecture
—32 uniform sectors of 64 Kbytes each
—Any combination of sectors can be erased.
—Supports full chip erase
—Group sector protection:
A hardware method of locking sector groups to prevent any program or erase operations within that sector group
Temporary Sector Group Unprotect allows code changes in previously locked sectors
■Embedded Algorithms
—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors
—Embedded Program algorithm automatically writes and verifies bytes at specified addresses
■Minimum 1,000,000 program/erase cycles per sector guaranteed
■Package options
—48-pin TSOP
■Compatible with JEDEC standards
—Pinout and software compatible with
single-power-supply Flash standard
—Superior inadvertent write protection
■Data# Polling and toggle bits
—Provides a software method of detecting program or erase cycle completion
■Ready/Busy# output (RY/BY#)
—Provides a hardware method for detecting program or erase cycle completion
■Erase Suspend/Erase Resume
—Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
■Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
Publication# 21195 Rev: B Amendment/+2
Issue Date: April 1998
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29F017B is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes. The 8 bits of data appear on DQ0–DQ7. The Am29F017B is offered in a 48-pin TSOP package. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.35 µm process technology, and offers all the features and benefits of the Am29F016C, which was manufactured using 0.5 µm process technology.
The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The system can place the device into the standby mode. Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all b i t s w i t h i n a s e c t o r s i m u l t a n e o u s l y v i a F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s programmed using hot electron injection.
2 |
Am29F017B |
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number |
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Am29F017B |
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Speed Options (VCC = 5.0 V ± 10% |
-70 |
-90 |
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-120 |
-150 |
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Max Access Time (ns) |
70 |
90 |
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120 |
150 |
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CE# Access (ns) |
70 |
90 |
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120 |
150 |
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OE# Access (ns) |
40 |
40 |
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50 |
75 |
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Note: See the AC Characteristics section for more information.
BLOCK DIAGRAM
DQ0–DQ7
Sector Switches
VCC
VSS |
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Erase Voltage |
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Input/Output |
RY/BY# |
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Generator |
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Buffers |
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RESET# |
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WE# |
State |
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Control |
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Command |
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Register |
PGM Voltage |
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Generator |
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Chip Enable |
STB |
Data |
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Latch |
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CE# |
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Output Enable |
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OE# |
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Logic |
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STB |
Y-Decoder |
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Y-Gating |
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VCC Detector |
Timer |
Latch |
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Address |
X-Decoder |
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Cell Matrix |
A0–A20 |
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21195B-1 |
Am29F017B |
3 |
P R E L I M I N A R Y
CONNECTION DIAGRAMS
NC |
1 |
NC |
2 |
A19 |
3 |
A18 |
4 |
A17 |
5 |
A16 |
6 |
A15 |
7 |
A14 |
8 |
A13 |
9 |
A12 |
10 |
CE# 11 |
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VCC |
12 |
NC 13 |
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RESET# 14 |
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A11 |
15 |
A10 |
16 |
A9 |
17 |
A8 |
18 |
A7 |
19 |
A6 |
20 |
A5 |
21 |
A4 |
22 |
NC |
23 |
NC |
24 |
NC 1
NC 2
A20 3
NC 4
WE# 5
OE# 6
RY/BY# 7
DQ7 8
DQ6 9
DQ5 10
DQ4 11
VCC 12
VSS 13
VSS 14
DQ3 15
DQ2 16
DQ1 17
DQ0 18
A0 19
A1 20
A2 21
A3 22
NC 23
NC 24
48-Pin Standard TSOP
48-Pin Reverse TSOP
4 |
Am29F017B |
48 |
NC |
47 |
NC |
46 |
A20 |
45 |
NC |
44 |
WE# |
43 |
OE# |
42 |
RY/BY# |
41 |
DQ7 |
40 |
DQ6 |
39 |
DQ5 |
38 |
DQ4 |
37 |
VCC |
36 |
VSS |
35 |
VSS |
34 |
DQ3 |
33 |
DQ2 |
32 |
DQ1 |
31 |
DQ0 |
30 |
A0 |
29 |
A1 |
28 |
A2 |
27 |
A3 |
26 |
NC |
25 |
NC |
21195B-2
48 NC
47 NC
46 A19
45 A18
44 A17
43 A16
42 A15
41 A14
40 A13
39 A12
38 CE#
37 VCC
36 NC
35 RESET#
34 A11
33 A10
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 NC
25 NC
21195B-3
P R E L I M I N A R Y
PIN CONFIGURATION
A0–A20 |
= |
21 Addresses |
DQ0–DQ7 |
= |
8 Data Inputs/Outputs |
CE# |
= |
Chip Enable |
WE# |
= |
Write Enable |
OE# |
= |
Output Enable |
RESET# |
= Hardware Reset Pin, Active Low |
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RY/BY# |
= |
Ready/Busy Output |
VCC |
= +5.0 V single power supply |
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(see Product Selector Guide for |
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device speed ratings and voltage |
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supply tolerances) |
VSS |
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Device Ground |
NC |
= Pin Not Connected Internally |
LOGIC SYMBOL
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21 |
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A0–A20 |
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DQ0–DQ7 |
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CE# |
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OE# |
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WE# |
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RESET# |
RY/BY# |
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21195B-4
Am29F017B |
5 |
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
Am29F017B |
-70 |
E |
I |
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I |
= Industrial (–40°C to +85°C) |
E = Extended (–55°C to +125°C) |
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PACKAGE TYPE |
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E |
= 48-Pin Thin Small Outline Package |
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(TSOP) Standard Pinout (TS 048) |
F |
= 48-Pin Thin Small Outline Package |
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(TSOP) Reverse Pinout (TSR048) |
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F017B
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory 5.0 V Read, Program, and Erase
Valid Combinations
Am29F017B-70
Am29F017B-90
EC, EI, EE, FC, FI, FE
Am29F017B-120
Am29F017B-150
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
6 |
Am29F017B |
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1. Am29F017B Device Bus Operations
Operation |
CE# |
OE# |
WE# |
RESET# |
A0–A20 |
DQ0–DQ7 |
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Read |
L |
L |
H |
H |
AIN |
DOUT |
Write |
L |
H |
L |
H |
AIN |
DIN |
CMOS Standby |
VCC ± 0.5 V |
X |
X |
VCC ± 0.5 V |
X |
High-Z |
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TTL Standby |
H |
X |
X |
H |
X |
High-Z |
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Output Disable |
L |
H |
H |
H |
X |
High-Z |
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Hardware Reset |
X |
X |
X |
L |
X |
High-Z |
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Temporary Sector Unprotect |
X |
X |
X |
VID |
AIN |
DIN |
(See Note) |
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note:
See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.
Am29F017B |
7 |
P R E L I M I N A R Y
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.
The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
In the DC Characteristics tables, ICC3 represents the standby current specification.
drives the RESET# pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VIL, the device enters the TTL standby mode; if RESET# is held at VSS ± 0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
8 |
Am29F017B |
P R E L I M I N A R Y
Table 2. Sector Address Table
Sector |
A20 |
A19 |
A18 |
A17 |
A16 |
Address Range |
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SA0 |
0 |
0 |
0 |
0 |
0 |
000000h-00FFFFh |
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SA1 |
0 |
0 |
0 |
0 |
1 |
010000h-01FFFFh |
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SA2 |
0 |
0 |
0 |
1 |
0 |
020000h-02FFFFh |
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SA3 |
0 |
0 |
0 |
1 |
1 |
030000h-03FFFFh |
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SA4 |
0 |
0 |
1 |
0 |
0 |
040000h-04FFFFh |
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SA5 |
0 |
0 |
1 |
0 |
1 |
050000h-05FFFFh |
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SA6 |
0 |
0 |
1 |
1 |
0 |
060000h-06FFFFh |
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SA7 |
0 |
0 |
1 |
1 |
1 |
070000h-07FFFFh |
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SA8 |
0 |
1 |
0 |
0 |
0 |
080000h-08FFFFh |
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SA9 |
0 |
1 |
0 |
0 |
1 |
090000h-09FFFFh |
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SA10 |
0 |
1 |
0 |
1 |
0 |
0A0000h-0AFFFFh |
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SA11 |
0 |
1 |
0 |
1 |
1 |
0B0000h-0BFFFFh |
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SA12 |
0 |
1 |
1 |
0 |
0 |
0C0000h-0CFFFFh |
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SA13 |
0 |
1 |
1 |
0 |
1 |
0D0000h-0DFFFFh |
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SA14 |
0 |
1 |
1 |
1 |
0 |
0E0000h-0EFFFFh |
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SA15 |
0 |
1 |
1 |
1 |
1 |
0F0000h-0FFFFFh |
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SA16 |
1 |
0 |
0 |
0 |
0 |
100000h-10FFFFh |
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SA17 |
1 |
0 |
0 |
0 |
1 |
110000h-11FFFFh |
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SA18 |
1 |
0 |
0 |
1 |
0 |
120000h-12FFFFh |
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SA19 |
1 |
0 |
0 |
1 |
1 |
130000h-13FFFFh |
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SA20 |
1 |
0 |
1 |
0 |
0 |
140000h-14FFFFh |
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SA21 |
1 |
0 |
1 |
0 |
1 |
150000h-15FFFFh |
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SA22 |
1 |
0 |
1 |
1 |
0 |
160000h-16FFFFh |
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SA23 |
1 |
0 |
1 |
1 |
1 |
170000h-17FFFFh |
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SA24 |
1 |
1 |
0 |
0 |
0 |
180000h-18FFFFh |
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SA25 |
1 |
1 |
0 |
0 |
1 |
190000h-19FFFFh |
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SA26 |
1 |
1 |
0 |
1 |
0 |
1A0000h-1AFFFFh |
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SA27 |
1 |
1 |
0 |
1 |
1 |
1B0000h-1BFFFFh |
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SA28 |
1 |
1 |
1 |
0 |
0 |
1C0000h-1CFFFFh |
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SA29 |
1 |
1 |
1 |
0 |
1 |
1D0000h-1DFFFFh |
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SA30 |
1 |
1 |
1 |
1 |
0 |
1E0000h-1EFFFFh |
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SA31 |
1 |
1 |
1 |
1 |
1 |
1F0000h-1FFFFFh |
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Note: All sectors are 64 Kbytes in size.
Am29F017B |
9 |
P R E L I M I N A R Y
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.
Table 3. Am29F017B Autoselect Codes (High Voltage Method)
Description |
CE# |
OE# |
WE# |
A20-A18 |
A17-A10 |
A9 |
A8-A7 |
A6 |
A5-A2 |
A1 |
A0 |
DQ7-DQ0 |
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Manufacturer ID: |
L |
L |
H |
X |
X |
VID |
X |
VIL |
X |
VIL |
VIL |
01h |
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AMD |
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Device ID: |
L |
L |
H |
X |
X |
VID |
X |
VIL |
X |
VIL |
VIH |
3Dh |
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Am29F017B |
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Sector Group |
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Sector |
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01h (protected) |
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Protection |
L |
L |
H |
Group |
X |
VID |
X |
VIL |
X |
VIH |
VIL |
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00h (unprotected) |
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Verification |
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Address |
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L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Group Protection/Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector. Each sector group consists of four adjacent sectors. Table 4 shows how the sectors are goruped, and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sectors.
Sector group protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 21544. Contact an AMD representative to obtain a copy of the appropriate document.
The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.
It is possible to determine whether a sector group is protected or unprotected. See “Autoselect Mode” for details.
Table 4. Sector Group Addresses
Sector |
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Group |
A20 |
A19 |
A18 |
Sectors |
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SGA0 |
0 |
0 |
0 |
SA0–SA3 |
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SGA1 |
0 |
0 |
1 |
SA4–SA7 |
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SGA2 |
0 |
1 |
0 |
SA8–SA11 |
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SGA3 |
0 |
1 |
1 |
SA12–SA15 |
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SGA4 |
1 |
0 |
0 |
SA16–SA19 |
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SGA5 |
1 |
0 |
1 |
SA20–SA23 |
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SGA6 |
1 |
1 |
0 |
SA24–SA27 |
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SGA7 |
1 |
1 |
1 |
SA28–SA31 |
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Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sectors groups to change data in-sys- tem. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the p r ev i o u s l y p r o t e c t e d s e c t o r g r o u p s a r e protected again. Figure 1 shows the algorithm, and the Temporary Sector/Sector Group Unprotect diagram shows the timing waveforms, for this feature.
10 |
Am29F017B |
P R E L I M I N A R Y
Hardware Data Protection
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector Group
Unprotect
Completed (Note 2)
21195B-5
Notes:
1.All protected sector groups unprotected.
2.All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect
Operation
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Am29F017B |
11 |