AMD Advanced Micro Devices AM29LV400BT-90SIB, AM29LV400BT-90SI, AM29LV400BT-90SEB, AM29LV400BT-90SE, AM29LV400BT-80FIB Datasheet

PRELIMINARY

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

■Simultaneous Read/Write operations

—Host system can program or erase in one bank, then immediately and simultaneously read from the other bank

—Zero latency between read and write operations

—Read-while-erase

—Read-while-program

■Single power supply operation

—2.7 to 3.6 volt read and write operations for battery-powered applications

■Manufactured on 0.35 µm process technology

■High performance

—Access times as fast as 70 ns

■Low current consumption (typical values at 5 MHz)

—7 mA active read current

—21 mA active read-while-program or read-while- erase current

—17 mA active program-while-erase-suspended current

—200 nA in standby mode

—200 nA in automatic sleep mode

—Standard t CE chip enable access time applies to transition from automatic sleep mode to active mode

■Flexible sector architecture

—Two 16 Kword, two 8 Kword, four 4 Kword, and six 32 Kword sectors in word mode

—Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and six 64 Kbyte sectors in byte mode

—Any combination of sectors can be erased

—Supports full chip erase

■Unlock Bypass Program Command

—Reduces overall programming time when issuing multiple program command sequences

■Sector protection

—Hardware method of locking a sector to prevent any program or erase operation within that sector

—Sectors can be locked in-system or via programming equipment

—Temporary Sector Unprotect feature allows code changes in previously locked sectors

■Top or bottom boot block configurations available

■Embedded Algorithms

—Embedded Erase algorithm automatically

pre-programs and erases sectors or entire chip

—Embedded Program algorithm automatically programs and verifies data at specified address

■Minimum 1 million program/erase cycles guaranteed per sector

■Package options

—44-pin SO

—48-pin TSOP

■Compatible with JEDEC standards

—Pinout and software compatible with

single-power-supply flash standard

—Superior inadvertent write protection

■Data# Polling and Toggle Bits

—Provides a software method of detecting program or erase cycle completion

■Ready/Busy# output (RY/BY#)

—Hardware method for detecting program or erase cycle completion

■Erase Suspend/Erase Resume

—Suspends or resumes erasing sectors to allow reading and programming in other sectors

—No need to suspend if sector is in the other bank

■Hardware reset pin (RESET#)

—Hardware method of resetting the device to reading array data

Publication# 21606 Rev: C Amendment/0

Issue Date: April 1998

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29DL400B is an 4 Mbit, 3.0 volt-only flash memory device, organized as 262,144 words or 524,288 bytes. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide (x16) data appears on DQ0–DQ15; the byte-wide (x8) data appears on DQ0–DQ7. This device requires only a single 3.0 volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

The standard device offers access times of 70, 80, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. Standard control pins— chip enable (CE#), write enable (WE#), and output enable (OE#)—control read and write operations, and avoid bus contention issues.

The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. Bank 1 contains boot/parameter sectors, and Bank 2 consists of larger, code sectors of uniform size. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

Am29DL400B Features

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device automatically returns to reading array data.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector within that bank that is not selected for erasure. True background erase can thus be achieved. There is no need to suspend the erase operation if the read data is in the other bank.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device to reading array data, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte or word at a time using hot electron injection.

2	Am29DL400B

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number		Am29DL400B
Speed Options (Full Voltage Range: VCC = 2.7 – 3.6 V)	-70	-80	-90	-120
Max Access Time (ns)	70	80	90	120
CE# Access (ns)	70	80	90	120
OE# Access (ns)	30	30	35	50

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM
VCC					OE#	BYTE#
VSS
					Logic
A0–A17			Upper Bank Address		Latches and Control
			Y-Decoder	Upper Bank
	A0–A17	RY/BY#					DQ0–DQ15
A0–A17				X-Decoder
RESET#	STATE
	CONTROL		Status
WE#		&
CE#	COMMAND
	REGISTER
BYTE#			Control
DQ0–DQ15
	A0–A17			X-Decoder			DQ0–DQ15
				Lower Bank	Latches and	Control Logic
A0–A17			Lower Bank Address
			DecoderY-
					OE#	BYTE#

DQ0–DQ15

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P R E L I M I N A R Y

CONNECTION DIAGRAMS

A15 1

A14 2

A13 3

A12 4

A11 5

A10 6

A9 7

A8 8

NC 9

NC 10

WE# 11

RESET# 12

NC 13

NC 14

RY/BY# 15

NC 16

A17 17

A7 18

A6 19

A5 20

A4 21

A3 22

A2 23

A1 24

A16 1

BYTE# 2

VSS 3

DQ15/A-1 4

DQ7 5

DQ14 6

DQ6 7

DQ13 8

DQ5 9

DQ12 10

DQ4 11

VCC 12

DQ11 13

DQ3 14

DQ10 15

DQ2 16

DQ9 17

DQ1 18

DQ8 19

DQ0 20

OE# 21

VSS 22

CE# 23

A0 24

Standard TSOP

Reverse TSOP

48 A16

47 BYTE#

46 VSS

45 DQ15/A-1

44 DQ7

43 DQ14

42 DQ6

41 DQ13

40 DQ5

39 DQ12

38 DQ4

37 VCC

36 DQ11

35 DQ3

34 DQ10

33 DQ2

32 DQ9

31 DQ1

30 DQ8

29 DQ0

28 OE#

27 VSS

26 CE#

25 A0

48 A15

47 A14

46 A13

45 A12

44 A11

43 A10

42 A9

41 A8

40 NC

39 NC

38 WE#

37 RESET#

36 NC

35 NC

34 RY/BY#

33 NC

32 A17

31 A7

30 A6

29 A5

28 A4

27 A3

26 A2

25 A1

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P R E L I M I N A R Y

CONNECTION DIAGRAMS

RY/BY#	1				44	RESET#
NC	2				43	WE#
A17	3				42	A8
A7	4				41	A9
A6	5				40	A10
A5	6				39	A11
A4	7				38	A12
A3	8				37	A13
A2	9				36	A14
A1	10				35	A15
A0	11		SO		34	A16
CE# 12					33	BYTE#
VSS 13					32	VSS
OE# 14					31	DQ15/A-1
DQ0 15					30	DQ7
DQ8 16					29	DQ14
DQ1 17					28	DQ6
DQ9 18					27	DQ13
DQ2 19					26	DQ5
DQ10 20					25	DQ12
DQ3 21					24	DQ4
DQ11 22					23	VCC

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P R E L I M I N A R Y

PIN DESCRIPTION

A0-A17 = 18 Addresses

DQ0-DQ14 = 15 Data Inputs/Outputs

DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode)

CE#	= Chip Enable
OE#	= Output Enable
WE#	= Write Enable
BYTE#	= Selects 8-bit or 16-bit mode
RESET#	= Hardware Reset Pin, Active Low
RY/BY#	= Ready/Busy Output
VCC	= 3.0 volt-only single power supply
	(see Product Selector Guide for speed
	options and voltage supply tolerances)
VSS	= Device Ground
NC	= Pin Not Connected Internally

LOGIC SYMBOL

	18			A0–A17		16 or 8
					DQ0–DQ15
				CE#	(A-1)
				OE#
				WE#
				RESET#
				BYTE#	RY/BY#

21606C-4

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P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

Am29DL400B T

-70

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I	= Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E	= 40-Pin Thin Small Outline Package (TSOP)
	Standard Pinout (TS 040)
F	= 40-Pin Thin Small Outline Package (TSOP)
	Reverse Pinout (TSR040)
S	= 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

	Valid Combinations
	Am29DL400BT-70	EC, EI, FC, FI,
	Am29DL400BB-70	SC, SI
	Am29DL400BT-80
	Am29DL400BB-80
		EC, EI, EE,
	Am29DL400BT-90
		FC, FI, FE,
	Am29DL400BB-90
		SC, SI, SE
	Am29DL400BT-120
	Am29DL400BB-120

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations to check on newly released combinations.

Am29DL400B

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P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Am29DL400B Device Bus Operations

								DQ8–DQ15
					Addresses	DQ0–	BYTE#	BYTE#
Operation	CE#	OE#	WE#	RESET#	(Note 1)	DQ7	= VIH	= VIL
Read	L	L	H	H	AIN	DOUT	DOUT	DQ8–DQ14 = High-Z,
Write	L	H	L	H	AIN	DIN	DIN	DQ15 = A-1
Standby	VCC ±	X	X	VCC ±	X	High-Z	High-Z	High-Z
	0.3 V			0.3 V
Output Disable	L	H	H	H	X	High-Z	High-Z	High-Z
Reset	X	X	X	L	X	High-Z	High-Z	High-Z
					Sector Address,
Sector Protect (Note 2)	L	H	L	VID	A6 = L, A1 = H,	DIN	X	X
					A0 = L
					Sector Address,
Sector Unprotect (Note 2)	L	H	L	VID	A6 = H, A1 = H,	DIN	X	X
					A0 = L
Temporary Sector Unprotect	X	X	X	VID	AIN	DIN	DIN	High-Z

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1.Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL).

2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0-15 are active and controlled by CE# and OE# .

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing

8	Am29DL400B

P R E L I M I N A R Y

sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Byte/Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector.

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased).

Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-program and read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

ICC3 in the DC Characteristics table represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched

and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep

mode current specification.

Am29DL400B

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P R E L I M I N A R Y

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.

memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RE-

SET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

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P R E L I M I N A R Y

Table 2. Am29DL400BT Top Boot Sector Architecture

				Sector Address
			Bank						Sector Size
			Address
									(Kbytes/	(x8)	(x16)
	Bank	Sector	A17	A16	A15	A14	A13	A12	Kwords)	Address Range	Address Range
		SA0	0	0	0	X	X	X	64/32	00000h–0FFFFh	00000h–07FFFh
		SA1	0	0	1	X	X	X	64/32	10000h–1FFFFh	08000h–0FFFFh
	Bank 2	SA2	0	1	0	X	X	X	64/32	20000h–2FFFFh	10000h–17FFFh
		SA3	0	1	1	X	X	X	64/32	30000h–3FFFFh	18000h–1FFFFh
		SA4	1	0	0	X	X	X	64/32	40000h–4FFFFh	20000h–27FFFh
		SA5	1	0	1	X	X	X	64/32	50000h–5FFFFh	28000h–2FFFFh
		SA6	1	1	0	0	0	X	16/8	60000h–63FFFh	30000h–31FFFh
		SA7	1	1	0	0	1	X	32/16	64000h–6BFFFh	32000h–35FFFh
						1	0	X
		SA8	1	1	0	1	1	0	8/4	6C000h–6DFFFh	36000h–36FFFh
	Bank 1	SA9	1	1	0	1	1	1	8/4	6E000h–6FFFFh	37000h–37FFFh
		SA10	1	1	1	0	0	0	8/4	70000h–71FFFh	38000h–38FFFh
		SA11	1	1	1	0	0	1	8/4	72000h–73FFFh	39000h–39FFFh
		SA12	1	1	1	0	1	X	32/16	74000h–7BFFFh	3A000h–3DFFFh
						1	0	X
		SA13	1	1	1	1	1	X	16/8	7C000h–7FFFFh	3E000h–3FFFFh

Note: The address range is A17:A-1 if in byte mode (BYTE# = VIL). The address range is A17:A0 if in word mode (BYTE# = VIH).

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P R E L I M I N A R Y

Table 3. Am29DL400BB Bottom Boot Sector Architecture

				Sector Address
			Bank
			Address						Sector Size	(x8)	(x16)
	Bank	Sector	A17	A16	A15	A14	A13	A12	(Kbytes/Kwords)	Address Range	Address Range
		SA13	1	1	1	X	X	X	64/32	70000h–7FFFFh	38000h–3FFFFh
		SA12	1	1	0	X	X	X	64/32	60000h–6FFFFh	30000h–37FFFh
	Bank 2	SA11	1	0	1	X	X	X	64/32	50000h–5FFFFh	28000h–2FFFFh
		SA10	1	0	0	X	X	X	64/32	40000h–4FFFFh	20000h–27FFFh
		SA9	0	1	1	X	X	X	64/32	30000h–3FFFFh	18000h–1FFFFh
		SA8	0	1	0	X	X	X	64/32	20000h–2FFFFh	10000h–17FFFh
		SA7	0	0	1	1	1	X	16/8	1C000h–1FFFFh	0E000h–0FFFFh
		SA6	0	0	1	1	0	X	32/16	14000h–1BFFFh	0A000h–0DFFFh
						0	1	X
		SA5	0	0	1	0	0	1	8/4	12000h–13FFFh	09000h–09FFFh
	Bank 1	SA4	0	0	1	0	0	0	8/4	10000h–11FFFh	08000h–08FFFh
		SA3	0	0	0	1	1	1	8/4	0E000h–0FFFFh	07000h–07FFFh
		SA2	0	0	0	1	1	0	8/4	0C000h–0DFFFh	06000h–06FFFh
		SA1	0	0	0	1	0	X	32/16	04000h–0BFFFh	02000h–05FFFh
						0	1	X
		SA0	0	0	0	0	0	X	16/8	00000h–03FFFh	00000h–01FFFh

Note: The address range is A17:A-1 if in byte mode (BYTE# = VIL). The address range is A17:A0 if in word mode (BYTE# = VIH).

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in

Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require VID. Refer to the Autoselect Command Sequence section for more information.

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Table 4. Am29DL400B Autoselect Codes (High Voltage Method)

A17

A11

A8

A5

DQ8

DQ7

to

to

to

to

to

to

Description

Mode

CE#

OE#

WE#

A12

A10

A9

A7

A6

A2

A1

A0

DQ15

DQ0

Manufacturer ID: AMD

L

L

H

BA

X

VID

X

L

X

L

L

X

01h

Device ID:

Word

L

L

H

22h

0C

Am29DL400B

BA

X

VID

X

L

X

L

H

Byte

L

L

H

X

0C

(Top Boot Block)

Device ID:

Word

L

L

H

22h

0F

Am29DL400B

BA

X

VID

X

L

X

L

H

Byte

L

L

H

X

0F

(Bottom Boot Block)

X

01h

(protected)

Sector Protection Verification

L

L

H

SA

X

VID

X

L

X

H

L

X

00h

(unprotected)

Note: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods.

The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle.

The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 22145 contains further details; contact an AMD representative to request a copy.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE-

SET# pin to VID (11.5 V – 12.5 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature.

START

RESET# = VID

(Note 1)

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

21606C-5

Notes:

1.All protected sectors unprotected.

2.All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

Am29DL400B

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