PRELIMINARY
Am29LV400
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
—Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
—Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors
■High performance
—Full voltage range: access times as fast as 100 ns
—Regulated voltage range: access times as fast as 90 ns
■Ultra low power consumption (typical values at 5 MHz)
—200 nA Automatic Sleep mode current
—200 nA standby mode current
—10 mA read current
—20 mA program/erase current
■Flexible sector architecture
—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)
—One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)
—Supports full chip erase
—Sector Protection features:
A hardware method of locking a sector to prevent any program or erase operations within that sector
Sectors can be locked via programming equipment
Temporary Sector Unprotect feature allows code changes in previously locked sectors
■Top or bottom boot block configurations available
■Embedded Algorithms
—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors
—Embedded Program algorithm automatically writes and verifies data at specified addresses
■Typical 1,000,000 write cycles per sector (100,000 cycles minimum guaranteed)
■Package option
—48-ball FBGA
—48-pin TSOP
—44-pin SO
■Compatibility with JEDEC standards
—Pinout and software compatible with singlepower supply Flash
—Superior inadvertent write protection
■Data# Polling and toggle bits
—Provides a software method of detecting program or erase operation completion
■Ready/Busy# pin (RY/BY#)
—Provides a hardware method of detecting program or erase cycle completion
■Erase Suspend/Erase Resume
—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
■Hardware reset pin (RESET#)
—Hardware method to reset the device to reading array data
Publication# 20514 Rev: C Amendment/+1
Issue Date: March 1998
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV400 is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers.
The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Am29LV400 |
2 |
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number |
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Am29LV400 |
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Speed Options |
Regulated Voltage Range: VCC =3.0–3.6 V |
-90R |
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Full Voltage Range: VCC = 2.7–3.6 V |
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-100 |
-120 |
-150 |
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Max access time, ns (tACC) |
90 |
100 |
120 |
150 |
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Max CE# access time, ns (tCE) |
90 |
100 |
120 |
150 |
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Max OE# access time, ns (tOE) |
40 |
40 |
40 |
55 |
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Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
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RY/BY# |
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DQ0–DQ15 (A-1) |
VCC |
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Sector Switches |
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VSS |
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RESET# |
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Erase Voltage |
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Input/Output |
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Generator |
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Buffers |
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WE# |
State |
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BYTE# |
Control |
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Command |
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Register |
PGM Voltage |
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Generator |
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Chip Enable |
STB |
Data |
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Latch |
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CE# |
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Output Enable |
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OE# |
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Logic |
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STB |
Y-Decoder |
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Y-Gating |
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VCC Detector |
Timer |
Latch |
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Address |
X-Decoder |
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Cell Matrix |
A0–A17 |
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20514C-1 |
3 |
Am29LV400 |
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
NC 9
NC 10
WE# 11
RESET# 12
NC 13
NC 14
RY/BY# 15
NC 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
A16 |
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1 |
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BYTE# |
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2 |
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VSS |
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3 |
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DQ15/A-1 |
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4 |
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DQ7 |
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5 |
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DQ14 |
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6 |
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DQ6 |
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7 |
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DQ13 |
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8 |
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DQ5 |
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9 |
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DQ12 |
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10 |
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DQ4 |
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11 |
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VCC |
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12 |
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DQ11 |
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13 |
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DQ3 |
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14 |
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DQ10 |
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15 |
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DQ2 |
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16 |
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DQ9 |
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17 |
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DQ1 |
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18 |
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DQ8 |
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19 |
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DQ0 |
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20 |
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OE# |
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21 |
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VSS |
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22 |
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CE# |
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23 |
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A0 |
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24 |
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48 |
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A16 |
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47 |
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BYTE# |
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46 |
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VSS |
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45 |
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DQ15/A-1 |
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44 |
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DQ7 |
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43 |
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DQ14 |
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42 |
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DQ6 |
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41 |
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DQ13 |
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40 |
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DQ5 |
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39 |
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DQ12 |
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Standard TSOP |
38 |
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DQ4 |
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37 |
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VCC |
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36 |
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DQ11 |
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35 |
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DQ3 |
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34 |
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DQ10 |
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33 |
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DQ2 |
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32 |
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DQ9 |
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31 |
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DQ1 |
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30 |
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DQ8 |
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29 |
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DQ0 |
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28 |
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OE# |
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27 |
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VSS |
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26 |
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CE# |
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25 |
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A0 |
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48 |
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A15 |
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47 |
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A14 |
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46 |
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A13 |
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45 |
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A12 |
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44 |
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A11 |
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43 |
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A10 |
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42 |
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A9 |
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41 |
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A8 |
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40 |
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NC |
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39 |
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NC |
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38 |
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WE# |
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Reverse TSOP |
37 |
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RESET# |
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36 |
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NC |
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35 |
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NC |
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34 |
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RY/BY# |
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33 |
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NC |
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32 |
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A17 |
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31 |
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A7 |
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30 |
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A6 |
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29 |
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A5 |
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28 |
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A4 |
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27 |
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A3 |
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26 |
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A2 |
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25 |
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A1 |
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20514C-2
Am29LV400 |
4 |
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P R E L I M I N A R Y |
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CONNECTION DIAGRAMS |
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NC |
1 |
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44 |
RESET# |
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RY/BY# |
2 |
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43 |
WE# |
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A17 |
3 |
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42 |
A8 |
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A7 |
4 |
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41 |
A9 |
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A6 |
5 |
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40 |
A10 |
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A5 |
6 |
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39 |
A11 |
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A4 |
7 |
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38 |
A12 |
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A3 |
8 |
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37 |
A13 |
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A2 |
9 |
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36 |
A14 |
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A1 |
10 |
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35 |
A15 |
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A0 |
11 |
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SO |
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34 |
A16 |
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CE# 12 |
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33 BYTE# |
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VSS 13 |
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32 |
VSS |
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OE# 14 |
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31 |
DQ15/A-1 |
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DQ0 15 |
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30 |
DQ7 |
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DQ8 16 |
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29 |
DQ14 |
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DQ1 17 |
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28 |
DQ6 |
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DQ9 18 |
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27 |
DQ13 |
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DQ2 19 |
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26 |
DQ5 |
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DQ10 20 |
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25 |
DQ12 |
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DQ3 21 |
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24 |
DQ4 |
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DQ11 22 |
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23 |
VCC |
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FBGA
Bump Side (Bottom) View
A1 |
B1 |
C1 |
D1 |
E1 |
F1 |
G1 |
H1 |
A3 |
A4 |
A2 |
A1 |
A0 |
CE# |
OE# |
VSS |
A2 |
B2 |
C2 |
D2 |
E2 |
F2 |
G2 |
H2 |
A7 |
A17 |
A6 |
A5 |
DQ0 |
DQ8 |
DQ9 |
DQ1 |
A3 |
B3 |
C3 |
D3 |
E3 |
F3 |
G3 |
H3 |
RY/BY# |
NC |
NC |
NC |
DQ2 |
DQ10 |
DQ11 |
DQ3 |
A4 |
B4 |
C4 |
D4 |
E4 |
F4 |
G4 |
H4 |
WE# |
RESET# |
NC |
NC |
DQ5 |
DQ12 |
VCC |
DQ4 |
A5 |
B5 |
C5 |
D5 |
E5 |
F5 |
G5 |
H5 |
A9 |
A8 |
A10 |
A11 |
DQ7 |
DQ14 |
DQ13 |
DQ6 |
A6 |
B6 |
C6 |
D6 |
E6 |
F6 |
G6 |
H6 |
A13 |
A12 |
A14 |
A15 |
A16 |
BYTE# |
DQ15/A-1 |
VSS |
20514C-3
5 |
Am29LV400 |
P R E L I M I N A R Y
Special Handling Instructions for Fine PItch Ball Grid Array (FBGA)
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. T h e p a c k a g e a n d / o r d a t a i n t e g r i t y m a y b e compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
PIN CONFIGURATION
A0–A17 = 18 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 |
= DQ15 (data input/output, word mode), |
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A-1 (LSB address input, byte mode) |
BYTE# |
= Selects 8-bit or 16-bit mode |
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CE# |
= |
Chip enable |
OE# |
= |
Output enable |
WE# |
= |
Write enable |
RESET# |
= Hardware reset pin, active low |
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RY/BY# |
= |
Ready/Busy# output |
VCC |
= 3.0 volt-only single power supply |
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(see Product Selector Guide for speed |
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options and voltage supply tolerances) |
VSS |
= |
Device ground |
NC |
= Pin not connected internally |
LOGIC SYMBOL
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18 |
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A0–A17 |
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16 or 8 |
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DQ0–DQ15 |
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CE# |
(A-1) |
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OE# |
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WE# |
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RESET# |
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BYTE# |
RY/BY# |
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20514C-4
Am29LV400 |
6 |
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29LV400 |
T |
70R |
E |
C |
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E |
= 48-Pin Thin Small Outline Package (TSOP) |
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Standard Pinout (TS 048) |
F |
= 48-Pin Thin Small Outline Package (TSOP) |
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Reverse Pinout (TSR048) |
S |
= 44-Pin Small Outline Package (SO 044) |
WA |
= 48-ball Fine Pitch Ball Grid Array (FBGA) |
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0.80 mm pitch, 6 x 8 mm package |
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV400
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
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Valid Combinations |
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Am29LV400T70R, |
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EC, EI, FC, |
Am29LV400B70R |
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FI, SC, SI, WAC |
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Am29LV400T80, |
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Am29LV400B80 |
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EC, EI, EE, |
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Am29LV400T90, |
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FC, FI, FE, |
Am29LV400B90 |
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SC, SI, SE, |
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WAC, WAI, WAE |
Am29LV400T120, |
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Am29LV400B120 |
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Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
7 |
Am29LV400 |
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1. Am29LV400 Device Bus Operations
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DQ8–DQ15 |
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Addresses |
DQ0– |
BYTE# |
BYTE# |
Operation |
CE# |
OE# |
WE# |
RESET# |
(See Note) |
DQ7 |
= VIH |
= VIL |
Read |
L |
L |
H |
H |
AIN |
DOUT |
DOUT |
DQ8–DQ14 = High-Z, |
Write |
L |
H |
L |
H |
AIN |
DIN |
DIN |
DQ15 = A-1 |
|
||||||||
Standby |
VCC ± |
X |
X |
VCC ± |
X |
High-Z |
High-Z |
High-Z |
|
0.3 V |
|
|
0.3 V |
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|
|
Output Disable |
L |
H |
H |
H |
X |
High-Z |
High-Z |
High-Z |
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Reset |
X |
X |
X |
L |
X |
High-Z |
High-Z |
High-Z |
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|
|
|
|
Temporary Sector Unprotect |
X |
X |
X |
VID |
AIN |
DIN |
DIN |
High-Z |
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out
Note: Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 12 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.
An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section
Am29LV400 |
8 |
P R E L I M I N A R Y
has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
ICC3 in the DC Characteristics table represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t A C C + 30 ns . The automatic sl eep m ode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
9 |
Am29LV400 |
P R E L I M I N A R Y
Table 2. Am29LV400T Top Boot Block Sector Address Table
|
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|
|
Sector Size |
Address Range (in hexadecimal) |
|
|
|
|
|
|
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|
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|
|
(Kbytes/ |
(x8) |
(x16) |
Sector |
A17 |
A16 |
A15 |
A14 |
A13 |
A12 |
Kwords) |
Address Range |
Address Range |
|
|
|
|
|
|
|
|
|
|
SA0 |
0 |
0 |
0 |
X |
X |
X |
64/32 |
00000h–0FFFFh |
00000h–07FFFh |
|
|
|
|
|
|
|
|
|
|
SA1 |
0 |
0 |
1 |
X |
X |
X |
64/32 |
10000h–1FFFFh |
08000h–0FFFFh |
|
|
|
|
|
|
|
|
|
|
SA2 |
0 |
1 |
0 |
X |
X |
X |
64/32 |
20000h–2FFFFh |
10000h–17FFFh |
|
|
|
|
|
|
|
|
|
|
SA3 |
0 |
1 |
1 |
X |
X |
X |
64/32 |
30000h–3FFFFh |
18000h–1FFFFh |
|
|
|
|
|
|
|
|
|
|
SA4 |
1 |
0 |
0 |
X |
X |
X |
64/32 |
40000h–4FFFFh |
20000h–27FFFh |
|
|
|
|
|
|
|
|
|
|
SA5 |
1 |
0 |
1 |
X |
X |
X |
64/32 |
50000h–5FFFFh |
28000h–2FFFFh |
|
|
|
|
|
|
|
|
|
|
SA6 |
1 |
1 |
0 |
X |
X |
X |
64/32 |
60000h–6FFFFh |
30000h–37FFFh |
|
|
|
|
|
|
|
|
|
|
SA7 |
1 |
1 |
1 |
0 |
X |
X |
32/16 |
70000h–77FFFh |
38000h–3BFFFh |
|
|
|
|
|
|
|
|
|
|
SA8 |
1 |
1 |
1 |
1 |
0 |
0 |
8/4 |
78000h–79FFFh |
3C000h–3CFFFh |
|
|
|
|
|
|
|
|
|
|
SA9 |
1 |
1 |
1 |
1 |
0 |
1 |
8/4 |
7A000h–7BFFFh |
3D000h–3DFFFh |
|
|
|
|
|
|
|
|
|
|
SA10 |
1 |
1 |
1 |
1 |
1 |
X |
16/8 |
7C000h–7FFFFh |
3E000h–3FFFFh |
|
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|
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Table 3. Am29LV400B Bottom Boot Block Sector Address Table
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|
Sector Size |
Address Range (in hexadecimal) |
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|
(Kbytes/ |
(x8) |
(x16) |
Sector |
A17 |
A16 |
A15 |
A14 |
A13 |
A12 |
Kwords) |
Address Range |
Address Range |
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|
SA0 |
0 |
0 |
0 |
0 |
0 |
X |
16/8 |
00000h–03FFFh |
00000h–01FFFh |
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|
SA1 |
0 |
0 |
0 |
0 |
1 |
0 |
8/4 |
04000h–05FFFh |
02000h–02FFFh |
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|
SA2 |
0 |
0 |
0 |
0 |
1 |
1 |
8/4 |
06000h–07FFFh |
03000h–03FFFh |
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|
|
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|
|
|
|
SA3 |
0 |
0 |
0 |
1 |
X |
X |
32/16 |
08000h–0FFFFh |
04000h–07FFFh |
|
|
|
|
|
|
|
|
|
|
SA4 |
0 |
0 |
1 |
X |
X |
X |
64/32 |
10000h–1FFFFh |
08000h–0FFFFh |
|
|
|
|
|
|
|
|
|
|
SA5 |
0 |
1 |
0 |
X |
X |
X |
64/32 |
20000h–2FFFFh |
10000h–17FFFh |
|
|
|
|
|
|
|
|
|
|
SA6 |
0 |
1 |
1 |
X |
X |
X |
64/32 |
30000h–3FFFFh |
18000h–1FFFFh |
|
|
|
|
|
|
|
|
|
|
SA7 |
1 |
0 |
0 |
X |
X |
X |
64/32 |
40000h–4FFFFh |
20000h–27FFFh |
|
|
|
|
|
|
|
|
|
|
SA8 |
1 |
0 |
1 |
X |
X |
X |
64/32 |
50000h–5FFFFh |
28000h–2FFFFh |
|
|
|
|
|
|
|
|
|
|
SA9 |
1 |
1 |
0 |
X |
X |
X |
64/32 |
60000h–6FFFFh |
30000h–37FFFh |
|
|
|
|
|
|
|
|
|
|
SA10 |
1 |
1 |
1 |
X |
X |
X |
64/32 |
70000h–7FFFFh |
38000h–3FFFFh |
|
|
|
|
|
|
|
|
|
|
Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A171:A0 in word mode. See “Word/Byte Configuration” section for more information.
Am29LV400 |
10 |
P R E L I M I N A R Y
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.
Table 4. Am29LV400 Autoselect Codes (High Voltage Method)
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A17 |
A11 |
|
A8 |
|
A5 |
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|
DQ8 |
DQ7 |
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to |
to |
|
to |
|
to |
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|
to |
to |
Description |
Mode |
CE# |
OE# |
WE# |
A12 |
A10 |
A9 |
A7 |
A6 |
A2 |
A1 |
A0 |
DQ15 |
DQ0 |
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Manufacturer ID: AMD |
L |
L |
H |
X |
X |
VID |
X |
L |
X |
L |
L |
X |
01h |
||
Device ID: |
Word |
L |
L |
H |
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22h |
B9h |
Am29LV400 |
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X |
X |
VID |
X |
L |
X |
L |
H |
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|
Byte |
L |
L |
H |
|
X |
B9h |
|||||||||
(Top Boot Block) |
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||||||
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Device ID: |
Word |
L |
L |
H |
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22h |
BAh |
Am29LV400 |
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X |
X |
VID |
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X |
L |
X |
L |
H |
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|||||
(Bottom Boot |
Byte |
L |
L |
H |
X |
BAh |
|||||||||
Block) |
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X |
01h |
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(protected) |
|
Sector Protection Verification |
L |
L |
H |
SA |
X |
VID |
X |
L |
X |
H |
L |
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||
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|||||||||||||
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X |
00h |
|||||||||||||
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||
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(unprotected) |
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L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.
Sector protection/unprotection is implemented using programming equipment, and requires VID on address pin A9 and OE#. Publication number 20873 contains further details; contact an AMD representative to request a copy.
The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.
It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 21 shows the timing diagrams, for this feature.
11 |
Am29LV400 |
P R E L I M I N A R Y
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
20514C-5
Notes:
1.All protected sectors unprotected.
2.All previously protected sectors are protected once again.
Figure 1. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Am29LV400 |
12 |