Ordering number : EN5823
CMOS IC
LC35256D-10, LC35256DM, DT-70/10
Dual Control Pins: OE and CE
256K (32768-word × 8-bit) SRAM
Overview
The LC35256D, LC35256DM, and LC35256DT are 32768-word × 8-bit asynchronous silicon gate CMOS static RAMs. These devices use a 6-transistor full CMOS memory cell, and feature low-voltage operation, low current drain, and an ultralow standby current. They provide two control signal inputs: an OE input for highspeed access and a chip select (CE) input for device selection and low power operating mode. This makes these devices optimal for systems that require low power or battery backup, and they allow memory to be expanded easily. Their ultralow standby current allows capacitorbased backup to be used as well. Since they support 3-V operation, they are appropriate for use in portable systems that operate from batteries.
Features
•Supply voltage range: 2.7 to 5.5 V
— 5-V operation: 5.0 V±10%
— 3-V operation: 2.7 to 3.6 V
•Access times
—5-V operation
LC35256DM, DT-70: 70 ns (max) LC35256D, DM, DT-10: 100 ns (max)
—3-V operation
LC35256DM, DT-70: 200 ns (max) LC35256D, DM, DT-10: 500 ns (max)
•Standby current
—5-V operation: 1.0 µA (Ta ≤ 60°C),
5.0µA (Ta ≤ 85°C)
—3-V operation: 0.8 µA (Ta ≤ 60°C),
4.0µA (Ta ≤ 85°C)
•Operating temperature range: –40 to +85°C
•Data retention supply voltage: 2.0 to 5.5 V
•All I/O levels
—5-V operation: TTL compatible
—3-V operation: VCC – 0.2 V/0.2 V
•Shared I/O pins and 3-state outputs
•No clock signal required.
•Packages
—28-pin DIP (600 mil) plastic package: LC35256D
—28-pin SOP (450 mil) plastic package: LC35256DM
—28-pin TSOP (8 × 13.4 mm) plastic package: LC35256DT
Package Dimensions
unit: mm
3012A-DIP28
[LC35256D]
SANYO: DIP28
unit: mm
3187-SOP28D
[LC35256DM]
SANYO: SOP28D
unit: mm
3221-TSOP28(type-I)
[LC35256DT]
SANYO: TSOP28(type-I)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51398RM (OT) No. 5823-1/8
LC35256D-10, LC35256DM, DT-70/10
Pin Assignment
Block Diagram
Address buffer |
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Row decoder |
Input data buffer |
Input data control circuit |
Memory cell array
Column |
Output |
I/O circuit |
data |
buffer
Column decoder
Address buffer
Pin Functions
A0 to A14 |
Address inputs |
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Read/write control input |
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WE |
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Output enable input |
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OE |
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Chip enable input |
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CE |
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I/O1 to I/O8 |
Data I/O |
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VCC, GND |
Power supply, ground |
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No. 5823-2/8
LC35256D-10, LC35256DM, DT-70/10
Function Table
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Mode |
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CE |
OE |
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WE |
I/O |
Supply current |
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Read cycle |
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L |
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L |
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H |
Data output |
ICCA |
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Write cycle |
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L |
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X |
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L |
Data input |
ICCA |
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Output disable |
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L |
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H |
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H |
High-impedance |
ICCA |
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Unselected |
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H |
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X |
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X |
High-impedance |
ICCS |
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X : H or L |
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Specifications
Absolute Maximum Ratings
Parameter |
Symbol |
Conditions |
Ratings |
Unit |
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Maximum supply voltage |
VCC max |
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7.0 |
V |
Input pin voltage |
VIN |
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–0.3* to VCC + 0.3 |
V |
I/O pin voltage |
VI/O |
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–0.3 to VCC + 0.3 |
V |
Operating temperature |
Topr |
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–40 to +85 |
°C |
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Storage temperature |
Tstg |
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–55 to +125 |
°C |
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Note *: –3.0 V for pulse widths of up to 30 ns.
I/O Capacitances at Ta = 25°C, f = 1 MHz
Parameter |
Symbol |
Conditions |
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Ratings |
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Unit |
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min |
typ |
max |
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I/O pin capacitance |
CI/O |
VI/O = 0 V |
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6 |
10 |
pF |
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Input pin capacitance |
CIN |
VIN = 0 V |
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6 |
10 |
pF |
Note: These parameters are not measured in all units, but rather are only measured in sampled units.
[5-V Operation]
DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V
Parameter |
Symbol |
Conditions |
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Ratings |
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Unit |
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min |
typ |
max |
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Supply voltage |
VCC |
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4.5 |
5.0 |
5.5 |
V |
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Input voltages |
VIH |
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2.2 |
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VCC + 0.3 |
V |
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VIL |
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–0.3* |
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+0.8 |
V |
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Note *: –3.0 V for pulse widths of up to 30 ns.
DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V
Parameter |
Symbol |
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Conditions |
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Ratings |
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Unit |
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min |
typ* |
max |
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Input leakage current |
ILI |
VIN = 0 to VCC |
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–1.0 |
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+1.0 |
µA |
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Output leakage current |
ILO |
V |
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= VIH or V |
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= VIH or V |
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= VIL, VI/O = 0 to VCC |
–1.0 |
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+1.0 |
µA |
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CE |
OE |
WE |
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High-level output voltage |
VOH |
IOH = –1.0 mA |
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2.4 |
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V |
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Low-level output voltage |
VOL |
IOL = 2.0 mA |
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0.4 |
V |
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ICCA2 |
V |
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= VIL, II/O = 0 mA, VIN = VIH or VIL |
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5.0 |
mA |
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CE |
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Operating |
TTL inputs |
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V |
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= VIL, VIN |
= VIH or VIL, |
min |
LC35256DM, DT-70 |
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35 |
40 |
mA |
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current drain |
ICCA3 |
CE |
cycle |
LC35256D, DM, DT-10 |
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25 |
30 |
mA |
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II/O = 0 mA, Duty 100% |
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1 µs cycle |
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3.5 |
6.0 |
mA |
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VCC – 0.2 V/ |
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V |
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≥ VCC – 0.2 V, |
Ta ≤ 25°C |
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0.01 |
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µA |
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CE |
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Standby mode |
ICCS1 |
Ta ≤ 60°C |
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1.0 |
µA |
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0.2 V inputs |
VIN = 0 to VCC |
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current drain |
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Ta ≤ 85°C |
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5.0 |
µA |
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TTL inputs |
ICCS2 |
V |
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= VIH, VIN = 0 to VCC |
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1.0 |
mA |
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CE |
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Note *: Reference value at Ta = 25°C, VCC = 5 V.
No. 5823-3/8
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