SANYO LC6529F, LC6529N, LC6529L Datasheet

Ordering number : EN*5117

CMOS LSI

LC6529N, LC6529F, LC6529L

4-Bit Microcomputer for Small-Scale Control Applications

Preliminary

Overview

The LC6529N/F/L provides the basic architecture and instruction set of the Sanyo LC6500 Series of 4-bit singlechip microcomputers in a version specially for small-scale control applications involving circuits built with standard logic elements, applications using simple, comparatorbased voltage or phase detectors, or other applications controlling a limited number of controls. The LC6529F is a replacement for the former LC6529H. (Certain functions differ, however.) The N (medium-speed) and L (powersaving) versions are new additions to the lineup.

•Choice of clock oscillator options to match system specifications

—Oscillator circuit options: 2-pin RC oscillator circuit (N and L versions) or 2-pin ceramic oscillator circuit (N, F, and L versions)

—Frequency divider options: Built-in 1/3 and 1/4 frequency dividers that eliminate the need for external frequency dividers

Features

•Power-saving CMOS design (Standby mode accessed with HALT instruction included.)

•Memory: 1 kilobyte of 8-bit ROM and 64 words of 4-bit RAM

•Instruction set: 51-member subset of LC6500 standard complement of 80 instructions

•(L version) Wide range of operating voltages: 2.2 to 6.0 V

•(F version) 0.92 µs/3.0 V instruction cycle time

•Flexible I/O ports

Four ports with up to 16 lines

— Bidirectional I/O ports: 12

Dedicated input ports: 4 (These double as comparator inputs.)

— I/O voltage limit: max. +15 V (open-drain configuration)

— Output current: max. 20 mA sink current (capable of directly driving an LED)

Choice of options to match system specifications

— Choice of open-drain or pull-up resistor output configurations at the bit level for all ports

— Choice of reset output levels for Ports C and D in groups of 4 bits each

Port E configurable as four comparator inputs

•Stack: Four levels

•Timers: 4-bit prescaler plus 8-bit programmable counter

•Comparators: 4 channels (2 reference levels) Separator reference level for each channel pair

— Feedback resistor option for choice of input with or without hysteresis

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

92995HA (OT) No. 5117-1/39

LC6529N, LC6529F, LC6529L

Summary of Functions

	Item	LC6529N	LC6529F	LC6529L
	[Memory]
	ROM	1024 × 8 bits	1024 × 8 bits	1024 × 8 bits
	RAM	64 × 4 bits	64 × 4 bits	64 × 4 bits
	Instruction set	51	51	51
	[On-board functions]
	Timers	4-bit prescaler plus 8-bit	4-bit prescaler plus 8-bit	4-bit prescaler plus 8-bit
		programmable counter	programmable counter	programmable counter
	Stack levels	4	4	4
	Standby mode	HALT instruction places chip	HALT instruction places chip	HALT instruction places chip
		on standby.	on standby.	on standby.
	Comparators	4 channels (2 reference levels)	4 channels (2 reference levels)	4 channels (2 reference levels)
	[I/O ports]
	Number of ports	12 bidirectional I/O pins, 4 input pins	12 bidirectional I/O pins, 4 input pins	12 bidirectional I/O pins, 4 input pins
	I/O voltage limit	max. 15 V (ports A, C, and D)	max. 15 V (ports A, C, and D)	max. 15 V (ports A, C, and D)
	Output current	10 mA typ. 20 mA max.	10 mA typ. 20 mA max.	10 mA typ. 20 mA max.
	I/O circuit configuration	Choice of open-drain output or pull-up resistors at the bit level for ports A, C, and D
	Reset output level	Choice of high or low in groups of 4 bits each (ports C and D)
	Port function	Port E configurable as four comparator inputs
	[Characteristics]
	Minimum cycle time	2.77 µs (VDD ≥ 3.0 V)	0.92 µs (VDD ≥ 3.0 V)	3.84 µs (VDD ≥ 2.2 V)
	Operating temperature	–40 to +85°C	–40 to +85°C	–40 to +85°C
	Power supply voltage	3.0 to 6.0 V	3.0 to 6.0 V	2.2 to 6.0 V
	Current drain	1.1 mA typ.	1.6 mA typ.	1.0 mA typ.
	[Clock]
		RC (850 kHz, 400 kHz typ.)		RC (400 kHz typ.)
	Oscillator	Ceramic oscillator (400 kHz, 800 kHz,	Ceramic oscillator (2 MHz, 4 MHz)	Ceramic oscillator (400 kHz, 800 kHz,
		2 MHz, 4 MHz)		2 MHz, 4 MHz)
	Frequency divider options	1/1, 1/3, 1/4	1/1	1/1, 1/3, 1/4
	[Miscellaneous]
	Package	DIP24S, SSOP24, MFP30S	DIP24S, SSOP24, MFP30S	DIP24S, SSOP24, MFP30S
	OTP	Included	Included	Included

Note: The oscillator constants will be announced once the recommended circuit design has been decided.

No. 5117-2/39

LC6529N, LC6529F, LC6529L

Pin Assignments

MFP30S

DIP24S/SSOP24

Note: Do not use dip-soldering when mounting the SSOP package on the circuit board.

Package Dimensions

unit: mm

3073A-MFP30S

[LC6529N, 6529F, 6529L]

SANYO: MFP30S

unit: mm

3067-DIP24S

[LC6529N, 6529F, 6529L]

SANYO: DIP24S

unit: mm

3175A-SSOP24

[LC6529N, 6529F, 6529L]

SANYO: SSOP24

Note: The above diagrams give only the nominal dimensions. Contact Sanyo for drawings complete with tolerances.

No. 5117-3/39

		LC6529N, LC6529F, LC6529L
Pin Names
OSC1, OSC2:		Pins for RC or ceramic oscillator circuit
TEST:		Test pin
RES:		Reset pin
PA0 to PA3:		Bidirectional I/O port A, bits 0 to 3
PC0 to PC3:		Bidirectional I/O port C, bits 0 to 3
PD0 to PD3:		Bidirectional I/O port D, bits 0 to 3
PE0 to PE3:		Unidirectional input port E, bits 0 to 3

CMP0 to CMP3: Comparator input port, bits 0 to 3

VREF0, VREF1: Reference inputs

System Block Diagram

RAM:	Data memory	ROM:	Program memory
AC:	Accumulator	PC:	Program Counter
ALU:	Arithmetic and Logic Unit	IR:	Instruction Register
DP:	Data pointer	I.DEC:	Instruction Decoder
E:	E register	CF:	Carry Flag
OSC:	Oscillator circuit	ZF:	Zero Flag
TM:	Timer	TMF:	Timer overflow Flag
STS:	Status register

No. 5117-4/39

LC6529N, LC6529F, LC6529L

Pin Functions

Pin No.	Symbol			I/O		Function		Output driver type		Options	State after reset
1		VDD		—	Power supply. Normally +5 V.					—	—
1		VSS		—	Power supply. 0 V.					—	—
									1. 2-pin RC oscillator circuit
1	OSC1			I	Pins for attaching external system				(1-pin external clock)
									2. 2-pin ceramic oscillator circuit
1	OSC2			O	clock oscillator circuit (RC or ceramic)
									3. Frequency divider options:
									1/1, 1/3, 1/4
					•	Bidirectional I/O port A0 to A3: 4-bit	•	N channel: sink
						input (IP instruction), 4-bit output (OP
						instruction), 1-bit conditionals (BP		current type
		PA0					•	I/O voltage limit for	1. Open-drain output
						and BNP instructions), 1-bit set and
4		PA1		I/O		reset (SPB and RPB instructions)		open-drain	2. Pull-up resistor		High output (output
		PA2			• PA3 also doubles as standby			configuration: max.	•	Choice of configuration 1. or 2. at	N channel transistor
								+15 V		bit level	off)
						operation control.
		PA3					•	P channel: high-
					•	Block chattering from entering PA3
								impedance pull-up
						during the HALT instruction
								type
						execution cycle.
							•	N channel: sink	1. Open-drain output
								current type
					•	Bidirectional I/O port C0 to C3.			2. Pull-up resistor
		PC0					•	I/O voltage limit for
						Functions the same as PA0 to PA3			3. High output after reset
								open-drain
		PC1				except that there is no the standby
4				I/O				configuration: max.	4. Low output after reset		High or low (option)
		PC2				operation control.
								+15 V	•	Choice of configuration 1. or 2. at
					•	Option controls whether output is
		PC3					•	P channel: low-		bit level
						high or low after reset.
									•	Choice of configuration 3. or 4. at
								impedance pull-up
										port (4-bit) level
								type
							•	N channel: sink	1. Open-drain output
								current type
									2. Pull-up resistor
		PD0					•	I/O voltage limit for
									3. High output after reset
		PD1			Bidirectional I/O port D0 to D3.			open-drain
4				I/O	Functions and options the same as			configuration: max.	4. Low output after reset		High or low (option)
		PD2
					PC0 to PC3.			+15 V	•	Choice of configuration 1. or 2. at
		PD3					•	P channel: high-		bit level
									•	Choice of configuration 3. or 4. at
								impedance pull-up
										port (4-bit) level
								type
					• When configured for comparator
						input: CMP0 and CMP1 use
						reference voltage VREF0; CMP2 and			1. Comparator input
4				I		CMP3 use reference voltage VREF1.			2. Port E input
	PE0/CMP0				• 4-bit (CMP0 to 3) input (IP
									3. Without feedback resistor
	PE1/CMP1					instruction)
									4. With feedback resistor
	PE2/CMP2				•	1-bit conditionals (BP and BNP
									•	Choice of configuration 1. or 2. at
						instructions)
	PE3/CMP3									port (4-bit) level
					•	When configured for port E input:
									•	Options 3. and 4. only available
4				I	•	4-bit (E0-3) input (IP instruction)				with 1.
					•	1-bit conditionals (BP and BNP
						instructions)
					•	Comparator reference level inputs:
						CMP0 and CMP1 use reference
2	VREF0			I		voltage VREF0; CMP2 and CMP3
	VREF1					use reference voltage VREF1.
					• Connect to VSS when PE0/CMP0 to
						PE3/CMP3 configured as port E.
					•	System reset input
					•	Connect external capacitor for power
1		RES		I		up reset.
					•	Low level input for a minimum of four
						clock cycles triggers a reset.
1	TEST			I	Chip test pin. Normally connect to VSS.

No. 5117-5/39

LC6529N, LC6529F, LC6529L

Oscillator Circuit Options

	Name		Circuit diagram		Conditions, etc.
	External clock				Leave OSC2 open.
	2-pin RC oscillator circuit
	2-pin ceramic oscillator circuit
	Frequency Divider Options
	Name		Circuit diagram		Conditions, etc.
	No frequency divider (1/1)				Available with all three oscillator circuit options
					(N, F, and L versions)
	1/3 frequency divider				Available only with external clock and ceramic
					oscillator circuit options (N and L versions)
	1/4 frequency divider				Available only with external clock and ceramic
					oscillator circuit options (N and L versions)
	Frequency Divider Options
	LC6529N
	Oscillator circuit	Frequency	Frequency divider options	VDD range	Note
			(cycle time)
		400 kHz	1/1 (10 µs)	3 to 6 V	1/3 and 1/4 frequency divider options
					not available
			1/1 (5 µs)	3 to 6 V
		800 kHz	1/3 (15 µs)	3 to 6 V
	Ceramic oscillator		1/4 (20 µs)	3 to 6 V
		2 MHz	1/3 (6 µs)	3 to 6 V	1/1 frequency divider option not available
			1/4 (8 µs)	3 to 6 V
		4 MHz	1/3 (3 µs)	3 to 6 V	1/1 frequency divider option not available
			1/4 (4 µs)	3 to 6 V
	External clock based on RC	200 k to 1444 kHz	1/1 (20 to 2.77 µs)	3 to 6 V
		600 k to 4330 kHz	1/3 (20 to 2.77 µs)	3 to 6 V
	oscillator circuit
		800 k to 4330 kHz	1/4 (20 to 3.70 µs)	3 to 6 V
		Use 1/1 frequency divider and recommended
		constants or, if this is not possible, one of the
	RC oscillator circuit	frequency, frequency divider option, and VDD range		3 to 6 V
		combinations listed for external clocks based on
		an RC oscillator circuit.
	External clock based on ceramic	This configuration not allowed. Use an external clock based on an RC oscillator circuit instead.
	oscillator circuit

No. 5117-6/39

LC6529N, LC6529F, LC6529L

LC6529F

	Oscillator circuit	Frequency	Frequency divider options	VDD range	Note
			(cycle time)
	Ceramic oscillator	4 MHz	1/1 (1 µs)	3 to 6 V
	External clock based on RC	200 k to 4330 kHz	1/1 (20 to 0.92 µs)	3 to 6 V
	oscillator circuit
	External clock based on ceramic	This configuration not allowed. Use an external clock based on an RC oscillator circuit instead.
	oscillator circuit

LC6529L

	Oscillator circuit	Frequency	Frequency divider options	VDD range	Note
			(cycle time)
		400 kHz	1/1 (10 µs)	2.2 to 6 V	1/3 and 1/4 frequency divider options
					not available
			1/1 (5 µs)	2.2 to 6 V
		800 kHz	1/3 (15 µs)	2.2 to 6 V
	Ceramic oscillator		1/4 (20 µs)	2.2 to 6 V
		2 MHz	1/3 (6 µs)	2.2 to 6 V	1/1 frequency divider option not available
			1/4 (8 µs)	2.2 to 6 V
		4 MHz	1/4 (4 µs)	2.2 to 6 V	1/1 and 1/3 frequency divider options not
					available
	External clock based on RC	200 k to 1040 kHz	1/1 (20 to 3.84 µs)	2.2 to 6 V
		600 k to 3120 kHz	1/3 (20 to 3.84 µs)	2.2 to 6 V
	oscillator circuit
		800 k to 4160 kHz	1/4 (20 to 3.84 µs)	2.2 to 6 V
		Use 1/1 frequency divider and recommended
		constants or, if this is not possible, one of the
	RC oscillator circuit	frequency, frequency divider option, and VDD range		2.2 to 6 V
		combinations listed for external clocks based on
		an RC oscillator circuit.
	External clock based on ceramic	This configuration not allowed. Use an external clock based on an RC oscillator circuit instead.
	oscillator circuit

Reset Level Options for Ports C and D

The following two options are available for controlling the output levels of ports C and D in groups of four bits each.

Option	Conditions, etc.
High level output after reset	Selection affects all bits of port
Low level output after reset	Selection affects all bits of port

Comparator vs. Port E Configuration Option

The four pins PE0/CMP0 to PE3/CMP3 may be configured for comparator input or as port E.

Option	Conditions, etc.
Comparator input	Selection affects all bits of port
Port E input	Selection affects all bits of port

No. 5117-7/39

LC6529N, LC6529F, LC6529L

Comparator Options

The comparators offer the following two configuration options.

Name	Circuit diagram	Conditions, etc.
Without feedback resistor		The comparator does not use hysteresis.
With feedback resistor		The comparator, in combination with an
		external resistor, uses hysteresis.

Port Output Configurations

The bidirectional I/O ports A, C, and D offer a choice of two output configurations.

Name	Circuit diagram	Conditions, etc.
Open drain (OD)
		This option adds a high-impedance pull-up
With pull-up resistors (PU)		resistor for port A or D and a low-impedance
		one for port C.

No. 5117-8/39

LC6529N, LC6529F, LC6529L

Specifications

LC6529N

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter	Symbol				Conditions	min	typ		max		Unit
Maximum supply voltage	VDD max		VDD			–0.3				+7.0	V
	V	1	OSC1*1			–0.3		V	DD	+ 0.3
	I
Input voltage	VI2
			TEST,	RES		–0.3		VDD + 0.3			V
	VI3		Port E (PE) configuration			–0.3		VDD + 0.3
Output voltage	VO		OSC2			Voltages up to that generated allowed.					V
I/O voltages	VIO1		Open-drain (OD) configuration			–0.3				+15	V
	VIO2		Pull-up (PU) resistor configuration			–0.3		VDD + 0.3
Peak output current	IOP		PA, PC, PD			–2				+20	mA
	IOA		PA, PC, PD: Average for pin over 100-ms interval			–2				+20
Average output current	ΣIOA1		PA: Total current for pins PA0 to PA3*2			–6				+40	mA
	ΣIOA2		PC, PD: Total current for pins PC0 to PC3 and			–14				+90
			PD0 to PD3*2
	Pd max1		Ta = –40 to +85°C (DIP24S)							360
Allowable power dissipation	Pd max2		Ta = –40 to +85°C (SSOP24)							165	mW
	Pd max3		Ta = –40 to +85°C (MFP30S)							150
Operating temperature	Topr					–40				+85	°C
Storage temperature	Tstg					–55				+125

Note: 1. When the oscillator circuit in Figure 3 and the guaranteed constant are used, this is guaranteed over the full amplitude. 2. Averaged over 100-ms interval.

Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V

Parameter	Symbol					Conditions	min	typ	max	Unit
Supply voltage	VDD	VDD					3.0		6.0	V
Standby voltage	VST	VDD: Preserves contents of RAM and registers*.					1.8		6.0	V
	VIH1	Open-drain (OD) configuration: With output N-channel					0.7 VDD		13.5
		transistor off
	VIH2	Pull-up (PU) resistor configuration: With output					0.7 VDD		VDD
Input high level voltage		N-channel transistor off								V
	VIH3	PE: Using port E configuration					0.7 VDD		VDD
	VIH4					VDD = 1.8 to 6 V	0.8 VDD		VDD
				RES:
	VIH5	OSC1: Using external clock option					0.8 VDD		VDD
	VIL1	PA, PC, PD: With output N-channel transistor off,					VSS		0.3 VDD
		VDD = 4 to 6 V
	VIL2	PA, PC, PD: With output N-channel transistor off					VSS		0.25 VDD
	VIL3	PE: Using port E configuration, VDD = 4 to 6 V					VSS		0.3 VDD
	VIL4	PE: Using port E configuration					VSS		0.25 VDD
Input low level voltage	VIL5	OSC1: Using external clock option, VDD = 4 to 6 V					VSS		0.25 VDD	V
	VIL6	OSC1: Using external clock option					VSS		0.2 VDD
	VIL7	TEST: VDD = 4 to 6 V					VSS		0.3 VDD
	VIL8	TEST					VSS		0.25 VDD
	VIL9						VSS		0.25 VDD
			RES:		VDD = 4 to 6 V
	VIL10						VSS		0.2 VDD
			RES
Operating frequency	fop	Using the built-in 1/3 or 1/4 frequency dividers extends					200 (20)		1444 (2.77)	kHz (µs)
(cycle time)	(Tcyc)	the maximum to 4.33 MHz.

Note: * Maintain the power supply voltage at VDD until the HALT instruction has completed execution, placing the chip in the standby mode. Block chattering from entering PA3 during the HALT instruction execution cycle.

Continued on next page.

No. 5117-9/39

LC6529N, LC6529F, LC6529L

Continued from preceding page.

Parameter	Symbol	Conditions	min		typ	max	Unit
[External clock conditions]
Frequency	text		200			4330	kHz
		OSC1: If the clock frequency exceeds 1.444 MHz, use
Pulse width	textH, textL		69				ns
		the built-in 1/3 or 1/4 frequency divider. Figure 1
Rise/fall times	textR, textF					50
[Oscillator guaranteed constants]
	Cext	OSC1, OSC2: VDD = 4 to 6 V, Figure 2			220 ± 5%		pF
2-pin RC oscillator circuit	Cext	OSC1, OSC2: Figure 2			220 ± 5%
	Rext	OSC1, OSC2: VDD = 4 to 6 V, Figure 2			4.7 ± 1%		kΩ
	Rext	OSC1, OSC2: Figure 2			12.0 ± 1%
Ceramic oscillator		Figure 3	See Table 1.

Electrical Characteristics at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V

Parameter	Symbol			Conditions	min	typ	max	Unit
			Open-drain (OD) configuration for port: With output
	IIH1		N-channel transistor off. (Includes transistor’s leak				5.0
Input high level current			current.) VIN = 13.5 V					µA
	IIH2		PE: Using port E configuration, VIN = VDD				1.0
	IIH3		OSC1: Using external clock option, VIN = VDD				1.0
			Open-drain (OD) configuration for port: With output
	IIL1		N-channel transistor off. (Includes transistor’s leak		–1.0
			current.) VIN = VSS					µA
			Pull-up (PU) resistor configuration for port A or D:
	IIL2		With output N-channel transistor off. (Includes		–220	–71.5
Input low level current			transistor’s leak current.) VIN = VSS
			Pull-up (PU) resistor configuration for port C:
	IIL3		With output N-channel transistor off. (Includes		–6.00	–2.17		mA
			transistor’s leak current.) VIN = VSS
	IIL4		PE: Using port E configuration, VIN = VSS		–1.0
	IIL5				–45	–10		µA
			RES:	VIN = VSS
	IIL6		OSC1: Using external clock option, VIN = VSS		–1.0
	VOH1		Pull-up (PU) resistor configuration for port C:		VDD – 1.2
			IOH = –300 µA, VDD = 4 to 6 V
Output high level voltage								V
	VOH2		Pull-up (PU) resistor configuration for port C:		VDD – 0.5
			IOH = –60 µA
	VOL1		PA, PC, PD: IOL = 10 mA, VDD = 4 to 6 V				1.5
Output low level voltage	VOL2		PA, PC, PD: With IOL for each port less than or equal				0.4	V
			to 1 mA, IOL = 1.8 mA
	VHIS1					0.1 VDD
Hysteresis voltage			RES					V
	VHIS2		OSC1*: Using RC oscillator or external clock option			0.1 VDD

Note: * The RC oscillator and external clock options require a Schmidt trigger configuration for OSC1.

No. 5117-10/39

LC6529N, LC6529F, LC6529L

	Parameter	Symbol			Conditions			min	typ	max	Unit
[Current drain]
	RC oscillator	IDD OP1	VDD: Figure 2, 850 kHz (typ)						0.8	2.0	mA
		IDD OP2	VDD: Figure 2, 400 kHz (typ)						0.4	1.0
		IDD OP3	VDD: Figure 3, 4 MHz, 1/3 frequency divider						1.6	4.0
		IDD OP4	VDD: Figure 3, 4 MHz, 1/4 frequency divider						1.6	4.0
	Ceramic oscillator	IDD OP5	VDD: Figure 3, 2 MHz, 1/3 frequency divider						1.3	3.0	mA
		IDD OP6	VDD: Figure 3, 2 MHz, 1/4 frequency divider						1.3	3.0
		IDD OP7	VDD: Figure 3, 800 kHz						1.1	2.6
		IDD OP8	VDD: Figure 3, 400 kHz						0.9	2.4
			VDD: 200 to 667 kHz, 1/1 frequency divider,
		IDD OP9	600 to 2000 kHz, 1/3 frequency divider,						1.0	2.5
	External clock		800 to 2667 kHz, 1/4 frequency divider								mA
			VDD: 200 to 1444 kHz, 1/1 frequency divider,
		IDD OP10	600 to 4330 kHz, 1/3 frequency divider,						1.6	4.2
			800 to 4330 kHz, 1/4 frequency divider
		IDD st1	VDD: With output N-channel transistor off and						0.05	10
			port level = VDD, VDD = 6 V
	Standby operation										µA
		IDD st2	VDD: With output N-channel transistor off and						0.025	5
			port level = VDD, VDD = 3 V
[Oscillator characteristics] (RC oscillator)
			OSC1, OSC2: Figure 2, Cext = 220 pF ± 5%,					309	400	577
			Rext = 12.0 kΩ ± 1%
	Oscillator frequency	fMOSC									kHz
			OSC1, OSC2: Figure 2, Cext = 220 pF ± 5%,					660	850	1229
			Rext = 4.7 kΩ ± 1%, VDD = 4 to 6 V
[Oscillator characteristics] (Ceramic oscillator)
			OSC1, OSC2: Figure 3, fO = 400 kHz					384	400	416
	Oscillator frequency	fCFOSC*	OSC1, OSC2: Figure 3, fO = 800 kHz					768	800	832	kHz
			OSC1, OSC2: Figure 3, fO = 2 MHz					1920	2000	2080
			OSC1, OSC2: Figure 3, fO = 4 MHz					3840	4000	4160
			Figure 4, fO = 400 kHz							10
	Oscillator stabilization interval	tCFS	Figure 4, f = 800 kHz, f			= 2 MHz, f	= 4 MHz,				ms
					O	O	O			10
			1/3, 1/4 frequency divider
[Pull-up resistors]
			Pull-up (PU) resistor configuration for port A or D:
		RPP1	With output N-channel transistor off and VIN = VSS,					30	70	130
	I/O ports		VDD = 5 V
			Pull-up (PU) resistor configuration for port C:								kΩ
		RPP2	With output N-channel transistor off and VIN = VSS,					1.0	2.3	3.9
			VDD = 5 V
	Reset port	Ru						200	500	725
				RES:	VIN = VSS, VDD = 5 V
External reset characteristic:		tRST							See
Reset time									Figure 6.
Pin capacitance		CP	f = 1 MHz, VIN = VSS for pins other than one							10	pF
			being measured

Note: * fCFOSC is the allowable oscillator frequency.

Comparator Characteristics for Comparator Option at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V

Parameter	Symbol	Conditions	min	typ	max	Unit
Reference input voltage range	VRFIN	VREF0 and VREF1	VSS + 0.3		VDD – 1.5	V
Inphase input voltage range	VCMIN	CMP0 to CMP3	VSS		VDD – 1.5	V
Offset voltage	VOFF	VCMIN = VSS to VDD – 1.5 V		±50	±300	mV
Response speed	TRS1	Figure 5: VDD = 4 to 6 V		1.0	5.0	µs
	TRS2	Figure 5		1.0	200
Input high level current	IIH1	VREF0 and VREF1			1.0	µA
	IIH2	CMP0 to CMP3: Without feedback resistor option			1.0
Input low level current	IIL1	VREF0 and VREF1	–1.0			µA
	IIL2	CMP0 to CMP3: Without feedback resistor option	–1.0
Feedback resistor	RCMFB	CMP0 to CMP3: With feedback resistor option		460		kΩ

No. 5117-11/39

LC6529N, LC6529F, LC6529L

Table 1 Guaranteed Constants for Ceramic Oscillators

	Oscillator type		Standard type					Chip type
		Manufacturer	Oscillator	C1	C2	Rd	Manufacturer	Oscillator	C1	C2
	[External capacitor]
	4-MHz ceramic	Murata	CS A4.00MG	33 pF ± 10%	33 pF ± 10%	—	Murata	CS AC4.00MGC	33 pF ± 10%	33 pF ± 10%
	oscillator	Kyocera	KBR-4.0MSA	33 pF ± 10%	33 pF ± 10%	—	—	—	—	—
	2-MHz ceramic	Murata	CS A2.00MG	33 pF ± 10%	33 pF ± 10%	—	Murata	CS AC2.00MGC	33 pF ± 10%	33 pF ± 10%
	oscillator	Kyocera	KBR-2.0MSA	33 pF ± 10%	33 pF ± 10%	—	—	—	—	—
	[Built-in capacitor]
	4-MHz ceramic	Murata	CS A4.00MG	—	—	—	Kyocera	KBR-4.0MWS	—	—
	oscillator	Kyocera	KBR-4.0MSA	—	—	—	—	—	—	—
	2-MHz ceramic	Murata	CS A2.00MG	—	—	—	Kyocera	KBR-2.0MWS	—	—
	oscillator
	800-kHz ceramic	Murata	CS B800J	100 pF ± 10%	100 pF ± 10%	3.3 kΩ	—	—	—	—
	oscillator	Kyocera	KBR-800F/Y	150 pF ± 10%	150 pF ± 10%	—	—	—	—	—
	400-kHz ceramic	Murata	CS B400P	220 pF ± 10%	220 pF ± 10%	3.3 kΩ	—	—	—	—
	oscillator	Kyocera	KBR-400BK/Y	330 pF ± 10%	330 pF ± 10%	—	—	—	—	—

Figure 1 External Clock Input Waveform

No. 5117-12/39