SANYO LC665316A, LC665312A, LC665308A, LC665306A, LC665304A Datasheet

CMOS LSI

No. 5485			LC665304A, 665306A, 665308A, 665312A, 665316A

Four-Bit Single-Chip Microcontrollers with 4, 6, 8, 12, and 16 KB of On-Chip ROM

Preliminary

Overview

The LC665304A, LC665306A, LC665308A, LC665312A, and LC665316A are 4-bit CMOS microcontrollers that integrate on a single chip all the functions required in a system controller, including ROM, RAM, I/O ports, a serial interface, 16-value comparator inputs, timers, interrupt functions, and an optional sub-oscillator circuit. These microcontrollers are available in a 48-pin package.

Features and Functions

•On-chip ROM capacitiy of 4, 6, 8, 12, and 16 kilobytes, and an on-chip RAM capacity of 512 × 4 bits.

•Fully supports the LC66000 Series common instruction set (128 instructions).

•I/O ports: 42 pins

•A sub-oscillator circuit can be used (option)

This circuit allows power dissipation to be reduced by operating at lower speeds.

•8-bit serial interface: two circuits (can be connected in cascade to form a 16-bit interface)

•Instruction cycle time: 0.95 to 10 µs (at 3 to 5.5 V)

•Powerful timer functions and prescalers

—Time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer.

—Time limit timer, event counter, PWM output, and square wave output using an 8-bit timer.

—Time base function using a 12-bit prescaler.

•Powerful interrupt system with 8 interrupt factors and 8 interrupt vector locations.

—External interrupts: 3 factors/3 vector locations

—Internal interrupts: 5 factors/5 vector locations

•Flexible I/O functions

16-value comparator inputs, 20-mA drive outputs, inverter circuits, pull-up and open-drain circuits selectable as options.

•Optional runaway detection function (watchdog timer)

•8-bit I/O functions

•Power saving functions using halt and hold modes.

•Packages: DIP48S, QIP48E (QFP48E)

•Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850-TB662YXX2

LC66E5316(on-chip EPROM microcontroller)

Package Dimensions

unit: mm

3149-DIP48S
[LC665304A/665306A/665308A/665312A/665316A]
48			25		0.25
				15.24	13.8
1			24		5.1max
	46.0			4.25
0.48	1.05	1.78	2.53	0.51min	3.8
			SANYO: DIP48S

unit: mm

3156-QFP48E

[LC665304A/665306A/665308A/665312A/665316A]

				17.2
				14.0	1.6
			1.5	1.0	1.5
	1.6		36		25
		1.5	37		24
17.2	14.0
		1.0
		1.5	48		13
			1		12
				0.35
	3.0max
			0.8	15.6

0.15

0.1

2.70

(STAND OFF)

SANYO: QFP48E

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

22897HA (OT) No. 5485-1/26

LC665304A, 665306A, 665308A, 665312A, 665316A

Series Organization

	Type No.	No. of	ROM capacity	RAM	Package		Features
		pins		capacity
	LC66304A/306A/308A	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E
							Normal versions
	LC66404A/406A/408A	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E
							4.0 to 6.0 V/0.92 µs
	LC66506B/508B/512B/516B	64	6 K/8 K/12 K/16 KB	512 W	DIP64S	QFP64A
	LC66354A/356A/358A	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E
							Low-voltage versions
	LC66354S/356S/358S	42	4 K/6 K/8 KB	512 W		QFP44M
							2.2 to 5.5 V/3.92 µs
	LC66556A/558A/562A/566A	64	6 K/8 K/12 K/16 KB	512 W	DIP64S	QFP64E
	LC66354B/356B/358B	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E	Low-voltage high-speed versions
	LC66556B/558B/562B/566B	64	6 K/8 K/12 K/16 KB	512 W	DIP64S	QFP64E	3.0 to 5.5 V/0.92 µs
	LC66354C/356C/358C	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E	2.5 to 5.5 V/0.92 µs
	LC662104A/06A/08A	30	4 K/6 K/8 KB	384 W	DIP30SD	MFP30S	On-chip DTMF generator versions
	LC662304A/06A/08A/12A/16A	42	4 K/6 K/8 K/12 K/16 KB	512 W	DIP42S	QFP48E
							3.0 to 5.5 V/0.95 µs
	LC662508A/12A/16A	64	8 K/12 K/16 KB	512 W	DIP64S	QFP64E
	LC665304A/06A/08A/12A/16A	48	4 K/6 K/8 K/12 K/16 KB	512 W	DIP48S	QFP48E	Dual oscillator support
							3.0 to 5.5 V/0.95 µs
	LC66E308	42	EPROM 8 KB	512 W	DIC42S	QFC48
					with window	with window
	LC66P308	42	OTPROM 8 KB	512 W	DIP42S	QFP48E
	LC66E408	42	EPROM 8 KB	512 W	DIC42S	QFC48	Window and OTP evaluation versions
					with window	with window
							4.5 to 5.5 V/0.92 µs
	LC66P408	42	OTPROM 8 KB	512 W	DIP42S	QFP48E
	LC66E516	64	EPROM 16 KB	512 W	DIC64S	QFC64
					with window	with window
	LC66P516	64	OTPROM 16 KB	512 W	DIP64S	QFP64E
	LC66E2108*	30	EPROM 8 KB	384 W
	LC66E2316	42	EPROM 16 KB	512 W	DIC42S	QFC48
					with window	with window
							Window evaluation versions
					DIC64S	QFC64
	LC66E2516	64	EPROM 16 KB	512 W			4.5 to 5.5 V/0.92 µs
					with window	with window
	LC66E5316	52/48	EPROM 16 KB	512 W	DIC52S	QFC48
					with window	with window
	LC66P2108*	30	OTPROM 8 KB	384 W	DIP30SD	MFP30S
	LC66P2316*	42	OTPROM 16 KB	512 W	DIP42S	QFP48E	OTP
	LC66P2516	64	OTPROM 16 KB	512 W	DIP64S	QFP64E	4.0 to 5.5 V/0.95 µs
	LC66P5316	48	OTPROM 16 KB	512 W	DIP48S	QFP48E
	Note: * Under development

No. 5485-2/26

LC665304A, 665306A, 665308A, 665312A, 665316A

Pin Assignments

							DIP48S
P20/SI0									P13
						1		48
P21/SO0									P12
						2		47
P22/SCK0						3		46	P11
P23/INT0									P10
						4		45
									P03
P30/INT1						5		44
P31/POUT0									P02
						6		43
P32/POUT1									P01
						7		42
			VSS						P00
						8		41
	OSC1					9	LC665304A	40	PD3/AN4/INV4O
	OSC2					10	5306A	39	PD2/AN3/INV4I
		VDD							PD1/AN2/INV3O
						11	5308A	38
			RES			12	5312A	37	PD0/AN1/INV3I
PE0/XT1									PC3/INV2O
						13	5316A	36
PE1/XT2									PC2/INV2I
						14		35
	TEST								PC1
						15		34
P33/HOLD									PC0
						16		33
P40/INV0I									P83
						17		32
P41/INV0O									P82
						18		31
P42/INV1I									P81/DS1
						19		30
P43/INV1O									P80/DS0
						20		29
			P50						P63/PIN1
						21		28
			P51						P62/SCK1
						22		27
			P52						P61/SO1
						23		26
P53/INT2									P60/SI1
						24		25

									QFP48E
					P01	P00	PD3/AN4/INV4O	PD2/AN3/INV4I	PD1/AN2/INV3O	PD0/AN1/INV3I	PC3/INV2O	PC2/INV2I	PC1 PC0 P83 P82
					36 35 34 33 32 31 30 29 28 27 26 25
		P02			37								24	P81/DS1
		P03			38								23	P80/DS0
		P10			39								22	P63/PIN1
		P11			40								21
									LC665304A					P62/SCK1
		P12			41						5306A		20	P61/SO1
		P13			42						5308A		19	P60/SI1
P20/S10					43						5312A		18	P53/INT2
P21/SO0					44						5316A		17	P52
					45								16	P51
P22/SCK0
P23/INT0					46								15	P50
					47								14	P43/INV1O
P30/INT1
P31/POUT0					48	2	3	4	5	6	7	8	13	P42/INV1I
					1								9 10 11 12

P32/POUT1	V	OSC1 OSC2	V	RES	PE0/XT1 PE1/XT2 TEST P33/HOLD P40/INV0I P41/INV0O
	SS		DD

Top view

We recommend the use of reflow soldering techniques to solder-mount QFP packages.

Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).

No. 5485-3/26

LC665304A, 665306A, 665308A, 665312A, 665316A

System Block Diagram

RAM STACK

ROM

RES

(512W)

4K/6K/8K/12K/16KB

TEST

C

Z

SYSTEM

FLAG

OSC1

CONTROL

OSC2

SP

E

D D

D D

E

A

ALU

PC

M

P P

P P

HOLD

R

H L

X Y

XT1					POUT0
XT2
					SI0
AN1 to 4	PRESCALER	MPX	TIMER0	SERIAL I/O 0	SO0
	ADC				SCK0
					INT0

PE

MPX

INT1, INT2

	PD	INTERRUPT	MPX			SI1
		CONTROL		TIMER1	SERIAL I/O 1	SO1
						SCK1
	PC					PIN1, POUT1

							INVxO	INVxI
P0	P1	P2	P3	P4	P5	P6	P8	(x=0 to 4)
							DS1	DS0

Differences between the LC6653XX Series and the LC663XX Series

	Item	LC6630X Series			LC6635XB Series			LC6653XX Series
		(Including the LC66599 evaluation chip)
	System differences	65536 cycles			16384 cycles			16384 cycles
	• Hardware wait time (number of
		About 64 ms at 4 MHz (Tcyc = 1 µs)			About 16 ms at 4 MHz (Tcyc = 1 µs)			About 16 ms at 4 MHz (Tcyc = 1 µs)
	cycles) when hold mode is cleared
	• Value of timer 0 after a reset
	(Including the value after hold mode	Set to FF0.			Set to FFC.			Set to FFC.
	is cleared)
	• Inverter array	None (Tools are handled with			None			Yes
		external devices.)
	• Buffer array (data shaper circuit)	None (Tools are handled with			None			Yes
		external devices.)
	• Sub-oscillator	None			None			Yes (option)
	• Three-value inputs/comparator	Yes			Yes			Only a 16-value comparator
	inputs
	• Three-state output from P31	None			None			Yes
	and P32
	• Using P0 to clear halt mode	In 4-bit groups			In 4-bit groups			Can be specified for each bit.
		None for INT3, INT4, and INT5.
	• External extended interrupts	(Tools are handled with external			None for INT3, INT4, and INT5.			None for INT3, INT4, and INT5.
		devices.)
		Shared with INT2						Shared with INT2
	• Other P53 functions	(Tools are handled with external			Shared with INT2
								(The logic is inverted.)
		devices.)
								• 3.0 to 5.5 V/0.95 to 10 µs
	Differences in main characteristics	• LC66304A/306A/308A			• 3.0 to 5.5 V/0.92 to 10 µs			(When the main oscillator is
		4.0 to 6.0 V/0.92 t 10 µs			• LC6635XA			operating)
	• Operating power-supply voltage
		• LC66E308/P308			2.2 to 5.5 V/3.92 to 10 µs			• 3.0 to 5.5 V/25 to 127 µs
	and operating speed (cycle time)
		4.5 to 5.5 V/0.92 to 10 µs			3.0 to 5.5 V/1.96 to 10 µs			(When the sub-oscillator is
								operating)
	• Pull-up resistors	P0, P1, P4, and P5: about 3 to 10 k			P0, P1, P4, and P5: about 3 to 10 k			P0, P1, P4, and P5: about 100 k
		• P2 to P6 and PC: 15-V handling			• P2 to P6 and PC: 15-V handling			All ports: normal voltage handling
	• Port voltage handling	• P0, P1, PD, PE: Normal voltage			• P0, P1, PD, PE: Normal voltage
								(7-V handling provided)
		handling			handling

For other differences and details, see the data sheets for the individual products.

No. 5485-4/26

LC665304A, 665306A, 665308A, 665312A, 665316A

Pin Function Overview

Pin

I/O

Overview

Output driver type

Options

State after a

Standby mode

reset

operation

P00

I/O ports P00 to P03

Hold mode:

• Pull-up MOS or

Output off

• Input or output in 4-bit or 1-bit units

• Pch: Pull-up MOS type

P01

Nch OD output

High or low

I/O

• P00 to P03 support the halt mode

• Nch: Intermediate sink current

P02

• Output level on

(option)

control function (This function can be

type

Halt mode:

P03

reset

specified in bit units.)

Output

retained

P10

• Pull-up MOS or

Hold mode:

• Pch: Pull-up MOS type

Output off

P11

I/O ports P10 to P13

Nch OD output

High or low

I/O

• Nch: Intermediate sink current

P12

Input or output in 4-bit or 1-bit units

• Output level on

(option)

type

Halt mode:

P13

reset

Output

retained

I/O ports P20 to P23

• Input or output in 4-bit or 1-bit units

Hold mode:

• P20 is also used as the serial input SI0

pin.

• Pch: CMOS type

Output off

P20/SI0

• P21 is also used as the serial output

• Nch: Intermediate sink current

P21/SO0

SO0 pin.

CMOS or Nch OD

I/O

type

H

P22/SCK0

• P22 is also used as the serial clock

output

• Nch: +7-V handling when OD

P23/INT0

SCK0 pin.

option selected

Halt mode:

• P23 is also used as the INT0 interrupt

Output

request pin, and also as the timer 0

retained

event counting and pulse width

measurement input.

I/O ports P30 to P32

Hold mode:

• Input or output in 3-bit or 1-bit units

Output off

• P30 is also used as the INT1 interrupt

• Pch: CMOS type

request.

P30/INT1

• Nch: Intermediate sink current

• P31 is also used for the square wave

CMOS or Nch OD

P31/POUT0

I/O

type

H

output from timer 0.

output

P32/POUT1

• Nch: +7-V handling when OD

• P32 is also used for the square wave

option selected

Halt mode:

and PWM output from timer 1.

Output

• P31 and P32 also support 3-state

retained

outputs.

Hold mode control input

• Hold mode is set up by the HOLD

instruction when

HOLD

is low.

• In hold mode, the CPU is restarted by

setting

HOLD

to the high level.

• This pin can be used as input port P33

P33/HOLD

I

along with P30 to P32.

pin is at the low

• When the P33/HOLD

level, the CPU will not be reset by a

low level on the

RES

pin. Therefore,

applications must not set P33/HOLD

low when power is first applied.

Hold mode:

I/O ports P40 to P43

Port output

• Input or output in 4-bit or 1-bit units

• Pch: Pull-up MOS type

• Pull-up MOS or

off, inverter

P40/INV0I

• Input or output in 8-bit units when used

output off

• CMOS type when the inverter

Nch OD output

High or low

P41/INV0O

in conjunction with P50 to P53.

I/O

circuit option is selected

• Output level on

or inverter

P42/INV1I

• Can be used for output of 8-bit ROM

Halt mode:

• Nch: Intermediate sink current

reset

I/O (option)

P43/INV1O

data when used in conjunction with

Port output

type

• Inverter circuit

P50 to P53.

retained,

• Dedicated inverter circuit (option)

inverter

output

continues

Continued on next page.

No. 5485-5/26

LC665304A, 665306A, 665308A, 665312A, 665316A

	Pin	I/O			Overview	Output driver type	Options	State after a	Standby mode
								reset	operation
			I/O ports P50 to P53
			• Input or output in 4-bit or 1-bit units						Hold mode:
	P50		• Input or output in 8-bit units when used				• Pull-up MOS or		Output off
				in conjunction with P40 to P43.		• Pch: Pull-up MOS type
	P51						Nch OD output	High or low
		I/O	• Can be used for output of 8-bit ROM			• Nch: Intermediate sink current
	P52						• Output level on	(option)
				data when used in conjunction with		type
	P53/INT2						reset		Halt mode:
				P40 to P43.
									Output
			• P53 is also used as the INT2 interrupt
									retained
				request.
			I/O ports P60 to P63
			• Input or output in 4-bit or 1-bit units						Hold mode:
			• P60 is also used as the serial input SI1			• Pch: MOS type
									Output off
	P60/SI1			pin.		• Nch: Intermediate sink current
							• CMOS or Nch OD
	P61/SO1		• P61 is also used as the serial output			type
		I/O					output	H
	P62/SCK1			SO1 pin.		• Nch: +7-V handling when OD
	P63/PIN1		• P62 is also used as the serial clock			option selected (P61 and P63			Halt mode:
				SCK1	pin.	only)			Output
			• P63 is also used for the event count						retained
				input to timer 1.
									Hold mode:
									Port output
			Dedicated output ports P80 to P83				• CMOS or Pch OD		off, buffer
									output off
							output
			• Output in 4-bit or 1-bit units
	P80/DS0						• Output level at
			• The contents of the output latch are			• Pch: CMOS type		High or low
	P81/DS1						reset
		O		input using input instructions.		• Nch: Intermediate sink current		Buffered I/O
	P82						• Buffer circuit		Halt mode:
			• P80 is a buffer input or a zero-cross			type		(option)
	P83						• Zero-cross
									Port output
				buffer input and P81 is a buffer input
							detector buffer
									retained,
				(options).
							circuit
									buffer output
									continues
									with the
									buffer
									resistor off.
									Hold mode:
									Port output
									off, inverter
	PC0		I/O ports PC0 to PC3			• Pch: CMOS type	• CMOS or Nch OD		output off
	PC1
		I/O	• Output in 4-bit or 1-bit units			• Nch: Intermediate sink current	output	H
	PC2/INV2I								Halt mode:
			• Dedicated inverter circuits (option)			type	• Inverter circuit
	PC3/INV2O								Port output
									retained,
									inverter
									output
									continues.
	PD0/AN1/
	INV3I					• Inverter circuits can be			Inverter:
	PD1/AN2/		Dedicated input ports PD0 to PD3					Normal	• Hold mode:
						selected as options.
	INV3O		• Can be switched in software to function					input or	Output off
		I				• Pch: CMOS type	Inverter circuit
	PD2/AN3			as 16-value analog inputs.				inverter I/O	• Halt mode:
						• Nch: Intermediate sink current
	INV4I		• Dedicated inverter circuits (option)					(option)	Output
						type
	PD3/AN4/								continues
	INV4O
									Sub-
									oscillator:
									Hold mode:
									Oscillator
	PE0/XT1	I	Dedicated input ports and sub-oscillator				Sub-oscillator/port	Selected as	stopped
	PE1/XT2		connections				PE selection	an option
									Halt mode:
									Oscillator
									operates

Continued on next page.

No. 5485-6/26

LC665304A, 665306A, 665308A, 665312A, 665316A

Continued from preceding page.

Pin

I/O

Overview

Output driver type

Options

State after a

Standby mode

reset

operation

Hold mode:

OSC1

I

System clock oscillator connections

Oscillator

Ceramic oscillator

stopped

When an external clock is used, leave

Selected as

or external clock

OSC2

O

OSC2 open and connect the clock signal

an option

selection

Halt mode:

to OSC1.

Oscillator

operates

System reset input

When the P33/HOLD pin is at the high

RES

I

level, a low level input to the RES pin will

initialize the CPU.

CPU test pin

TEST

I

This pin must be connected to VSS

during normal operation.

VDD

Power supply pins

VSS

Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD.

CMOS output: Complementary output.

OD output: Open-drain output.

User Options

1. Port 0, 1, 4, 5, and 8 output level at reset option

The output levels at reset for I/O ports 0, 1, 4, 5, and 8, in independent 4-bit groups, can be selected from the following two options.

	Option	Conditions and notes
1.	Output high at reset	The four bits of ports 0, 1, 4, 5, or 8 are set in a group
2.	Output low at reset	The four bits of ports 0, 1, 4, 5, or 8 are set in a group

2. Oscillator circuit options

• Main clock

	Option		Circuit	Conditions and notes
1.	External clock	OSC1		The input has Schmitt characteristics
		C1	OSC1
2.	Ceramic oscillator	Ceramic oscillator
		C2	OSC2

Note: There is no RC oscillator option.

• Sub-clock

Option

Circuit

Conditions and notes

			DSB
	1. Ports PE0 and PE1
			Input data
		C1	XT1
	2 Sub-oscillator	Crystal oscillator
	(crystal oscillator)
		C2	XT2

No. 5485-7/26

LC665304A, 665306A, 665308A, 665312A, 665316A

3.Watchdog timer option

A runaway detection function (watchdog timer) can be selected as an option.

4.Port output type options

•The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be selected individually from the following two options.

Option

Circuit

Conditions and notes

1. Open-drain output

Output data

The port P2, P3, P5, and P6 inputs have Schmitt

Input data

characteristics.

DSB

Output data

The port P2, P3, P5, and P6 inputs have Schmitt

2. Output with built-in pull-up

characteristics.

The CMOS outputs (ports P2, P3, P6, and PC)

resistor

Input data

and the pull-up MOS outputs (P0, P1, P4, and

P5) are distinguished by the drive capacity of the

p-channel transistor.

DSB

• One of the following two options can be selected for P8, in bit units.

Option

Circuit

Conditions and notes

1. Open-drain output

Output data

DSB

Output data

2. Output with built-in pulldown resistor

(CMOS output)

DSB

No. 5485-8/26