SANYO LC321664AT-80, LC321664AM-80, LC321664AJ-80 Datasheet

Ordering number : EN4795C

CMOS LSI

LC321664AJ, AM, AT-80

1 MEG (65536 words × 16 bits) DRAM

Fast Page Mode, Byte Write

Overview

The LC321664AJ, AM, AT is a CMOS dynamic RAM operating on a single 5 V power source and having a 65536-word × 16-bit configuration. Equipped with large capacity capabilities, high-speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment.

Address input utilizes a multiplexed address bus which permits it to be enclosed in compact plastic packages of SOJ 40-pin, SOP 40-pin and TSOP 44-pin. Refresh rates are within 4 ms with 256 row address (A0 to A7) selection and support RAS-only refresh, CAS-before-RAS refresh and hidden refresh settings.

There are functions such as page mode, read-modify- write, and byte-write.

Features

•65536-word × 16-bit configuration

•Single 5 V ±10% power supply

•All input and output (I/O) TTL compatible

•Supports fast page mode, read-modify-write, and bytewrite.

•Supports output caching control using early write and Output Enable (OE) control.

•4 ms refresh using 256 refresh cycles

•Supports RAS-only refresh, CAS-before-RAS refresh and hidden refresh.

•Packages

SOJ 40-pin	(400 mil) plastic package: LC321664AJ
SOP 40-pin	(525 mil) plastic package: LC321664AM

TSOP 44-pin (400 mil) plastic package: LC321664AT

•RAS access time/column address access time/CAS access time/ cycle time/power dissipation

Package Dimensions

unit: mm

3200-SOJ40

[LC321664AJ]

SANYO:SOJ40

unit : mm

3195-SOP40

[LC321664AM]

SANYO:SOP40

				Parameter			LC321664AJ, AM, AT-80
				access time			80 ns
	RAS
	Column address access time						45 ns
				access time			30 ns
		CAS
	Cycle time						135 ns
	Power dissipation					During operation	633 mW
	(max.)					During standby	5.5 mW (CMOS level)/11 mW (TTL level)

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN

32896HA (OT)/O3194TH/81094TH (OT) No. 4795-1/30

LC321664AJ, AM, AT-80

Package Dimensions

unit : mm

3207-TSOP44

[LC321664AT]

SANYO:TSOP44 (TYPE-II)

Pin Assignments

No. 4795-2/30

LC321664AJ, AM, AT-80

Block Diagram

Specifications

Absolute Maximum Ratings

	Parameter		Symbol	Ratings	Unit	Note
	Maximum supply voltage		VCC max	–1.0 to +7.0	V	1
	Input voltage		VIN	–1.0 to +7.0	V	1
	Output voltage		VOUT	–1.0 to +7.0	V	1
	Allowable power dissipation	LC321664AJ, AM	Pd max	800	mW	1
		LC321664AT		700
	Output short-circuit current		IOUT	50	mA	1
	Operating temperature range		Topr	0 to +70	°C	1
	Storage temperature range		Tstg	–55 to +150	°C	1

Note: 1) Stresses greater than the above listed maximum values may result in damage to the device.

DC Recommended Operating Ranges at Ta = 0 to +70°C

Parameter			Symbol	min	typ	max	Unit	Note
Power supply voltage			VCC	4.5	5.0	5.5	V	2
Input high level voltage			VIH	2.4		6.5	V	2
Input low level voltage (A0 to A7,			VIL	–1.0*		+0.8	V	2
RAS, CAS, UW, LW,	OE)
Input low level voltage			VIL	–0.5*		+0.8	V	2
(I/O1 to I/O16)

Note: 2) All voltages are referenced to VSS.

A bypass capacitor of about 0.1 µF should be connected between VCC and VSS of the device. * –2.0 V when pulse width is less than 20 ns

No. 4795-3/30

LC321664AJ, AM, AT-80

DC Electrical Characteristics at Ta = 0 to + 70°C, VCC = 5 V ± 10%

Parameter

Symbol

Conditions

min

max

Unit

Note

Operating current

address cycling:

3, 4,

ICC1

RAS,

CAS,

115

mA

(Average current during operation)

tRC = tRC min

5

Standby current

ICC2

= VIH

2

mA

RAS

=

CAS

= VIH:

RAS

cycling,

CAS

RAS-only refresh current

ICC3

115

mA

3, 5

tRC = tRC min

address cycling:

3, 4,

Fast page mode current

ICC4

RAS

= VIL,

CAS

70

mA

tPC = tPC min

5

Standby current

ICC5

1

mA

RAS

=

CAS

= VCC–0.2V

RAS,

CAS

cycling:

CAS-before-RAS refresh current

ICC6

115

mA

3

tRC = tRC min

Input leakage current

IIL

0V ≤ VIN ≤ 6.5V, pins other than

–10

+10

µA

measuring pin = 0V

Output leakage current

IOL

DOUT disable,

–10

+10

µA

0V ≤ VOUT ≤ 5.5V

Output high level voltage

VOH

IOUT = –2.5mA

2.4

V

Output low level voltage

VOL

IOUT = 2.1mA

0.4

V

Note: 3) All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is longer than shown here value becomes smaller.

Note: 4) ICC1 and ICC4 are dependent on output loads. Maximum values for ICC1 and ICC4 represent values with output open.

Note: 5) One address change can be performed while RAS = VIL (ICC1 and ICC3).

One address change can be performed during one tPC cycle (ICC4).

No. 4795-4/30

LC321664AJ, AM, AT-80

AC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5 V ± 10% (Note 6, 7, 8)

Parameter

Symbol

min

max

Unit

Note

Random read or

tRC

135

ns

write cycle time

Read-write/read-modify-write

tRWC

180

ns

cycle time

Fast page mode cycle time

tPC

55

ns

Fast page mode

tPRWC

Read-write/read-modify-

100

ns

write cycle time

tRAC

9, 14

RAS access time

80

ns

15

access time

tCAC

30

ns

9, 14

CAS

Column address access time

tAA

45

ns

9, 15

tCPA

50

ns

9

CAS

precharge access time

Output low-impedance

tCLZ

0

ns

9

time from CAS low

Output buffer turn-off delay time

tOFF

0

20

ns

10

Rise or fall time

tT

3

50

ns

precharge time

tRP

45

ns

RAS

tRAS

80

10000

ns

RAS

pulse width

pulse width for

RAS

tRASP

80

100000

ns

fast page mode only

hold time

tRSH

30

ns

RAS

tCSH

80

ns

CAS

hold time

pulse width

tCAS

30

10000

ns

CAS

to

delay time

tRCD

25

50

ns

14

RAS

CAS

to column address delay time

tRAD

17

35

ns

15

RAS

to

precharge time

tCRP

10

ns

CAS

RAS

tCP

10

ns

CAS

precharge time

Row address setup time

tASR

0

ns

Row address hold time

tRAH

12

ns

Column address setup time

tASC

0

ns

Column address hold time

tCAH

20

ns

Column address hold time

tAR

60

ns

referenced to RAS

Column address to

lead time

tRAL

45

ns

RAS

Read command setup time

tRCS

0

ns

Read command hold time

tRCH

0

ns

11

referenced to CAS

Read command hold time

tRRH

0

ns

11

referenced to RAS

Write command hold time

tWCH

15

ns

Write command hold time

tWCR

60

ns

referenced to RAS

Write command pulse width

tWP

15

ns

Continued on next page.

No. 4795-5/30

LC321664AJ, AM, AT-80

Continued from preceding page.

Parameter

Symbol

min

max

Unit

Note

Write command to

RAS

lead time

tRWL

20

ns

Write command to

lead time

tCWL

20

ns

CAS

Data input setup time

tDS

0

ns

12

Data input hold time

tDH

20

ns

12

Data input hold time

tDHR

60

ns

referenced to RAS

Refresh period

tREF

4

ms

Write command setup time

tWCS

0

ns

13

to

delay time

tCWD

50

ns

13

CAS

UW,

LW

to

delay time

tRWD

100

ns

13

RAS

UW,

LW

Column address to

UW,

LW

tAWD

65

ns

13

delay time

precharge to

delay

CAS

UW,

LW

tCPWD

70

ns

13

time (fast page mode cycle only)

setup time for

CAS

tCSR

10

ns

CAS-before-RAS refresh

hold time for

CAS

tCHR

15

ns

CAS-before-RAS refresh

RAS

precharge time to

tRPC

10

ns

CAS active time

precharge time for

CAS

tCPT

40

ns

CAS-before-RAS counter test

RAS

hold time referenced to OE

tROH

15

ns

tOEA

25

ns

9

OE

access time

delay time

tOED

15

ns

OE

to output buffer turn-off

OE

tOEZ

0

15

ns

10

delay time

tOEH

20

ns

OE

command hold time

Data input to

delay time

tDZC

0

ns

16

CAS

Data input to

OE

delay time

tDZO

0

ns

16

Masked write setup time

tMCS

0

ns

Masked write hold time

tMRH

0

ns

referenced to RAS

Masked write hold time

tMCH

0

ns

referenced to CAS

Input/Output Capacitance at Ta = 25°C, f = 1 MHz, VCC = 5 V ± 10%

Parameter

Symbol

min

max

Unit

Input capacitance

CIN

7

pF

(A0 to A7, RAS, CAS, UW, LW, OE)

I/O capacitance (I/O1 to I/O16)

CI/O

7

pF

No. 4795-6/30

LC321664AJ, AM, AT-80

Notes: 6) After the power is turned on, 200 µ s are required after the arrival of VCC stabilized current before memory is initialized and begins operation. In addition, before memory operation initializes, approximately 8 cycles worth of RAS dummy cycles are required. When the on-chip refresh counter is applied, approximately 8-cycles worth of CAS-before-RAS dummy cycles are required instead of the RAS dummy cycles.

7)Measured at tT = 5 ns.

8)When measuring input signal timing, VIH (min) and VIL (max) are used for reference points. In addition, rise and fall time are defined between VIH and VIL.

9)Measured using an equivalent of 50 pF and one standard TTL load.

10)tOFF (max) and tOEZ (max) are defined as the time until output voltage can no longer be measured when output switches to a high impedance condition.

11)Operation is guaranteed if either tRRH or tRCH are satisfied.

12)These parameters are measured from the falling edge of CAS for an early-write cycle, and from the falling edge of UW and LW for a read-write/read-modify-write cycle.

13)tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters for memory in that they specify the operating mode. If tWCS ≥ tWCS (min), the cycle switches to an early-write cycle and output pins switch to high impedance throughout the cycle. If tCWD ≥ tCWD (min), tRWD ≥ tRWD (min), tAWD ≥ tAWD (min) and tCPWD ≥ tCPWD (min), the cycle switches to a read-write/read-modify-write cycle and data outputs equal information in the selected cells. If neither of the above conditions are satisfied, output pins are in an undefined state.

14)tRCD (max) does not indicate a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRCD ≥ tRCD (max), access time is determined according to

tCAC.

15)tRAD (max) does not indicate a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRAD ≥ tRAD (max), access time is determined according to tAA.

16)Operation is guaranteed if either tDZC or tDZO are satisfied.

No. 4795-7/30

LC321664AJ, AM, AT-80

Timing Chart

Read Cycle

No. 4795-8/30

LC321664AJ, AM, AT-80

Early Write Cycle

No. 4795-9/30