SANYO LC662316A, LC662306A, LC662304A, LC662312A, LC662308A Datasheet

CMOS LSI

No. 5483			LC662304A, 662306A, 662308A, 662312A, 662316A

Four-Bit Single-Chip Microcontrollers with 4, 6, 8, 12, and 16 KB of On-Chip ROM

Preliminary

Overview

The LC662304A, LC662306A, LC662308A, LC662312A, and LC662316A are 4-bit CMOS microcontrollers that integrate on a single chip all the functions required in a special-purpose telephone controller, including ROM, RAM, I/O ports, a serial interface, a DTMF generator, timers, and interrupt functions. These microcontrollers are available in a 42-pin package.

Features and Functions

•On-chip ROM capacities of 4, 6, 8, 12, and 16 kilobytes, and an on-chip RAM capacity of 512 × 4 bits.

•Fully supports the LC66000 Series common instruction set (128 instructions).

•I/O ports: 36 pins

•DTMF generator

This microcontroller incorporates a circuit that can generate two sine wave outputs, DTMF output, or a melody output for software applications.

•8-bit serial interface: one circuit

•Instruction cycle time: 0.95 to 10 µs (at 3.0 to 5.5 V)

•Powerful timer functions and prescalers

—Time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer.

—Time limit timer, event counter, PWM output, and square wave output using an 8-bit timer.

—Time base function using a 12-bit prescaler.

•Powerful interrupt system with 10 interrupt factors and 7 interrupt vector locations.

—External interrupts: 3 factors/3 vector locations

—Internal interrupts: 4 factors/4 vector locations (Waveform output internal interrupts: 3 factors and 1 vector; shared with external expansion interrupts)

•Flexible I/O functions

Selectable options include 20-mA drive outputs, inverter circuits, pull-up and open drain circuits.

•Optional runaway detection function (watchdog timer)

•8-bit I/O functions

•Power saving functions using halt and hold modes.

•Packages: DIP42S, QIP48E (QFP48E)

•Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850-TB662YXX2

LC66E2316(on-chip EPROM microcontroller)

Package Dimensions

unit: mm

3025B-DIP42S
[LC662304A/662306A/662308A/662312A/662316A]
42			22
			15.24	13.8
					0.25
1			21
37.9
			4.25	5.1	max
			0.51 min	3.8
0.95	0.48	1.78	1.15
			SANYO: DIP42S

unit: mm

3156-QFP48E

[LC662304A/662306A/662308A/662312A/662316A]

				17.2
				14.0	1.6
			1.5	1.0	1.5
	1.6		36		25
		1.5	37		24
17.2	14.0
		1.0
		1.5	48		13
			1		12
				0.35
	3.0max
			0.8	15.6

0.15

0.1

2.70

(STAND OFF)

SANYO: QFP48E

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

22897HA (OT) No. 5483-1/25

LC662304A, 662306A, 662308A, 662312A, 662316A

Series Organization

	Type No.	No. of	ROM capacity	RAM	Package		Features
		pins		capacity
	LC66304A/306A/308A	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E
							Normal versions
	LC66404A/406A/408A	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E
							4.0 to 6.0 V/0.92 µs
	LC66506B/508B/512B/516B	64	6 K/8 K/12 K/16 KB	512 W	DIP64S	QFP64A
	LC66354A/356A/358A	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E
							Low-voltage versions
	LC66354S/356S/358S	42	4 K/6 K/8 KB	512 W		QFP44M
							2.2 to 5.5 V/3.92 µs
	LC66556A/558A/562A/566A	64	6 K/8 K/12 K/16 KB	512 W	DIP64S	QFP64E
	LC66354B/356B/358B	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E	Low-voltage high-speed versions
	LC66556B/558B/562B/566B	64	6 K/8 K/12 K/16 KB	512 W	DIP64S	QFP64E	3.0 to 5.5 V/0.92 µs
	LC66354C/356C/358C	42	4 K/6 K/8 KB	512 W	DIP42S	QFP48E	2.5 to 5.5 V/0.92 µs
	LC662104A/06A/08A	30	4 K/6 K/8 KB	384 W	DIP30SD	MFP30S	On-chip DTMF generator versions
	LC662304A/06A/08A/12A/16A	42	4 K/6 K/8 K/12 K/16 KB	512 W	DIP42S	QFP48E
							3.0 to 5.5 V/0.95 µs
	LC662508A/12A/16A	64	8 K/12 K/16 KB	512 W	DIP64S	QFP64E
	LC665304A/06A/08A/12A/16A	48	4 K/6 K/8 K/12 K/16 KB	512 W	DIP48S	QFP48E	Dual oscillator support
							3.0 to 5.5 V/0.95 µs
	LC66E308	42	EPROM 8 KB	512 W	DIC42S	QFC48
					with window	with window
	LC66P308	42	OTPROM 8 KB	512 W	DIP42S	QFP48E
	LC66E408	42	EPROM 8 KB	512 W	DIC42S	QFC48	Window and OTP evaluation versions
					with window	with window
							4.5 to 5.5 V/0.92 µs
	LC66P408	42	OTPROM 8 KB	512 W	DIP42S	QFP48E
	LC66E516	64	EPROM 16 KB	512 W	DIC64S	QFC64
					with window	with window
	LC66P516	64	OTPROM 16 KB	512 W	DIP64S	QFP64E
	LC66E2108*	30	EPROM 8 KB	384 W
	LC66E2316	42	EPROM 16 KB	512 W	DIC42S	QFC48
					with window	with window
							Window evaluation versions
					DIC64S	QFC64
	LC66E2516	64	EPROM 16 KB	512 W			4.5 to 5.5 V/0.92 µs
					with window	with window
	LC66E5316	52/48	EPROM 16 KB	512 W	DIC52S	QFC48
					with window	with window
	LC66P2108*	30	OTPROM 8 KB	384 W	DIP30SD	MFP30S
	LC66P2316*	42	OTPROM 16 KB	512 W	DIP42S	QFP48E	OTP
	LC66P2516	64	OTPROM 16 KB	512 W	DIP64S	QFP64E	4.0 to 5.5 V/0.95 µs
	LC66P5316	48	OTPROM 16 KB	512 W	DIP48S	QFP48E
	Note: * Under development

No. 5483-2/25

LC662304A, 662306A, 662308A, 662312A, 662316A

Pin Assignments

						DIP42S
P20/SI0								P13
					1		42
P21/SO0								P12
					2		41
P22/SCK0					3		40	P11
P23/INT0								P10
					4		39
P30/INT1					5		38	P03
P31/POUT0								P02
					6		37
P32/POUT1								P01
					7		36
			VSS					P00
					8	LC662304A	35
OSC1					9	2306A	34	PD3/INV30
OSC2								PD2/INV31
					10	2308A	33
			VDD			2312A		PD1/INV20
					11		32
			RES		12	2316A	31	PD0/INV21
			PE0					PC3
					13		30
			PE1					PC2
					14		29
	TEST							P63/PIN1
					15		28
								P62/DT
P33/HOLD					16		27
P40/INV01								P61
					17		26
P41/INV00								P60/ML
					18		25
P42/INV11								P53/INT2
					19		24
P43/INV10								P52
					20		23
			P50					P51
					21		22

QFP48E

P02

P01

P00

PD3/INV3O

PD2/INV3I

PD1/INV2O

NC

PD0/INV2I

PC3 PC2 P63/PIN

P62/DT

36 35 34 33 32 31 30 29 28 27 26 25

P03

37

24

P61

P10

38

23

P60/ML

P11

39

22

P53/INT2

P12

40

LC662304A

21

P52

P13

41

2306A

20

P51

NC

42

2308A

19

NC

NC

43

2312A

18

NC

P20/SI0

44

2316A

17

P50

P21/SO0

45

16

P43/INV1O

46

15

P42/INV1I

P22/SCK0

P23/INT0

47

14

P41/INV0O

48

13

P40/INV0I

P30/INT1

2

3

4

5

6

7

8

1

9 10 11 12

P31/POUT0

P32/POUT1

V

OSC1

OSC2

NC

V

RES

PE0 PE1 TEST

P33/HOLD

SS

DD

Top view

We recommend the use of reflow-soldering techniques to solder-mount QFP packages.

Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).

No. 5483-3/25

LC662304A, 662306A, 662308A, 662312A, 662316A

System Block Diagram

RES TEST OSC1 OSC2 HOLD

SYSTEM CONTROL

RAM STACK

ROM

(512W)

4K/6K/8K/12K/16KB

C

Z

FLAG

SP

E

D D

D D

E

A

ALU

PC

M

P P

P P

R

H L

X Y

ML						POUT0
	DTMF					SI0
		PRESCALER	MPX	TIMER0	SERIAL I/O 0
DT	GEN.					SO0
						SCK0
						INT0

PE	MPX						INT1, INT2
PD	INTERRUPT			MPX
	CONTROL					TIMER1
PC							PIN1, POUT1
							INVxO	INVxI
								(x=0 to 3)
	P0	P1	P2	P3	P4	P5	P6

Differences between the LC663XX Series and the LC6623XX Series

	Item	LC6630X Series			LC6635XB Series			LC6623XX Series
		(Including the LC66599 evaluation chip)
	System differences	65536 cycles			16384 cycles			16384 cycles
	• Hardware wait time (number of
		About 64 ms at 4 MHz (Tcyc = 1 µs)			About 16 ms at 4 MHz (Tcyc = 1 µs)			About 16 ms at 4 MHz (Tcyc = 1 µs)
	cycles) when hold mode is cleared
	• Value of timer 0 after a reset
	(Including the value after hold mode	Set to FF0.			Set to FFC.			Set to FFC.
	is cleared)
	• DTMF generator	None (Tools are handled with			None			Yes
		external devices.)
	• Inverter array	None (Tools are handled with			None			Yes
		external devices.)
	• SIO1	Yes			Yes			None
	• Three-value inputs/comparator	Yes			Yes			None
	inputs
	• Three-state output from P31	None			None			Yes
	and P32
	• Using P0 to clear halt mode	In 4-bit groups			In 4-bit groups			Can be specified for each bit.
		None for INT3, INT4, and INT5.						INT3, INT4, and INT5 can be used
	• External extended interrupts	(Tools are handled with external			None for INT3, INT4, and INT5.
								with the internal functions.
		devices.)
		Shared with	INT2
	• Other P53 functions	(Tools are handled with external			Shared with	INT2		Shared with INT2
		devices.)
	Differences in main characteristics	• LC66304A/306A/308A			• 3.0 to 5.5 V/0.92 to 10 µs
		4.0 to 6.0 V/0.92 t 10 µs			• LC6635XA
	• Operating power-supply voltage							3.0 to 5.5 V/0.95 to 10 µs
		• LC66E308/P308			2.2 to 5.5 V/3.92 to 10 µs
	and operating speed (cycle time)
		4.5 to 5.5 V/0.92 to 10 µs			3.0 to 5.5 V/1.96 to 10 µs
	• Pull-up resistors	P0, P1, P4, and P5: about 3 to 10 k			P0, P1, P4, and P5: about 3 to 10 k			P0, P1, P4, and P5: about 100 k
		• P2 to P6 and PC: 15-V handling			• P2 to P6 and PC: 15-V handling			P2, P3, P61, and P63: 12-V voltage
	• Port voltage handling	• P0, P1, PD, PE: Normal voltage			• P0, P1, PD, PE: Normal voltage			handling Others: normal voltage
		handling			handling			handling

No. 5483-4/25

LC662304A, 662306A, 662308A, 662312A, 662316A

Pin Function Overview

Pin

I/O

Overview

Output driver type

Options

State after a

Standby mode

reset

operation

P00

I/O ports P00 to P03

Hold mode:

• Pull-up MOS or

Output off

• Input or output in 4-bit or 1-bit units

• Pch: Pull-up MOS type

P01

Nch OD output

High or low

I/O

• P00 to P03 support the halt mode

• Nch: Intermediate sink current

P02

• Output level on

(option)

control function (This function can be

type

Halt mode:

P03

reset

specified in bit units.)

Output

retained

P10

• Pull-up MOS or

Hold mode:

• Pch: Pull-up MOS type

Output off

P11

I/O ports P10 to P13

Nch OD output

High or low

I/O

• Nch: Intermediate sink current

P12

Input or output in 4-bit or 1-bit units

• Output level on

(option)

type

Halt mode:

P13

reset

Output

retained

I/O ports P20 to P23

• Input or output in 4-bit or 1-bit units

Hold mode:

• P20 is also used as the serial input SI0

pin.

• Pch: CMOS type

Output off

P20/SI0

• P21 is also used as the serial output

• Nch: Intermediate sink current

P21/SO0

SO0 pin.

CMOS or Nch OD

I/O

type

H

P22/SCK0

• P22 is also used as the serial clock

output

• Nch: +12-V handling when

P23/INT0

SCK0 pin.

OD option selected

Halt mode:

• P23 is also used as the INT0 interrupt

Output

request pin, and also as the timer 0

retained

event counting and pulse width

measurement input.

I/O ports P30 to P32

Hold mode:

• Input or output in 3-bit or 1-bit units

Output off

• P30 is also used as the

INT1

interrupt

• Pch: CMOS type

request.

P30/INT1

• Nch: Intermediate sink current

• P31 is also used for the square wave

CMOS or Nch OD

P31/POUT0

I/O

type

H

output from timer 0.

output

P32/POUT1

• Nch: +12-V handling when

• P32 is also used for the square wave

OD option selected

Halt mode:

and PWM output from timer 1.

Output

• P31 and P32 also support 3-state

retained

outputs.

Hold mode control input

• Hold mode is set up by the HOLD

instruction when

HOLD

is low.

• In hold mode, the CPU is restarted by

setting

HOLD

to the high level.

• This pin can be used as input port P33

P33/HOLD

I

along with P30 to P32.

pin is at the low

• When the P33/HOLD

level, the CPU will not be reset by a

low level on the

RES

pin. Therefore,

applications must not set P33/HOLD

low when power is first applied.

Hold mode:

I/O ports P40 to P43

Port output

• Input or output in 4-bit or 1-bit units

• Pch: Pull-up MOS type

• Pull-up MOS or

off, inverter

P40/INV0I

• Input or output in 8-bit units when used

output off

• CMOS type when the inverter

Nch OD output

High or low

P41/INV0O

in conjunction with P50 to P53.

I/O

circuit option is selected

• Output level on

or inverter

P42/INV1I

• Can be used for output of 8-bit ROM

Halt mode:

• Nch: Intermediate sink current

reset

I/O (option)

P43/INV1O

data when used in conjunction with

Port output

type

• Inverter circuit

P50 to P53.

retained,

• Dedicated inverter circuit (option)

inverter

output

continues

Continued on next page.

No. 5483-5/25

LC662304A, 662306A, 662308A, 662312A, 662316A

Continued from preceding page.

Pin

I/O

Overview

Output driver type

Options

State after a

Standby mode

reset

operation

I/O ports P50 to P53

• Input or output in 4-bit or 1-bit units

Hold mode:

P50

• Input or output in 8-bit units when used

• Pull-up MOS or

Output off

in conjunction with P40 to P43.

• Pch: Pull-up MOS type

P51

Nch OD output

High or low

I/O

• Can be used for output of 8-bit ROM

• Nch: Intermediate sink current

P52

• Output level on

(option)

data when used in conjunction with

type

P53/INT2

reset

Halt mode:

P40 to P43.

Output

• P53 is also used as the INT2 interrupt

retained

request.

I/O ports P60 to P63

Hold mode:

• Input or output in 4-bit or 1-bit units

• Pch: CMOS type

Output off

P60/ML

• P60 is also used as the melody output

• Nch: Intermediate sink current

P61

I/O

ML pin.

type

CMOS or Nch OD

H

P62/DT

• P62 is also used as the tone output DT

• Nch: +12-V handling when

output

P63/PIN1

pin.

OD option selected (P61 and

Halt mode:

• P63 is also used for the event count

P63 only)

Output

input to timer 1.

retained

Hold mode:

Port output

• Pch: CMOS type

off

PC2

I/O ports PC2 to PC3

CMOS or Nch OD

I/O

• Nch: Intermediate sink current

H

PC3

Output in 2-bit or 1-bit units

output

type

Halt mode:

Port output

retained

Inverter

PD0/INV2I

• When the inverter circuit

Normal

• Hold

option is selected.

mode:

PD1/INV2O

Dedicated input ports PD0 to PD3

input or

I

• Pch: CMOS type

Inverter circuits

output off

PD2/INV3I

Dedicated inverter circuits (option)

inverter I/O

• Nch: Intermediate sink current

• Halt mode:

PD3/INV4O

(option)

type

output

continues

PE0

I

Dedicated input ports

Normal

PE1

input

Hold mode:

OSC1

I

System clock oscillator connections

Ceramic oscillator

Oscillator

When an external clock is used, leave

Option

stops

or external clock

OSC2

O

OSC2 open and connect the clock signal

selection

Halt mode:

selection

to OSC1.

Oscillator

continues

System reset input

I

When the P33/HOLD

pin is at the high

RES

level, a low level input to the RES pin will

initialize the CPU.

CPU test pin

TEST

I

This pin must be connected to VSS

during normal operation.

VDD

Power supply pins

VSS

Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD.

CMOS output: Complementary output.

OD output: Open-drain output.

No. 5483-6/25

LC662304A, 662306A, 662308A, 662312A, 662316A

User Options

1. Port 0, 1, 4, and 5 output level at reset option

The output levels at reset for I/O ports 0, 1, 4, and 5 in independent 4-bit groups, can be selected from the following two options.

	Option	Conditions and notes
1.	Output high at reset	The four bits of ports 0, 1, 4, or 5 are set in a group
2.	Output low at reset	The four bits of ports 0, 1, 4, or 5 are set in a group

2. Oscillator circuit options

• Main clock

Option

Circuit

Conditions and notes

1.	External clock	OSC1	The input has Schmitt characteristics
		C1	OSC1
2.	Ceramic oscillator	Ceramic oscillator

C2 OSC2

Note: There is no RC oscillator option.

3.Watchdog timer option

A runaway detection function (watchdog timer) can be selected as an option.

4.Port output type options

•The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be selected individually from the following two options.

Option

Circuit

Conditions and notes

1. Open-drain output

Output data

The port P2, P3, P5, and P6 inputs have Schmitt

Input data

characteristics.

DSB

Output data

The port P2, P3, P5, and P6 inputs have Schmitt

2. Output with built-in pull-up

characteristics.

The CMOS outputs (ports P2, P3, P6, and PC)

resistor

Input data

and the pull-up MOS outputs (P0, P1, P4, and

P5) are distinguished by the drive capacity of the

p-channel transistor.

DSB

No. 5483-7/25

LC662304A, 662306A, 662308A, 662312A, 662316A

5.Inverter array circuit option

One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PD0/PD1, and PD2/PD3. (PDs do not use option 1 because they are dedicated to input.)

Option	Circuit	Conditions and notes
	Output data
	Input data	When the open-drain output type is selected

		DSB
1. Normal port I/O circuit
			Output data
			When the built-in pull-up resistor output type is
			selected
			Input data
		DSB
	Input		Output data
			high
			Input data
		DSB	If this option is selected, The I/O circuit is
			disabled by the DSB signal.
2. Inverter I/O circuit			Also note that the open-drain port output type
			option and the high level at reset option must be
	Output		selected.
			Output data
			high
			Input data

DSB

No. 5483-8/25