Ordering number : EN2169C
CMOS LSI
LC7537, 7537AN, 7537NE
Electronic Volume Control System for
Audio Equipment
Overview
The LC7537N is an electronic control LSI capable of electronically controlling the volume, balance, loudness, fader, bass, and treble functions individually with fewer externally connected component parts.
Features
•Enables controlling the below-listed functions with 3- line serial data, including CE, DI, and CLK. Also, due to 0 V to 5 V swing of the serial data input voltage, permits the use of a general purpose microcomputer.
Volume : Separately controls the Lch and Rch volume levels across 81 positions over
the 0 dB to –79 dB (in 1 dB steps) range and –∞ , and consequently also serves
balance control purposes.
Loudness : By virtue of a center tap provided at the
–20 dB position of the volume controlling ladder resistors, permits loudness to be controlled with externally connected CR components.
Fader : By varying only the rear or front output level across 16 positions, provides fader functions (in 2 dB steps over the 0 dB to –20 dB range, and 5 dB steps over the –20 dB to –45 dB range, and at –∞ , for a total of 16 positions).
Bass/Treble : With CR components externally connected, forms an NF type tone control circuit (Baxandall type) to exercise control across 15 positions over both the bass and treble functions in 2 dB steps.
•By virtue of its CMOS structure, the LSI operates under a broad power supply voltage range from +4.5 V to +15 V, permitting the use of either a single or a dual ± power supply, whichever is preferred.
Package Dimensions
unit : mm
3025B-DIP42S
[LC7573N]
SANYO: DIP42S
unit : mm
3156-QFP48E
[LC7537NE]
SANYO: QIP48E
unit : mm
3052A-QFP48A
[LC7537AN]
SANYO: QIP48A
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
81096HA(OT)/31293JN/7018YT/6186KI,TS No. 2169-1/11
LC7537N, 7537AN, 7537NE
Pin Assignments
Equivalent Circuit Block Diagram
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V, VDD = ≥ VCC > VSS ≥ VEE
Item |
Symbol |
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Condition |
Rating |
Unit |
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Maximum supply voltage |
VDD – VEE max |
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VDD, VEE : VEE ≥ –8 V |
16 |
V |
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VCC max |
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VCC : VDD ≥ VCC |
VSS – 0.3 to VSS + 7 |
V |
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Input supply voltage |
VI1 |
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DI, CLK, CE |
VSS – 0.3 to VDD + 0.3 |
V |
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VI2 |
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INIT |
VSS – 0.3 to VDD + 0.3 |
V |
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Allowable power dissipation |
Pd max |
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Ta ≤ 85˚C, (LC7537N, 7537AN) |
200 |
mW |
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Ta ≤ 85˚C, (LC7537NE) |
300 |
mW |
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Operating temperature |
Topr |
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–40 to +85 |
˚C |
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Storage temperature |
Tstg *3 |
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–50 to +125 |
˚C |
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Allowable Operating Conditions at Ta = 25°C, VSS = 0 V, VDD = ≥ VCC > VSS ≥ VEE
Item |
Symbol |
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Condition |
Rating |
Unit |
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Supply voltage *1 |
VDD – VEE |
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VEE ≥ –7.5 V |
4.5 to 15 |
V |
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VCC |
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4.5 to 5.5 |
V |
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Input high–level voltage |
VIH1 *2 |
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DI, CLK, CE |
0.8 VCC to VCC |
V |
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VIH2 |
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INIT |
0.8 (VDD – VEE) + VEE to VDD |
V |
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Input low–level voltage |
VIL1 *2 |
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DI, CLK, CE |
VSS to 0.2 VCC |
V |
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VIL2 |
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INIT |
VEE to 0.2 (VDD – VEE) + VEE |
V |
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Input signal amplitude |
VIN |
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VEE to VDD |
VP-P |
Input pulse width |
tø W |
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1 min |
µs |
setup time |
tset up |
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1 min |
µs |
Hold time |
thold |
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1 min |
µs |
Operating frequency |
fopg |
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up to 330 |
kHz |
Note: 1. A1000 pF or larger capacitor should be added on between each individual power supply terminal and VSS.
2.When the microcomputer side control signals rise faster than VDD for the LC7537, a 2 kΩ or higher resistor should be inserted midway on each of the DI, CLK, and CE lines.
3.When mounting the QIP package on the board, do not dip the entire package in solder. Only the LC7537NE may be dipped directly in solder during mounting.
No. 2169-2/11
LC7537N, 7537AN, 7537NE
Electrical Characteristics at Ta = 25°C, VDD =+7.5 V, VEE =–7.5 V, VCC =+5 V
Item |
Symbol |
Condition |
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Rating |
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min |
typ |
max |
Unit |
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Total harmonic |
THD(1) |
VIN = 1 V, f = 1kHz, all flat overall |
|
0.005 |
0.01 |
% |
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Distortion |
THD(2) |
VIN = 1 V, f = 20 kHZ, all flat overall |
0.006 |
0.02 |
% |
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Crosstalk |
CT |
VIN = 1 V, f = 1 kHz, all flat, Rg = 1 kΩ |
60 |
95 |
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dB |
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Vomin(1) |
VIN = 1 V, f = 1 kHz, MAIN, VR = ∞ , FADER VR = ∞ |
80 |
90 |
dB |
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Maximum attenuation output |
Vomin(2) |
VIN = 1 V, f = 1 kHz, MAIN, VR = ∞ , VDD = 8 V, FADER VR = ∞ , |
70 |
80 |
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dB |
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VEE = VSS = 0 V, C between VSS and GND of L/R = 1000 µF |
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RVOL(1) |
5 dB-step |
12 |
20 |
28 |
kΩ |
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RVOL(2) |
1 dB-step |
12 |
20 |
28 |
kΩ |
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VR resistance voltage |
RBASS |
|
12 |
20 |
28 |
kΩ |
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RTREBLE |
|
12 |
20 |
28 |
kΩ |
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RFADER |
|
12 |
20 |
28 |
kΩ |
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Output noise |
VN(1) |
All flat overall (IHF-A) Rg = 1 kΩ |
|
2 |
10 |
µV |
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VN(2) |
Rg = 1 kΩ , VDD = 8 V, VEE = VSS = 0 V |
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2 |
10 |
µV |
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Current drain |
IDD |
VDD – VEE = 15 V |
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1 |
mA |
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ICC |
VCC = 5 V |
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1 |
mA |
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Pin Description ( |
) : LC7537AN, 7537NE |
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Pin No. |
Symbol |
Description of Functions |
Remarks |
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12(8) |
L.IN |
Main volume control block 5 dB-step attenuator input terminals. These pins should be |
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31(29) |
R.IN |
driven at a low impedance. |
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9(4) |
L.C1 |
Main volume control block 5 dB-step attenuator output terminals. Having been designed |
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to be open, the step positions will develop errors if at low acceptor impedances, so that as |
VR resistance : 20 kΩ |
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34(33) |
R.C1 |
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high load impedances as possible should be provided. |
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10(5) |
L.C2 |
Main volume control block 1 dB-step attenuator input terminals. Theses pins should be |
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33(32) |
R.C2 |
driven at alow impedance. |
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11(6) |
L.OUT |
Main volume control block 1 dB-step attenuator output terminals. Due to the step |
VR resistance : 20 kΩ |
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positions designed to be open, load impedances as high as possible should be provided to |
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32(31) |
R.OUT |
them, similar to those for the LC1 and RC1. |
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5(47) |
L.FIN |
Fader functions employing mode input terminals. These pins should be driven at a low |
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38(38) |
R.FIN |
impedance. |
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4(46) |
L.FOUT |
Fader block output terminals. These pins permit the front and rear sides to be faded out |
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3(45) |
L.ROUT |
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independently of each other. Attenuations exercised on Lch will be the same as on Rch. |
VR resistance : 20 kΩ |
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39(39) |
R.ROUT |
Due to the step positions designed to be open, acceptor impedances as high as possible |
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40(40) |
R.ROUT |
should be provided to them. |
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15(11) |
L.B1 |
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16(9) |
L.B2 |
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14(10) |
L.B3 |
Bass tone control block terminals. A total of 15 positions have been provided in 2 dB |
VR resistance : 20 kΩ |
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28(26) |
R.B1 |
steps |
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27(28) |
R.B2 |
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29(27) |
R.B3 |
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17(13) |
L.T1 |
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16(12) |
L.T2 |
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18(14) |
L.T3 |
Treble tone control block terminals. A total of 15 positions have been provided in 2 dB |
VR resistance : 20 kΩ |
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26(24) |
R.T1 |
steps. The VR resistance value is 20 kΩ . |
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27(25) |
R.T2 |
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25(23) |
R.T3 |
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7(1) |
LCT1 |
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6(48) |
LCT2 |
Loudness dedicated terminals. A high-frequency-range correcting C should be put |
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between CT1 and IN, and low-frequency-range correcting C between CT2 and L–VSS |
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36(36) |
RCT1 |
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(R–VSS). |
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37(37) |
RCT2 |
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Continued on next page.
No. 5190-3/10
LC7537N, 7537AN, 7537NE
Continued from preceding page.
Pin No. |
|
Symbol |
Description of Functions |
|
Remarks |
|
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8(2) |
L-VSS |
Main volume control block fader control common terminals. |
The impedance of pattern |
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connected to these pins should be as low as possible. Since L–VSS (R–VSS) and VSS |
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have not been connected inside the LSI, they should be connected together on the outside |
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in conformance with their individual specifications. Particular attenuation should be paid to |
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the capacitance assigned to the capacitors put between L–VSS (R–VSS) and VSS, which |
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will emerge as a residual resistive component when control is turned down for maximum |
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35(35) |
R-VSS |
attenuation. |
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Intra-IC latch resetting terminal |
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42(42) |
INIT |
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Control-setting data at the internal latch will be indeterminate when power has just been |
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switched on, so that by engaging the “L” level of this pin at power-on, the fader control |
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may be set at its –∞ position and muting behaviour is engaged (Note: VDD to VEE Level). |
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Chip enable terminal. When this pin is made “H” to “L”, data is written in the internal latch, |
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22(20) |
CE |
activating the various analog switches. When the “H” level is then restored, transfer of the |
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data will be enabled. |
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20(16) |
DI |
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Input terminals for serial data and clock that serve control purposes. |
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21(17) |
CLK |
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1(43) |
VDD |
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23(21) |
VCC |
These pins are connected to the relevant power supplies. Exercise caution against VCC |
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19(15) |
VSS |
rising earlier than VDD. |
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24(22) |
VEE |
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2(3, 7) |
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41(18, 30, |
NC |
No connect pins. Absolutely nothing should be connected here. |
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34, 41, 44) |
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(19) |
VDD(NC) |
VDD subterminal. Connected to VDD or left open. |
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LC7537AN and |
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LC7537NE only |
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No. 2169-4/11
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