SANYO LC7215FM, LC7215F, LC7215 Datasheet

Ordering number: EN 3584B

Silicon-gate CMOS LSI

LC7215, 7215F, 7215FM

MW/LW PLL Frequency Synthesizers

Overview

The LC7215, LC7215F and LC7215FM are phase-locked-loop frequency synthesizer LSIs that provide accurate reference frequencies over the MW and LW bands, making them ideally suited for AM tuners.

Features

. PLL frequency synthesizer LSIs for MW and LW bands.

. Reference frequencies of 1, 5, 9 and 10 kHz.

. On-chip transistor for the low-pass filter amplifier.

. Single output pin (CMOS output)

. Controller clock output pin.

. Time-base output pin.

. All devices can be used for double conversion demodulation.

. The LC7215F and 7215FM have expanded input frequency

ranges.
LC7215	0.5 to 13 MHz	: (DIP14)
LC7215F/FM	0.5 to 20 MHz	: (DIP14/MFP14S)

Package Dimensions

unit : mm

3003A-DIP14

SANYO : DIP14

unit : mm

3111-MFP14S

SANYO : MFP14S

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D2597HA(II)/1291JN/7200JN No.3584-1/7

LC7215, 7215F, 7215FM

Specifications

Absolute Maximum Ratings at Ta = 25°C, V SS = 0 V

Values in parentheses are for the LC7215F and LC7215FM.

Parameter	Symbol					Conditions	Ratings	Unit
Maximum supply voltage	VDD max	VDD					±0.3 to +6.5	V
Input voltage	VIN1	All input pins					±0.3 to VDD +0.3	V
	VIN2	CE, CL, DATA					(Note) ±0.3 to +6.5	V
Output current	IOUT	AOUT					0 to 5	mA
Output voltage	VOUT1	AOUT					±0.3 to +15	V
	VOUT2						±0.3 to +6.5	V
			SYC,		TB
	VOUT3	All output pins except VOUT1 and VOUT2					±0.3 to VDD +0.3	V
Allowable power	Pd max		Ta % 85°C				150	mW
dissipation
Operating temperature	Topr						±40 to +85	°C
Storage temperature	Tstg						±55 to +125	°C

Note: Voltage that is applied to the resistors when resistors totaling at least 10 kΩ are connected to a pin in series.

Allowable Operating Conditions at VSS = 0 V

Values in parentheses are for the LC7215F and LC7215FM.

	Parameter	Symbol					Conditions	min	typ	max	Unit
	Supply voltage	VDD1	VDD					(4.5)3.0		(5.5)5.5	V
		VDD2	VDD (Crystal OSC oscillation guaranteed)					3.0		5.5	V
	High-level input voltage	VIH	CE, CL, DATA					2.0		VDD1	V
	Low-level input voltage	VIL	CE, CL, DATA					0		0.5	V
	Output voltage	VOUT1	AOUT							13	V
		VOUT2
			SYC, TB							5.5	V
		fIN1	PIN: Sine wave, capacitive coupling VDD1,					(2.3)2.3		(20)13	MHz
	Input frequency			*S = 1
		fIN2	PIN: Sine wave, capacitive coupling VDD1,					0.5		2.5	MHz
				*S = 0
	Oscillation guaranteed	X'tal	XIN, XOUT: CI % 30 Ω					8.00	11.16	12.00	MHz
	crystal oscillator
		VIN1	PIN: Square wave, capacity connection VDD1,					100		1000	mVrms
	Input amplitude			*S = 1
		VIN2	PIN: Square wave, capacity connection VDD1,					100		1000	mVrms
				*S = 0
	Power supply	Ð		VDD, VSS: A capacitor of at least 1000 pF				1000			pF
							must be inserted.

No.3584-2/7

LC7215, 7215F, 7215FM

Electrical Characteristics within the allowable operating ranges

Values in parentheses are for LC7215F and LC7215FM.

Parameter	Symbol					Conditions	min	typ	max	Unit
	IIH1	XIN: VI = VDD							20	µA
High-level input currents	IIH2	PIN: VI = VDD							40	µA
	IIH3	CE, CL, DATA: VI = VDD							3.0	µA
	IIH4	AIN: VI = VDD						0.01	1.0	µA
	IIL1	XIN: VI = VSS							20	µA
Low-level input currents	IIL2	PIN: VI = VSS							40	µA
	IIL3	CE, CL, DATA: VI = VSS							3.0	µA
	IIL4	AIN: VI = VSS						0.01	1.0	µA
	VOH1	DOUT: IO = 1 mA					VDD			V
High-level output voltages							±1.0
	VOH2	PDOUT: IO = 0.5 mA					VDD			V
							±1.0
	VOL1	DOUT: IO = ±1 mA							1.0	V
Low-level output voltages	VOL2	PDOUT: IO = ±0.5 mA							1.0	V
	VOL4
		SYC, TB: IO = 0.5 mA							1.0	V
	VOL5	AOUT: IO = 1 mA							1.0	V
Output off-state leakage	IOFF1					VO = VDD			3.0	µA
			SYC,		TB:
currents	IOFF2	AOUT: VO = 13 V							5.0	µA
Tristate output High-level	IOFFH	PDOUT: VO = VDD						0.01	1.0	nA
off-state leakage current
Tristate output Low-level	IOFFL	PDOUT: VO = VSS						0.01	1.0	nA
off-state leakage current
High-level output voltage	VOH3	XOUT: IO = ±0.1 mA					VDD			V
							±1.0
Low-level output voltage	VOL3	XOUT: IO = 0.1 mA							1.0	V
		VDD: fIN1 = 13 MHz, *S = 1 (High speed)							10	mA
	IDD1			(Note 1)
				fIN1 = 20 MHz, *S = 1 (High speed)					(12)	mA
				(Note 1)
Supply current	IDD2	VDD: fIN1 = 2.5 MHz, *S = 0 (Low speed)							5	mA
				(Note 1)
		VDD: VDD = 5.5 V, *O = 0, P = 1 (Note 2)						1.2	2.0	mA
	IDD3				VDD = 4.5 V, *O = 0, P = 1 (Note 2)			0.7	1.5	mA
					VDD = 3.0 V, *O = 0, P = 1 (Note 2)			0.4	1.0	mA

* S, O and P are serial control bits.

Note 1. VIN1 = VIN2 = 100 mVms. The 11.16 MHz crystal is connected to XIN and XOUT. All other inputs are connected to VSS and all other outputs are open.

2.The 11.16 MHz crystal is connected to XIN and XOUT. All other inputs are connected to VDD and all other outputs are open. (Backup mode when PLL is halted.)

Pin Assignment

No.3584-3/7