SANYO LC72121 Datasheet

Ordering number : EN*5815A

CMOS IC

LC72121, 72121M, 72121V

PLL Frequency Synthesizers for Electronic Tuning

Preliminary

Overview

The LC72121 and the LC72121M and the LC72121V are high input sensitivity (20 mVrms at 130 MHz) PLL frequency synthesizers for 3 V systems. These ICs are serial data (CCB) compatible with the LC72131, and feature the improved input sensitivity and lower spurious radiation (provided by a redesigned ground system) required in high-performance AM/FM tuners.

Functions

•High-speed programmable divider

— FMIN: 10 to 160 MHz ... Pulse swallower technique

(With built-in divide-by-2 prescaler)

—AMIN: 2 to 40 MHz ... Pulse swallower technique

0.5to 10 MHz ... Direct division technique

•IF counter

—IFIN: 0.4 to 12 MHz ... For AM and FM IF counting

•Reference frequency

—One of 12 reference frequencies can be selected (using a 4.5 or 7.2 MHz crystal element)

1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, or 100 kHz

•Phase comparator

—Supports dead zone control.

—Built-in unlocked state detection circuit

—Built-in deadlock clear circuit

•An MOS transistor for an active low-pass filter is built in.

•I/O ports

—Output-only ports: 4 pins

—I/O ports: 2 pins

—Supports the output of a clock time base signal.

•Operating ranges

—Supply voltage: 2.7 to 3.6 V

—Operating temperature: – 40 to 85°C

•Package

—DIP22S, MFP24S, SSOP24

•Comparison with the LC72131/M

—Serial data compatible (CCB)

—Identical pin functions

—Two VSS pins were added.

—The DIP version is pin compatible (VSS pins were inserted as the DIP22S NC pins.)

—The MFP product provides a modified pin assignment (The MFP20 package was replaced by an MFP24 package, and extra VSS pins were added.)

—The SSOP24 is a newly developed package that has the same pin assignment as the MFP24S product.

•CCB is a trademark of SANYO ELECTRIC CO., LTD.

•CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

70398RM (OT) No. 5815-1/22

LC72121, 72121M, 72121V

Package Dimensions

unit: mm	unit: mm
3059-DIP22S	3112-MFP24S
[LC72121]		[LC72121M]

SANYO: DIP22S

SANYO: MFP24S

unit: mm

3175A-SSOP24

[LC72121V]

SANYO: SSOP24

Pin Assignments

Top view

No. 5815-2/22

LC72121, 72121M, 72121V

Block Diagram

No. 5815-3/22

LC72121, 72121M, 72121V

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSSd = VSSa = VSSX = 0 V

Parameter

Symbol

Conditions

Ratings

Unit

Maximum supply voltage

VDD max

VDD

–0.3 to +7.0

V

VIN1 max

CE, DI, CL, AIN

–0.3 to +7.0

V

Maximum input voltage

VIN2 max

XIN, FMIN, AMIN, IFIN

–0.3 to VDD +0.3

V

VIN3 max

–0.3 to +15

V

IO1,

IO2

VO1 max

DO

–0.3 to +7.0

V

Maximum output voltage

VO2 max

XOUT, PD

–0.3 to VDD +0.3

V

VO3 max

to

AOUT

–0.3 to +15

V

BO1

BO4,

IO1,

IO2,

Maximum output current

IO1 max

DO, AOUT

0 to +6.0

mA

IO2 max

BO1 to BO4, IO1, IO2

0 to +10.0

mA

DIP22S:

350

mW

(Ta ≤ 85°C)

Allowable power dissipation

Pd max

MFP24S:

200

mW

SSOP24:

150

mW

Operating temperature

Topr

–40 to +85

°C

Storage temperature

Tstg

–55 to +125

°C

Allowable Operating Ranges at Ta = – 40 to +85°C, VSSd = VSSa = VSSX = 0 V

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Supply voltage

VDD

VDD

2.7

3.6

V

Input high-level voltage

VIH1

CE, DI, CL

0.7 VDD

6.5

V

VIH2

IO1, IO2

0.7 VDD

13

V

Input low-level voltage

VIL

CE, DI, CL, IO1, IO2

0

0.3 VDD

V

Output voltage

VO1

DO

0

6.5

V

VO2

BO1 to BO4, IO1, IO2, AOUT

0

13

V

fIN1

XIN: VIN1

1

8

MHz

fIN2

FMIN: VIN2

10

160

MHz

Input frequency

fIN3

AMIN (SNS = 1): VIN3

2

40

MHz

fIN4

AMIN (SNS = 0): VIN4

0.5

10

MHz

fIN5

IFIN: VIN5

0.4

12

MHz

VIN1

XIN: fIN1

200

800

mVrms

VIN2-1

FMIN: f = 10 to 130 MHz

20

800

mVrms

VIN2-2

FMIN: f = 130 to 160 MHz

40

800

mVrms

Input amplitude

VIN3

AMIN (SNS = 1): fIN3

40

800

mVrms

VIN4

AMIN (SNS = 0): fIN4

40

800

mVrms

VIN5-1

IFIN: fIN5, IFS = 1

40

800

mVrms

VIN5-2

IFIN: fIN5, IFS = 0

70

800

mVrms

Guaranteed crystal oscillator frequency

Xtal

XIN, XOUT: *1

4.5

MHz

XIN, XOUT: *2

7.2

MHz

Notes: 1. Recommended value for CI for the crystal oscillator element: CI < 120Ω 2. Recommended value for CI for the crystal oscillator element: CI < 70Ω

Electrical Characteristics in the Allowable Operating Ranges

Parameter	Symbol		Conditions		Ratings		Unit
				min	typ	max
	Rf1	XIN			1		MΩ
Internal feedback resistance	Rf2	FMIN			500		kΩ
	Rf3	AMIN			500		kΩ
	Rf4	IFIN			250		kΩ
Internal pull-down resistance	Rpd1	FMIN		100	200	400	kΩ
	Rpd2	AMIN		100	200	400	kΩ
Hysteresis	VHIS	CE, DI, CL			0.1 VDD		V
Output high-level voltage	VOH1	PD: IO = –1 mA		VDD – 1.0			V

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No. 5815-4/22

LC72121, 72121M, 72121V

Continued from preceding page.

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

VOL1

PD: IO = 1 mA

1.0

V

VOL2

BO1 to BO4, IO1, IO2: IO = 1 mA

0.2

V

Output low-level voltage

BO1 to BO4, IO1, IO2: IO = 8 mA

1.6

V

VOL3

DO: IO = 5 mA

1.0

V

VOL4

AOUT: IO = 1 mA, AIN = 1.3 V

0.5

V

IIH1

CE, DI, CL: VI = 6.5 V

5.0

µA

IIH2

IO1, IO2: VI = 13 V

5.0

µA

Input high-level current

IIH3

XIN: VI = VDD

1.3

8

µA

IIH4

FMIN, AMIN: VI = VDD

2.5

15

µA

IIH5

IFIN: VI = VDD

5.0

30

µA

IIH6

AIN: VI = 6.5 V

200

nA

IIL1

CE, DI, CL: VI = 0 V

5.0

µA

IIL2

IO1, IO2: VI = 0 V

5.0

µA

Input low-level current

IIL3

XIN: VI = 0 V

1.3

8

µA

IIL4

FMIN, AMIN: VI = 0 V

2.5

15

µA

IIL5

IFIN: VI = 0 V

5.0

30

µA

IIL6

AIN: VI = 0 V

200

nA

IOFF1

Output off leakage current

BO1 to BO4, IO1, IO2, AOUT: VO = 13 V

5.0

µA

IOFF2

DO: VO = 6.5 V

5.0

µA

High-level 3-state off leakage current

IOFFH

PD: VO = VDD

0.01

200

nA

Low-level 3-state off leakage current

IOFFL

PD: VO = 0 V

0.01

200

nA

Input capacitance

CIN

FMIN

6

pF

IDD1

VDD: Xtal = 7.2 MHz, fIN2 = 130 MHz,

2.5

6

mA

VIN2 = 20 mVrms

Supply current

VDD: PLL block stopped (PLL inhibit mode)

IDD2

Crystal oscillator operating

0.3

mA

(crystal frequency: 7.2 MHz)

IDD3

VDD: PLL block stopped, crystal oscillator

10

µA

stopped

Pin Descriptions

	Pin	Pin No.		Type	Function	Equivalent circuit
	name	LC72121	LC72121M
			LC72121V
	XIN	1	1	Xtal	• Crystal oscillator element connections (4.5 or 7.2 MHz)
	XOUT	22	24
					• FMIN is selected when DVS in the serial data is set to 1.
					• Input frequency: 10 to 160 MHz
				Local	• The signal is passed through an internal divide-by-two prescaler and
	FMIN	16	17	oscillator	then input to the swallow counter.
				signal input	• The divisor can be set to a value in the range 272 to 65535. Since
					the internal divide-by-two prescaler is used, the actual divisor will be
					twice the set value.
					• AMIN is selected when DVS in the serial data is set to 0.
					• When SNS in the serial data is set to 1:
					• Input frequency: 2 to 40 MHz
					• The signal is input to the swallow counter directly.
				Local	• The divisor can be set to a value in the range 272 to 65535. The
	AMIN	15	16	oscillator	set value becomes the actual divisor.
				signal input	• When SNS in the serial data is set to 0:
					• Input frequency: 0.5 to 10 MHz
					• The signal is input to a 12-bit programmable divider directly.
					• The divisor can be set to a value in the range 4 to 4095. The set
					value becomes the actual divisor.
						Continued on next page.

No. 5815-5/22

LC72121, 72121M, 72121V

Continued from preceding page.

			Pin		Pin No.		Type	Function	Equivalent circuit
	name				LC72121	LC72121M
						LC72121V
			CE		3	3	Chip enable	• This pin must be set high to enable serial data input (DI) or serial
								data output (DO).
			DI		4	4	Input data	• Input for serial data transferred from the controller
			CL		5	5	Clock	• Clock used for data synchronization for serial data input (DI) and
								serial data output (DO).
			DO		6	6	Output data	• Output for serial data transmitted to the controller. The content of the
								data transmitted is determined by DOC0 through DOC2.
		VDD			17	18	Power supply	• LC72121 power supply (VDD 2.7 to 3.6 V)	——
								• The power on reset circuit operates when power is first applied.
	VSSX				2	2	Ground	• Ground for the crystal oscillator circuit	——
	VSSa				21	22	Ground	• Ground for the low-pass filter MOS transistor	——
	VSSd				14	15	Ground	• Ground for the LC72121 digital systems other than those that use	——
								VSSa or VSSX.
								• Shared function I/O ports
								• The pin function is determined by IOC1 and IOC2 in the serial data.
								When the data value 0: Input port
								When the data value 1: Output port
								• When specified to function as an input port:
								The input pin state is reported to the controller through the DO pin.
			IO1		11	11	I/O port	When the input state is low: The data will be 0:
								When the input state is high: The data will be 1:
			IO2		13	14
								• When specified to function as an output port:
								The output state is determined by IO1 and IO2 in the serial data.
								When the data value is 0: The output state will be the open circuit
								state.
								When the data value is 1: The output state will be a low level.
								• These pins are set to input mode after a power on reset.
								• Output-only ports
					7	7		• The output state is determined by BO1 through BO4 in the serial
	BO1
								data.
					8	8
	BO2						Output port	When the data value is 0: The output state will be the open circuit
					9	9		state.
	BO3
					10	10		When the data value is 1: The output state will be a low level.
	BO4
								• A time base signal (8 Hz) is output from BO1 when TBC in the serial
								data is set to 1.
								• PLL charge pump output
							Charge pump	A high level is output when the frequency of the local oscillator signal
			PD		18	19		divided by N is higher than the reference frequency, and a low level
							output
								is output when that frequency is lower. This pin goes to the high-
								impedance state when the frequencies match.
		AIN			19	20	Low-pass filter	• Connections for the MOS transistor used for the PLL active low-pass
	AOUT				20	21	amplifier	filter.
							transistor
								• The input frequency range is 0.4 to 12 MHz
		IFIN			12	13	IF counter	• The signal is passed directly to the IF counter.
								• The result is output, MSB first, through the DO pin.
								• Four measurement periods are supported: 4, 8, 32, and 64 ms.
			NC		—	12	NC pin	• No connection	——
						23

No. 5815-6/22

LC72121, 72121M, 72121V

Procedures for Input and Output of Serial Data

This product uses the CCB (Computer Control Bus), which is Sanyo’s audio product serial bus format, for data input and output. This product adopts an 8-bit address CCB format.

		I/O mode				Address					Function
			B0	B1	B2	B3	A0	A1	A2	A3
											• Control data input (serial data input) mode
	1	IN1 (82)	0	0	0	1	0	1	0	0	• 24 bits of data are input.
											• See the “DI Control Data (serial data input)” section for details on the
											content of the input data.
											• Control data input (serial data input) mode
	2	IN2 (92)	1	0	0	1	0	1	0	0	• 24 bits of data are input.
											• See the “DI Control Data (serial data input)” section for details on the
											content of the input data.
											• Data output (serial data output) mode
	3	OUT (A2)	0	1	0	1	0	1	0	0	• The number of bits output is equal to the number of clock cycles.
											• See the “DO Control Data (serial data output)” section for details on the
											content of the output data.
											I/O mode determined

CL: Normally high

CL: Normally low

No. 5815-7/22