Ordering number : ENN6498
CMOS IC
LC651432N/F/L, 651431N/F/L
Four-Bit CMOS Microcontrollers for
Small-Scale Control Applications
Overview
The LC651431N/F/L and LC651432N/F/L are the smallscale control models in Sanyo’s LC6500 Series of 4-bit microcontrollers and feature the same basic architecture and instruction set. These microcontrollers are appropriate for a wide range of applications, from applications that require only a limited number of circuits and controls and were previously implemented in standard logic to larger application such as audio equipment, including tape decks and disc players, office equipment, communication equipment, automotive equipment, and home appliances. Furthermore, since these products have equivalent basic functions (although there are differences in some functions and characteristics) and are pin compatible with the earlier LC6543N/F/L and LC6546N/F/L products, they can be used to replace those devices.
Features
•Fabricated in a CMOS process for low power operation (Standby mode can be controlled by CPU instructions.)
•ROM/RAM
LC651432N/F/L
—ROM: 2 K × 8 bits, RAM: 128 × 4 bits
LC651431N/F/L
—ROM: 1 K × 8 bits, RAM: 64 × 4 bits
•Instruction set: The 80-instruction set common to the whole LC6500 Series
•Wide operating supply voltage range of 2.2 to 6.0 V (L versions)
•Instruction cycle time of 0.92 µs (F versions)
•On-chip serial I/O function
•Highly flexible I/O ports Number of ports
—7 ports (Up to 25 pins) All ports
—Can be used for either input or output
—Voltage handling capability (input and output): 15 V maximum (For open-drain specification ports)
—Output current: 20 mA maximum sink current (Capable of directly driving an LED.)
I/O port options to match application requirements:
—Open-drain output and pull-up resistor specification: Can be specified for all ports in bit units.
—Output level at reset specification: Either a high or low level can be specified for ports C and D in 4-bit units each.
•Interrupts
Timer overflow vector interrupt (can also be tested by CPU instructions)
INT pin or serial I/O full/empty vector interrupt (can also be tested by CPU instructions)
•Stack levels: 4 levels (also used by interrupts)
•Timers: 8-bit programmable timer with 4-bit prescaler
•Clock oscillator options to match application requirements:
Oscillator circuit option:
—Two-pin RC oscillator (N and L versions) Two-pin ceramic oscillator or single external clock input pin (N, F, and L versions)
—Divider circuit option: No divider, built-in divide- by-three circuit, built-in divide-by-four circuit
(N and L versions)
•Continuous square-wave output with a period 64 times the cycle time.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40700RM (OT) No. 6498-1/39
LC651432N/F/L, 651431N/F/L
Package Dimensions
unit : mm |
unit : mm |
3196A-DIP30SD |
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3191A-SSOP30 |
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[LC651432N/F/L, 651431N/F/L] |
[LC651432N/F/L, 651431N/F/L] |
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27.0 |
30 |
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16 |
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30 |
16 |
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8.6 |
10.16 |
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5.6 |
7.6 |
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1 |
15 |
0.25 |
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0.5 |
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0.95 |
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1 |
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15 |
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3.95max |
(3.25) |
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0.15 |
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1.5max |
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9.75 |
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0.1(1.3) |
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3.0 |
0.51min |
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0.48 |
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(1.04) |
1.78 |
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0.22 |
0.65 |
(0.33) |
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SANYO: DIP30SD |
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SANYO: SSOP30 |
unit : mm
3216B-MFP30S |
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[LC651432N/F/L, 651431N/F/L] |
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30 |
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16 |
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7.9 |
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10.5 |
1 |
15.2 |
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15 |
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2.45max |
0.15 |
0.65 |
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(2.15) |
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0.4 |
1.0 |
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(0.6) |
0.1 |
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SANYO: MFP30S |
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No. 6498-2/39
LC651432N/F/L, 651431N/F/L
Function Overview
Parameter |
LC651432N/1431N |
LC651432F/1431F |
LC651432L/1431L |
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ROM |
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2048 × 8 bits (1432N/F/L) |
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1024 × 8 bits (1431N/F/L) |
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Memory |
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RAM |
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128 × 4 bits (1432N/F/L) |
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64 × 4 bits (1431N/F/L) |
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Instructions |
Instruction set |
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80 |
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Table reference |
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Provided |
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Interrupts |
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One external, one internal |
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Timers |
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8-bit timer with 4-bit prescaler |
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On-chip functions |
Stack levels |
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4 |
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HALT instruction based |
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Standby function |
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standby function |
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Provided |
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Number of ports |
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Up to 25 I/O pins |
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Serial ports |
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I/O in 4-bit or 8-bit units |
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I/O voltage |
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15 V max. |
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I/O ports |
Output current |
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10 mA typ. 20 mA max. |
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I/O circuit types |
Open drain (n channel) or built-in pull-up resistor output can be specified in 1-bit units. |
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Output level at reset |
High or low can be specified in port units (C and D ports only) |
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Square-wave output |
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Possible |
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Minimum cycle time |
2.77 µs (VDD ≥ 3 V) |
0.92 µs (VDD ≥ 3 V) |
3.84 µs (VDD ≥ 2.2 V) |
Characteristics |
Supply voltage |
3 to 6 V |
3 to 6 V |
2.2 to 6 V |
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Supply current |
1 mA typ. |
1.5 mA typ. |
1 mA typ. |
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RC oscillator (400 or 800 kHz typical) |
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RC oscillator (400 kHz typical) |
Oscillator |
Oscillator element |
Ceramic oscillator (400 kHz, |
Ceramic oscillator: 4 MHz |
Ceramic oscillator (400 kHz |
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800 kHz, 1 MHz, or 4 MHz) |
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or 4 MHz) |
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Divider circuit option |
1/1, 1/3, 1/4 |
1/1 |
1/1, 1/3, 1/4 |
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Other features |
Package |
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DIP30S-D, MFP30S, |
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SSOP30 |
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Note: Sanyo will be providing details on oscillator elements and oscillator circuit constants as recommended circuits are developed. Contact your Sanyo representative for more information.
No. 6498-3/39
LC651432N/F/L, 651431N/F/L
Differences between the LC651432N/LC651431N and the LC6543N/LC6546N
This table lists the points that require care when replacing the LC6543N/LC6546N with the LC651432N/LC651431N in completes end products.
Parameter |
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LC651432N/1431N |
LC6543N/46N |
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Pdmax(1) : DIP |
310 mW |
250 mW |
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Allowable power dissipation |
Pdmax(2) : MFP |
220 mW |
150 mW |
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Pdmax(3) : SSOP |
160 mW |
(This package not available.) |
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I/O voltage (PIO) |
VIO(3) added |
–0.3 to VDD + 0.3 |
–0.3 to +15 V (When open-drain output is used.) |
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–0.3 to VDD + 0.3 (When a pull-up resistor is used.) |
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High-level input voltage |
VIH(n) |
VIH(1) to VIH(7) |
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(Associated with the I/O voltage (PI0) |
VIH(1) to VIH(6) |
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changes mentioned above.) |
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High-level input current |
IIH(n) |
IIH(1) to IIH(3) |
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(Associated with the I/O voltage (PI0) |
IIH(1) to IIH(2) |
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changes mentioned above.) |
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fCFOSC |
Oscillator frequency precision: ±2% |
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Recommended oscillator circuit constants |
Oscillator frequency precision: ±4% |
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[OSC1, OSC2] |
(under evaluation) |
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Oscillator characteristics |
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800 kHz typical (VDD = 3 to 6 V) |
850 kHz typical (VDD = 4 to 6 V) |
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Ceramic oscillator |
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Circuit constant changes: Rext = 6.8 kΩ ±1% |
Circuit constant changes: Rext = 4.7 kΩ ±1% |
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Oscillator frequency |
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Sample-to-sample frequency variation: |
Sample-to-sample frequency variation: |
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2-pin RC oscillator |
fMOSC |
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595 to 1274 kHz |
619 to 1144 kHz |
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Oscillator frequency |
[OSC1, OSC2] |
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400 kHz typical (VDD = 3 to 6 V) |
400 kHz typical (VDD = 3 to 6 V) |
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Sample-to-sample frequency variation: |
Sample-to-sample frequency variation: |
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284 to 790 kHz |
305 to 546 kHz |
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Current drain |
IDD |
1 mA typ. |
2 mA typ. |
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Serial clock input clock cycle time |
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tCKCY(1)[SCK] |
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min. 2.0 µs |
min 3.0 µs |
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Package |
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DIP30S-D, MFP30S, |
DIP30S-D, MFP30S |
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SSOP30 added |
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Differences between the LC651432F/LC651431F and the LC6543F/LC6546F
This table lists the points that require care when replacing the LC6543F/LC6546F with the LC651432F/LC651431F in completes end products.
Parameter |
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LC651432F/1431F |
LC6543F/46F |
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Pdmax(1) : DIP |
310 mW |
250 mW |
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Allowable power dissipation |
Pdmax(2) : MFP |
220 mW |
150 mW |
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Pdmax(3) : SSOP |
160 mW |
(This package not available.) |
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Operating supply voltage |
VDD |
3 to 6 V |
4.5 to 6 V |
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I/O voltage (PI0) |
VIO(3) added |
–0.3 to VDD + 0.3 |
–0.3 to +15 V (When open-drain output is used.) |
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–0.3 to VDD + 0.3 (When a pull-up resistor is used.) |
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High-level input voltage |
VIH(n) |
VIH(1) to VIH(7) |
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(Associated with the I/O voltage (PI0) |
VIH(1) to VIH(6) |
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changes mentioned above.) |
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High-level input current |
IIH(n) |
IIH(1) to IIH(3) |
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(Associated with the I/O voltage (PI0) |
IIH(1) to IIH(2) |
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changes mentioned above.) |
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Low-level input voltage |
VIL(n) |
IIH(1) to IIH(3) |
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Specifications when VDD = 4 to 6 V |
Specifications when VDD = 4 to 6 V |
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Specifications added for VDD = 3 to 6 V |
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Oscillator characteristics |
fCFOSC |
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Ceramic oscillator |
Oscillator frequency precision: ±2% |
Oscillator frequency precision: ±4% |
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Oscillator frequency |
[OSC1, OSC2] |
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Current drain |
IDD |
1.5 mA typ. |
2.5 mA typ. |
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Serial clock input clock cycle time |
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tCKCY(1)[SCK] |
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min. 2.0 µs |
min 3.0 µs |
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Package |
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DIP30S-D, MFP30S, |
DIP30S-D, MFP30S |
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SSOP30 added |
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No. 6498-4/39
LC651432N/F/L, 651431N/F/L
Differences between the LC651432L/LC651431L and the LC6543L/LC6546L
This table lists the points that require care when replacing the LC6543L/LC6546L with the LC651432L/LC651431L in completes end products.
Parameter |
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LC651432L/1431L |
LC6543L/46L |
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Pdmax(1) : DIP |
310 mW |
250 mW |
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Allowable power dissipation |
Pdmax(2) : MFP |
220 mW |
150 mW |
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Pdmax(3) : SSOP |
160 mW |
(This package not available.) |
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I/O voltage (PI0) |
VIO(3) added |
–0.3 to VDD + 0.3 |
–0.3 to +15 V (When open-drain output is used.) |
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–0.3 to VDD + 0.3 (When a pull-up resistor is used.) |
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High-level input voltage |
VIH(n) |
VIH(1) to VIH(7) |
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(Associated with the I/O voltage (PI0) |
VIH(1) to VIH(6) |
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changes mentioned above.) |
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High-level input current |
IIH(n) |
IIH(1) to IIH(3) |
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(Associated with the I/O voltage (PI0) |
IIH(1) to IIH(2) |
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changes mentioned above.) |
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fCFOSC |
Oscillator frequency precision: ±2% |
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Oscillator characteristics |
Recommended oscillator circuit constants |
Oscillator frequency precision: ±4% |
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[OSC1, OSC2] |
(under evaluation) |
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Ceramic oscillator |
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Oscillator frequency |
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400 kHz typical (VDD = 2.2 to 6 V) |
400 kHz typical (VDD = 2.2 to 6 V) |
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2-pin RC oscillator |
fMOSC |
Circuit constant changes: Rext = 15 kΩ ±1% |
Circuit constant changes: Rext = 12 kΩ ±1% |
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Oscillator frequency |
[OSC1, OSC2] |
Sample-to-sample frequency variation: |
Sample-to-sample frequency variation: |
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200 to 790 kHz |
284 to 546 kHz |
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Current drain |
IDD |
1 mA typ. |
2 mA typ. |
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Package |
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DIP30S-D, MFP30S, |
DIP30S-D, MFP30S |
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SSOP30 added |
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Caution: Always test the end product thoroughly after changing the microcontroller used.
Pin Assignment
The same pin assignment is used for the DIP, MFP, and SSOP packages.
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PE2 |
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PE1 |
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PE0 |
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PD3 |
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PD2 |
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PD1 |
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PD0 |
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PC3 |
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PC2 |
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PC1 |
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PC0 |
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RES |
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VSS |
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TEST |
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OSC1 |
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30 |
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16 |
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LC651432N/F/L
LC651431N/F/L
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1 |
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15 |
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PE3 |
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VDD |
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PF0/SI |
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PF1/SO |
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PF2/SCK |
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PF3/INT |
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PG0 |
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PG1 |
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PG2 |
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PG3 |
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PA0 |
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PA1 |
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PA2 |
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PA3 |
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PI0/OSC2 |
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No. 6498-5/39
LC651432N/F/L, 651431N/F/L
Pin Nomenclature
OSC1, OSC2: Connections for capacitor and resistor oscillator components or a ceramic oscillator element.
PG0 to 3: |
Shared-function I/O port G0 to 3 |
PI0: |
Shared-function I/O port IO |
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RES: |
Reset |
TEST: Test |
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PA0 to 3: |
Shared-function I/O port A0 to 3 |
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Interrupt request |
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INT: |
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PC0 to 3: |
Shared-function I/O port C0 to 3 |
SI: |
Serial input |
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PD0 to 3: |
Shared-function I/O port D0 to 3 |
SO: |
Serial output |
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PE0 to 3: |
Shared-function I/O port E0 to 3 |
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Serial clock input or output pin |
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SCK: |
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PF0 to 3: Shared-function I/O port F0 to 3
Notes: 1. The SI, SO, SCK, and INT pins are shared-function pins also used as PF0 to 3.
2. OSC2 and PIO are a single pin set exclusively to one or the other function as a user option.
System Block Diagram
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PA0 to 3 |
Port A |
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PC0 to 3 |
Port C |
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PD0 to 3 |
Port D |
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PE0 to 3 |
Port E |
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PF0 to 3 |
Port F |
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PF1/SO |
Serial |
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shift |
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port F |
4/8 bits |
register |
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Lower digit |
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with |
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Serial |
Shared |
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4 bits |
shift |
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register |
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Higher |
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PF0/SI |
4/8 bits |
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PF2/SCK |
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PF3/INT |
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LC651432N/F/L, LC651431N/F/L |
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RAM |
PC |
ROM |
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F WR |
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buffer |
STACK 1 |
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STACK 2 |
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I/O |
DP |
STACK 3 |
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STACK 4 |
IR |
I.DEC |
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System bus |
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E |
AC |
STS |
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TM CTL |
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CF ZF EXTF TMF |
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ALU |
CSF ZSF |
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Serial |
Serial |
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INT |
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mode |
mode |
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register |
register |
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OSC |
OSC1 |
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OSC2* |
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I/O bus |
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RES |
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TEST |
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VDD |
Port G |
Port I |
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VSS |
PG0-3 |
PI0 |
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* |
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Note: * OSC2 and PIO are a single pin set exclusively to one or the other function as a user option.
RAM: |
Data memory |
ROM: |
Program memory |
F: |
Flags |
PC: |
Program counter |
WR: |
Working register |
INT: |
Interrupt control |
AC: |
Accumulator |
IR: |
Instruction register |
ALU: |
Arithmetic and logic unit |
I.DEC: |
Instruction decoder |
DP: |
Data pointer |
CF, CSF: |
Carry flag, carry save flag |
E: |
E register |
ZF, ZSF: |
Zero flag, zero save flag |
CTL: |
Control register |
EXTF: |
External interrupt request flag |
OSC: |
Oscillator circuit |
TMF: |
Internal interrupt request flag |
TM: |
Timer |
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STS: |
Status register |
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No. 6498-6/39
LC651432N/F/L, 651431N/F/L
Development Support
The following are available to support the development of LC651431 and LC651432 applications.
•User’s manual
“LC6543/46 User’s Manual” No. E71
•Development tool manual
See the “EVA86000 Development Tool Manual for 4-Bit Microcontrollers.”
•Software manual
“LC65/66 Series Software Manual”
•Development tools
Program development: EVA86000 System
Program evaluation: LC65E43 on-chip EPROM microcontroller
Pins Functions
Count |
Pin |
I/O |
Function |
Options |
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Reset state |
Handling when |
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unused |
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1 |
VDD |
— |
Power supply |
— |
— |
— |
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1 |
VSS |
— |
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1 |
OSC1 |
Input |
• Connection for the external system clock |
1. Single-pin external clock input |
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— |
— |
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RC or ceramic oscillator element |
2. 2-pin RC oscillator |
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• When a single pin is used for external clock |
3. 2-pin ceramic oscillator |
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input, the PI0/OSC2 pin is used as the PI0 |
4. Divider circuit option |
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I/O port. |
• No divider |
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• When a 2-pin RC oscillator or a 2-pin ceramic |
• Divide-by-three circuit |
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oscillator is used, the PI0/OSC2 pin is used as |
• Divide-by-four circuit |
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the OSC2 oscillator pin. |
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4 |
PA0 to PA3 |
I/O |
• I/O port A0 to 3 |
1. Open-drain output |
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• High-level |
The open-drain |
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Input in 4-bit units (IP instruction) |
2. Built-in pull-up resistor |
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output (with |
output option |
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Output in 4-bit units (OP instruction) |
Options 1 and 2 may be specified |
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the output n- |
must be |
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Test in single-bit units (BP and BNP instructions) |
in bit units. |
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channel |
selected and |
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Set/reset in single-bit units (SPB and RPB |
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transistor off) |
the pin |
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instructions) |
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connected to |
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• PA3 (Any one of PA0 to 3 can be selected) is |
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VSS. |
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used for standby mode control. |
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• Applications must assure that key bounce or |
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similar noise does not occur on PA3 (or PA0 to 3) |
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during a HALT instruction execution cycle. |
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4 |
PC0 to PC3 |
I/O |
• I/O port C0 to 3 |
1. Open-drain output |
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• High-level |
The same as |
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Provides the same functions as PA0 to 3. |
2. Built-in pull-up resistor |
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output |
that for PC0 to 3 |
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(See note.) |
3. High-level output at reset |
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• Low-level |
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• The output level at reset can be specified to be |
4. Low-level output at reset |
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output |
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either high or low. |
• Options 1 and 2 may be specified |
(Specified as a |
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Note: This port does not have the standby |
in bit units. |
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user option.) |
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mode control function. |
• Options 3 and 4 are specified in |
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a single 4-bit group |
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4 |
PD0 to PD3 |
I/O |
• I/O port D0 to 3 |
The same as those for PC0 to 3. |
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The same as |
The same as |
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Provides the same functions as PC0 to 3. |
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those for PC0 to 3. |
those for PC0 to 3. |
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Continued on next page.
No. 6498-7/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Count |
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Pin |
I/O |
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Function |
Options |
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Reset state |
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Handling when |
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unused |
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4 |
PE0 to PE3 |
I/O |
• I/O port E0 to 3 |
1. Open-drain output |
• High-level |
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The same as |
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Input in 4-bit units (IP instruction) |
2. Built-in pull-up resistor |
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output (with |
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that for |
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Output in 4-bit units (OP instruction) |
Options 1 and 2 may be specified |
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the output n- |
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PA0 to 3. |
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Set/reset in single-bit units (SPB and RPB |
in bit units. |
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channel |
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instructions) |
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transistor off) |
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Test in single-bit units (BP and BNP instructions) |
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• PE0 also has a continuous pulse (64Tcyc) |
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output function. |
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4 |
PF0/SI |
I/O |
• I/O port F0 to 3 |
The same as those for PE0 to 3. |
The same as |
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The same as |
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PF1/SO |
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Functions and options identical to PE0 to 3. |
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that for PE0 to 3. |
that for |
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(See note.) |
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The serial port |
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PA0 to 3. |
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PF2/SCK |
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PF3/INT |
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• PF0 to 3 have shared functions as the serial |
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is disabled and |
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interface pins and the |
INT |
input. |
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INT |
is the |
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Either function can be selected under program |
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interrupt source. |
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control. |
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SI ... Serial input port |
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SO ... Serial output port |
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SCK |
... Serial clock input or output |
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INT ... Interrupt request input |
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Serial input/output is switched between 4-bit |
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and 8-bit units under program control. |
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Note: This port does not have a continuous |
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pulse output function. |
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4 |
PG0 to PG3 |
I/O |
• I/O port G0 to 3 |
The same as those for PE0 to 3. |
The same as |
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The same as |
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Functions and options identical to PE0 to 3. |
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those for |
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that for |
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(See note.) |
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PE0 to 3. |
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PA0 to 3. |
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Note: This port does not have a continuous |
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pulse output function. |
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1 |
PI0/OSC2 |
I/O |
• I/O port IO |
The same as those for PG0 to 3. |
The same as |
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The same as |
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Output |
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Functions and options identical to PG0 to 3. |
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those for |
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that for |
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• However, consists of a single bit. |
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PG0 to 3. |
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PA0 to 3. |
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• When a 2-pins oscillator is used, this pin |
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functions as the OSC2 pin, and the I/O port |
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function is not available. |
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1 |
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Input |
• System reset input |
— |
— |
— |
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RES |
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• Connect an external capacitor to implement a |
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power-on reset. |
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• The reset start operation requires that a low |
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level be held for at least 4 clock cycles. |
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1 |
TEST |
Input |
• IC test pin |
— |
— |
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This pin must |
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This pin must be connected to VSS during |
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be connected to |
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normal operation. |
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VSS. |
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No. 6498-8/39
LC651432N/F/L, 651431N/F/L
Oscillator Circuit Options
Option |
Circuit |
Conditions and notes |
External clock |
OSC1 |
The PI0/OSC2 pin is used as the PI0 pin. |
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Cext |
OSC1 |
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Two-pin RC oscillator |
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The PI0/OSC2 pin is used as the OSC2 pin |
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and the port function is unavailable. |
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PI0/OSC |
Rext
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C1 |
OSC1 |
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Ceramic oscillator |
Ceramic oscillator |
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The PI0/OSC2 pin is used as the OSC2 pin |
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PI0/OSC |
and the port function is unavailable. |
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element |
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C2 R
Divider Circuit Options
Option
No divider circuit (1/1)
Divide-by-three circuit (1/3)
Divide-by-four circuit (1/4)
Circuit
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Oscillatorcircuit |
fOSC |
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Timing |
generator |
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Timing |
generator |
circuitOscillator |
fOSC |
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fOSC |
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3 |
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Divide-by-three |
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circuit |
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Timing |
generator |
circuitOscillator |
fOSC |
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fOSC |
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4 |
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Divide-by-four |
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circuit |
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Conditions and notes
•Applicable to all three oscillator options.
•The oscillator frequency or the external clock must not exceed 1444 kHz. (LC651431N and LC651432N)
•The oscillator frequency or the external clock must not exceed 4330 kHz. (LC651431F and LC651432F)
•The oscillator frequency or the external clock must not exceed 1040 kHz. (LC651431L and LC651432L)
•Only applicable to the external clock and the ceramic oscillator option.
•The oscillator frequency or the external clock must not exceed 4330 kHz.
•Only applicable to the external clock and the ceramic oscillator option.
•The oscillator frequency or the external clock must not exceed 4330 kHz.
Caution: The following table summarizes the oscillator and divider option combinations. Use care when selecting these options.
No. 6498-9/39
LC651432N/F/L, 651431N/F/L
Oscillator Divider Options for the LC651431N/LC651432N, LC651431F/LC651432F, and LC651431L/LC651432L
LC651432N, LC651431N
Oscillator type |
Frequency |
Divider option (cycle time) |
VDD range |
Notes |
Ceramic oscillator |
400 kHz |
1/1 (10 µs) |
3 to 6 V |
The divide-by-three and divide-by-four |
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circuits cannot be used. |
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800 kHz |
1/1 (5 µs) |
3 to 6 V |
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1/3 (15 µs) |
3 to 6 V |
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1/4 (20 µs) |
3 to 6 V |
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1 MHz |
1/1 (4 µs) |
3 to 6 V |
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1/3 (12 µs) |
3 to 6 V |
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1/4 (16 µs) |
3 to 6 V |
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4 MHz |
1/3 (3 µs) |
3 to 6 V |
The no-divider (1/1) option cannot be used. |
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1/4 (4 µs) |
3 to 6 V |
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Single-pin external clock input |
200 to 1444 kHz |
1/1 (20 to 2.77 µs) |
3 to 6 V |
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600 to 4330 kHz |
1/3 (20 to 2.77 µs) |
3 to 6 V |
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800 to 4330 kHz |
1/4 (20 to 3.70 µs) |
3 to 6 V |
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External clock provided by a |
As above |
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2-pin RC oscillator circuit |
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2-pin RC oscillator |
Using the no-divider (1/1) option and the |
3 to 6 V |
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recommended circuit constants. If the use of circuit |
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values other than the recommended values is unavoidable, the |
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frequencies, divider options, and VDD ranges specified for the |
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single-pin external clock input option must be strictly observed. |
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External clock used with the |
The IC cannot be driven by an external clock with this option. If external clock drive is required, select either the external |
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ceramic oscillator option |
clock option or the 2-pin RC oscillator option |
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LC651432F, LC651431F
Oscillator type |
Frequency |
Divider option (cycle time) |
VDD range |
Notes |
Ceramic oscillator |
4 MHz |
1/1 (1 µs) |
3 to 6 V |
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Single-pin external clock input |
200 to 4330 kHz |
1/1 (20 to 0.92 µs) |
3 to 6 V |
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External clock used with the |
The IC cannot be driven by an external clock with this option. If external clock drive is required, select the external clock |
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ceramic oscillator circuit |
option. |
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LC651432L, LC651431L
Oscillator type |
Frequency |
Divider option (cycle time) |
VDD range |
Notes |
Ceramic oscillator |
400 kHz |
1/1 (10 µs) |
2.2 to 6 V |
The divide-by-three and divide-by-four |
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circuits cannot be used. |
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4 MHz |
1/4 (4 µs) |
2.2 to 6 V |
The no-divider (1/1) and divide-by-three option |
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cannot be used. |
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Single-pin external clock input |
200 to 1040 kHz |
1/1 (20 to 3.84 µs) |
2.2 to 6 V |
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600 to 3120 kHz |
1/3 (20 to 3.84 µs) |
2.2 to 6 V |
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800 to 4160 kHz |
1/4 (20 to 3.84 µs) |
2.2 to 6 V |
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External clock provided by a |
As above |
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2-pin RC oscillator circuit |
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2-pin RC oscillator |
Using the no-divider (1/1) option and the |
2.2 to 6 V |
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recommended circuit constants. If the use of circuit |
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values other than the recommended values is unavoidable, the |
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frequencies, divider options, and VDD ranges specified for the |
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single-pin external clock input option must be strictly observed. |
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External clock used with the |
The IC cannot be driven by an external clock with this option. If external clock drive is required, select either the external |
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ceramic oscillator option |
clock option or the 2-pin RC oscillator option |
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No. 6498-10/39
LC651432N/F/L, 651431N/F/L
Port C and D Output Level at Reset Option
One of the following two options for the output level at reset may be chosen for the I/O ports C and D in 4-bit group units.
Option |
Conditions and notes |
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High-level output at reset |
Ports C and D in 4-bit units |
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Low-level output at reset |
Ports C and D in 4-bit units |
Port Output Circuit Type Option
One of the following two options for the circuit type can be selected for the I/O ports in bit units.
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Circuit |
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Applicable ports |
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Open-drain output |
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• Not applicable to the PI0/OSC2 pin if either |
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the 2-pin RC oscillator or the ceramic |
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Built-in pull-up resistor |
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oscillator is selected as the oscillator circuit. |
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output |
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No. 6498-11/39
LC651432N/F/L, 651431N/F/L
Specifications
LC651432N, 651431N
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter |
Symbol |
Conditions |
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Applicable pins |
Ratings |
Unit |
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Maximum supply voltage |
VDD max |
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VDD |
–0.3 to +7.0 |
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Voltages up to the |
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Output voltage |
VO |
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OSC2 |
voltage generated |
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are allowed. |
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V (1) |
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OSC1 *1 |
–0.3 to V +0.3 |
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Input voltage |
I |
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DD |
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VI(2) |
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TEST, RES |
–0.3 to VDD +0.3 |
V |
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VIO(1) |
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Ports with open-drain specifications |
–0.3 to +15 |
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I/O voltage |
VIO(2) |
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Ports with pull-up resistor |
–0.3 to VDD +0.3 |
V |
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specifications |
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VIO(3) |
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PI0 |
–0.3 to VDD +0.3 |
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Peak output current |
IOP |
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I/O ports |
–2 to +20 |
mA |
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IOA |
Per single pin, the average over a |
I/O ports |
–2 to +20 |
mA |
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100 ms period |
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The total current for PC0 to 3, |
PC0 to 3 |
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mA |
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ΣIOA(1) |
PD0 to 3 |
–15 to +100 |
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Average output current |
PD0 to 3, and PE0 to 3*2 |
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PE0 to 3 |
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The total current for PF0 to 3, |
PF0 to 3, PI0 |
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ΣIOA(2) |
PG0 to 3 |
–15 to +100 |
mA |
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PG0 to 3, PA0 to 3, and PI0*2 |
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PA0 to 3 |
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Pd max(1) |
Ta = –40 to +85°C (DIP package) |
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310 |
mW |
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Allowable power dissipation |
Pd max(2) |
Ta = –40 to +85°C (MFP package) |
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220 |
mW |
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Pd max(3) |
Ta = –40 to +85°C (SSOP package) |
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160 |
mW |
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Operating temperature |
Topr |
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–40 to +85 |
°C |
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Storage temperature |
Tstg |
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–55 to 125 |
°C |
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Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified)
Parameter |
Symbol |
Conditions |
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Applicable pins |
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Ratings |
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Unit |
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min |
typ |
max |
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Operating supply voltage |
VDD |
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VDD |
3.0 |
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6.0 |
V |
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Standby supply voltage |
VST |
RAM and register contents |
VDD |
1.8 |
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6.0 |
V |
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retained. *3 |
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VIH(1) |
With the n-channel output |
Ports with open-drain |
0.7 VDD |
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13.5 |
V |
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transistors off |
specifications (except for I0) |
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VIH(2) |
With the n-channel output |
Ports with pull-up resistor |
0.7 VDD |
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VDD |
V |
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transistors off |
specifications (except for I0) |
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VIH(3) |
With the n-channel output |
Port I0 |
0.7 VDD |
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VDD |
V |
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transistors off |
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High-level input voltage |
VIH(4) |
With the n-channel output |
The |
INT, |
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SCK, |
and SI pins |
0.8 VDD |
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13.5 |
V |
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transistors off |
with open-drain specifications |
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With the n-channel output |
The |
INT, |
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SCK, |
and SI pins |
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VIH(5) |
with pull-up resistor |
0.8 VDD |
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VDD |
V |
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transistors off |
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specifications |
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VIH(6) |
VDD = 1.8 to 6 V |
RES |
0.8 VDD |
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VDD |
V |
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VIH(7) |
External clock specifications |
OSC1 |
0.8 VDD |
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VDD |
V |
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Continued on next page.
No. 6498-12/39
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