Ordering number : EN5038
CMOS LSI
LC72136, 72136M
PLL Frequency Synthesizer
for Electronic Tuning
Overview
The LC72136 and LC72136M are PLL frequency synthesizers for use in radio/cassette players. They allow high-performance AM/FM tuners to be implemented easily.
Features
•High-speed programmable frequency divider
—FMIN: 10 to 160 MHz .....Pulse swallower
(divide-by-two prescaler built in)
—AMIN: 2 to 40 MHz .........Pulse swallower
0.5to 10 MHz ......Direct division
•IF counter
IFIN: 0.4 to 12 MHz ................For use as an AM/FM IF
counter
•Reference frequency
—Selectable from one of eight frequencies (crystal oscillator: 75 kHz)
1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz
•Phase comparator
—Supports dead zone control
—Built-in unlock detection circuit
—Built-in deadlock clear circuit
•Built-in MOS transistor for forming an active low-pass filter
•I/O ports
—Dedicated output ports: 6
—I/O ports: 2
—Supports clock time base output
•Serial Data I/O
—Supports CCB format communication with the system controller.
•Operating ranges
—Supply voltage: 4.5 to 5.5 V
—Operating temperature: –20 to +70°C
•Packages —DIP22S/MFP24S
•CCB is a trademark of SANYO ELECTRIC CO., LTD.
•CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.
Package Dimensions
unit: mm
3059-DIP22S
[LC72136]
SANYO: DIP22S
unit: mm
3112-MFP24S
[LC72136M]
SANYO: MFP24S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O3195HA (OT) No. 5038-1/23
LC72136, 72136M
Pin Assignments
No. 5038-2/23
LC72136, 72136M
Block Diagram
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter |
Symbol |
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Conditions |
Ratings |
Unit |
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Maximum supply voltage |
VDD max |
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VDD |
–0.3 to +7.0 |
V |
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VIN1 max |
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CE, CL, DI, AIN |
–0.3 to +7.0 |
V |
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Maximum input voltage |
VIN2 max |
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XIN, FMIN, AMIN, IFIN |
–0.3 to VDD + 0.3 |
V |
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VIN3 max |
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–0.3 to +15 |
V |
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IO1, |
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IO2 |
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VO1 max |
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DO |
–0.3 to +7.0 |
V |
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Maximum output voltage |
VO2 max |
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XOUT, PD |
–0.3 to VDD + 0.3 |
V |
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VO3 max |
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BO1 to BO5, |
BOF, |
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IO1, |
IO2, |
AOUT |
–0.3 to +15 |
V |
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IO1 max |
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BO1 |
0 to 3.0 |
mA |
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Maximum output current |
IO2 max |
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AOUT, DO |
0 to 6.0 |
mA |
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IO3 max |
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BO2 to BO5, BOF, |
IO1, |
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IO2 |
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0 to 10.0 |
mA |
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Allowable power dissipation |
Pd max |
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Ta ≤ 70°C: LC72136 (DIP22S) |
350 |
mW |
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Ta ≤ 70°C: LC72136M (MFP24S) |
200 |
mW |
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Operating temperature |
Topr |
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–20 to +70 |
°C |
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Storage temperature |
Tstg |
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–40 to +125 |
°C |
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No. 5038-3/23
LC72136, 72136M
Allowable Operating Ranges at Ta = –20 to +70°C, VSS = 0 V
Parameter |
Symbol |
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Conditions |
min |
typ |
max |
Unit |
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Supply voltage |
VDD |
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VDD |
4.5 |
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5.5 |
V |
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Input high-level voltage |
VIH1 |
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CE, CL, DI |
0.7 VDD |
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6.5 |
V |
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VIH2 |
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IO1, IO2 |
0.7 VDD |
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13 |
V |
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Input low-level voltage |
VIL |
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CE, CL, DI, |
IO1, |
IO2 |
0 |
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0.3 VDD |
V |
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Output voltage |
VO1 |
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DO |
0 |
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6.5 |
V |
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VO2 |
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BO1 to BO5, BOF, IO1, IO2, AOUT |
0 |
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13 |
V |
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fIN1 |
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XIN: VIN1 |
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75 |
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kHz |
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fIN2 |
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FMIN: VIN2 |
10 |
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160 |
MHz |
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Input frequency |
fIN3 |
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AMIN: VIN3, SNS = 1 |
2 |
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40 |
MHz |
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fIN4 |
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AMIN: VIN4, SNS = 0 |
0.5 |
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10 |
MHz |
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fIN5 |
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IFIN: VIN5 |
0.4 |
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12 |
MHz |
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VIN1 |
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XIN: fIN1 |
400 |
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1500 |
mVrms |
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VIN2-1 |
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FMIN: f = 10 to 130 MHz |
40 |
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1500 |
mVrms |
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VIN2-2 |
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FMIN: f = 130 to 160 MHz |
70 |
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1500 |
mVrms |
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Input amplitude |
VIN3 |
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AMIN: fIN3, SNS = 1 |
40 |
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1500 |
mVrms |
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VIN4 |
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AMIN: fIN4, SNS = 0 |
40 |
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1500 |
mVrms |
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VIN5-1 |
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IFIN: fIN5, IFS = 1 |
40 |
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1500 |
mVrms |
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VIN5-2 |
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IFIN: fIN6, IFS = 0 |
70 |
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1500 |
mVrms |
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Guaranteed crystal |
Xtal |
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XIN, XOUT* |
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75 |
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kHz |
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oscillator frequency |
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Note: * Crystal oscillator recommended CI value CI ≤ 35 kΩ (for a 75 kHz crystal)
The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and other items. Therefore we recommend consulting with the manufacturer of the crystal for evaluation and reliability.
The extremely high input impedance of the XIN pins means that applications must take the possibility of leakage into account.
Sample Oscillator Circuits
1. Seiko-Epson C-2-75kHz (CL = 11 pF)
2. Kyocera Corporation KF-38R5-09P0300 (CL = 9 pF)
No. 5038-4/23
LC72136, 72136M
Electrical Characteristics at Ta = –20 to +70°C, VSS = 0 V
Parameter |
Symbol |
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Conditions |
min |
typ |
max |
Unit |
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Rf1 |
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XIN |
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8.0 |
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MΩ |
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Internal feedback resistors |
Rf2 |
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FMIN |
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500 |
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kΩ |
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Rf3 |
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AMIN |
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500 |
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kΩ |
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Rf4 |
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IFIN |
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250 |
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kΩ |
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Internal pull-down resistors |
Rpd1 |
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FMIN |
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200 |
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kΩ |
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Rpd2 |
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AMIN |
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200 |
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kΩ |
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Internal output resistor |
Rd |
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XOUT |
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250 |
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kΩ |
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Hysteresis |
VHIS |
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CE, CL, DI, IO1, IO2 |
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0.1 VDD |
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V |
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Output high-level voltage |
VOH1 |
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PD: IO = –1 mA |
VDD – 1.0 |
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V |
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VOL1 |
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PD: IO = 1 mA |
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1.0 |
V |
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VOL2 |
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BO1: IO = 0.5 mA |
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0.5 |
V |
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BO1: IO = 1 mA |
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1.0 |
V |
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VOL3 |
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DO: IO = 1 mA |
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0.2 |
V |
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Output low-level voltage |
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DO: IO = 5 mA |
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1.0 |
V |
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BO2 to BO5, BOF, IO1, IO2: IO = 1 mA |
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0.2 |
V |
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VOL4 |
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BO2 to BO5, BOF, IO1, IO2: IO = 5 mA |
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1.0 |
V |
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BO2 to BO5, BOF, IO1, IO2: IO = 8 mA |
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1.6 |
V |
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VOL5 |
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AOUT: IO = 1 mA, AIN = 1.3 V |
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0.5 |
V |
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IIH1 |
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CE, CL, DI: VI = 6.5 V |
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5.0 |
µA |
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IIH2 |
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IO1, IO2: VI = 13 V |
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5.0 |
µA |
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Input high-level voltage |
IIH3 |
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XIN: VI = VDD |
0.3 |
0.6 |
1.4 |
µA |
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IIH4 |
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FMIN, AMIN: VI = VDD |
4.0 |
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22 |
µA |
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IIH5 |
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IFIN: VI = VDD |
8.0 |
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44 |
µA |
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IIH6 |
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AIN: VI = 6.5 V |
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200 |
nA |
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IIL1 |
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CE, CL, DI: VI = 0 V |
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5.0 |
µA |
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IIL2 |
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IO1, IO2: VI = 0 V |
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5.0 |
µA |
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Input low-level current |
IIL3 |
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XIN: VI = 0 V |
0.3 |
0.6 |
1.4 |
µA |
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IIL4 |
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FMIN, AMIN: VI = 0 V |
4.0 |
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µA |
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IIL5 |
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IFIN: VI = 0 V |
8.0 |
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44 |
µA |
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IIL6 |
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AIN: VI = 0 V |
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200 |
nA |
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Output off leakage current |
IOFF1 |
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BO1 to BO5, BOF, AOUT, IO1, IO2: VO = 13 V |
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5.0 |
µA |
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IOFF2 |
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DO: VO = 6.5 V |
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5.0 |
µA |
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High-level tree-state off |
IOFFH |
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PD: VO = VDD |
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0.01 |
200 |
nA |
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leakage current |
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Low-level tree-state off |
IOFFL |
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PD: VO = 0 V |
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0.01 |
200 |
nA |
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leakage current |
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Input capacitance |
CIN |
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FMIN |
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6 |
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pF |
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IDD1 |
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VDD: Xtal = 75 kHz, fIN2 = 130 MHz, VIN2 = 40 mVrms |
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10 |
mA |
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Current drain |
IDD2 |
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VDD: PLL block stopped (PLL inhibit), |
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0.1 |
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mA |
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Xtal oscillator operating (Xtal = 75 kHz) |
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IDD3 |
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VDD: PLL block stopped, Xtal oscillator stopped |
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10 |
µA |
No. 5038-5/23
LC72136, 72136M
Pin Functions
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Pin No. |
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Symbol |
(MFP pin numbers |
Type |
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Functions |
Circuit configuration |
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are in parentheses.) |
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XIN |
1 (1) |
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• |
Crystal oscillator connections (75 kHz) |
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Xtal |
• The extremely high input impedance of the XIN pins |
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XOUT |
22 (24) |
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means that applications must take the possibility of |
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leakage into account. |
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• |
FMIN is selected when the serial data input DVS bit is |
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set to 1. |
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• The input frequency range is from 10 to 160 MHz. |
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FMIN |
16 (17) |
Local oscillator |
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The input signal passes through the internal divide-by- |
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two prescaler and is input to the swallow counter. |
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• The divisor can be in the range 272 to 65535. However, |
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since the signal has passed through the divide-by-two |
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prescaler, the actual divisor is twice the set value. |
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AMIN is selected when the serial data input DVS bit is |
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set to 0. |
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When the serial data input SNS bit is set to 1: |
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— The input frequency range is 2 to 40 MHz. |
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— The signal is directly input to the swallow counter. |
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Local oscillator |
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— The divisor can be in the range 272 to 65535, and |
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AMIN |
15 (16) |
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the divisor used will be the value set. |
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signal input |
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When the serial data input SNS bit is set to 0: |
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— The input frequency range is 0.5 to 10 MHz. |
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— The signal is directly input to a 12-bit programmable |
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divider. |
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— The divisor can be in the range 4 to 4095, and the |
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divisor used will be the value set. |
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CE |
3 (4) |
Chip enable |
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Set this pin high when inputting (DI) or outputting (DO) |
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serial data. |
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CL |
5 (6) |
Clock |
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Used as the synchronization clock when inputting (DI) or |
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outputting (DO) serial data. |
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DI |
4 (5) |
Input data |
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Inputs serial data transferred from the controller to the |
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LC72136. |
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Outputs serial data transferred from the LC72136 to the |
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DO |
6 (7) |
Output data |
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controller. The data output is determined by the DOC0 to |
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DOC2 bits in the serial data. |
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VDD |
17 (18) |
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• The LC72136 power supply pin. (VDD = 4.5 to 5.5 V) |
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Power supply |
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The power on reset circuit operates when power is first |
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applied. |
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VSS |
21 (22) |
Ground |
• The LC72136 ground |
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Continued on next page.
No. 5038-6/23
LC72136, 72136M
Continued from preceding page.
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Pin No. |
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Symbol |
(MFP pin numbers |
Type |
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Functions |
Circuit configuration |
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are in parentheses.) |
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Dedicated outputs |
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• The output states are determined by the BO1 to BO5 |
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bits in the serial data. |
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Data: 0 = open, 1= low |
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BO1 |
7 (8) |
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• A time base signal (8 Hz) can be output from the BO1 |
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pin. (When the serial data TBC bit is set to 1.) |
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BO2 |
8 (9) |
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Care is required when using the BO1 pin, since it has a |
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BO3 |
9 (10) |
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higher on impedance that the other output ports (pins |
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BO4 |
10 (11) |
Output ports |
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BO2 to BO5). |
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The output state of the BOF pin is determined by the |
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BO5 |
14 (15) |
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serial data DVS bit. Thus this pin can be used as an FM |
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band selection switch. (Note that it should not be used |
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BOF |
2 (3) |
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as an AM band selection switch since it is susceptible to |
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noise from the crystal oscillator.) |
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DVS data: 0 = open, 1 = low |
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All output ports are set to the open state following a |
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power on reset. |
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I/O dual-use pins |
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The direction (input or output) is determined by bits IOC1 |
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and IOC2 in the serial data. |
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Data: 0 = input port, 1 = output port |
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When specified for use as input ports: |
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The state of the input pin is transmitted to the controller |
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over the DO pin. |
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IO1 |
11 (12) |
Input or output |
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Input state: low = 0 data value |
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ports |
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IO2 |
13 (14) |
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high = 1 data value |
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When specified for use as output ports: |
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The output states are determined by the IO1 and IO2 |
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bits in the serial data. |
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Data: 0 = open, 1 = low |
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• |
These pins function as input pins following a power on |
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reset. |
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• PLL charge pump output |
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When the frequency generated by dividing the local |
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Charge pump |
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oscillator signal frequency by N is higher than the |
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PD |
18 (19) |
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reference frequency, a high level is output from the PD |
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output |
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pin. Similarly, when that frequency is lower, a low level is |
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output. The PD pin goes to the high-impedance state |
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when the frequencies match. |
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AIN |
19 (20) |
LPF amplifier |
• The n-channel MOS transistor used for the PLL active |
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transistor |
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AOUT |
20 (21) |
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low-pass filter. |
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connections |
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• Accepts an input in the frequency range 0.4 to 12 MHz. |
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• |
The input signal is directly transmitted to the IF counter. |
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IFIN |
12 (13) |
IF counter |
• |
The result is output starting the MSB of the IF counter |
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using the DO pin. |
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• Four measurement periods are supported: 4, 8, 32, and |
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64 ms. |
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No. 5038-7/23