SANYO LC72136M, LC72136 Datasheet

0 (0)

Ordering number : EN5038

CMOS LSI

LC72136, 72136M

PLL Frequency Synthesizer

for Electronic Tuning

Overview

The LC72136 and LC72136M are PLL frequency synthesizers for use in radio/cassette players. They allow high-performance AM/FM tuners to be implemented easily.

Features

High-speed programmable frequency divider

FMIN: 10 to 160 MHz .....Pulse swallower

(divide-by-two prescaler built in)

AMIN: 2 to 40 MHz .........Pulse swallower

0.5to 10 MHz ......Direct division

IF counter

IFIN: 0.4 to 12 MHz ................For use as an AM/FM IF

counter

Reference frequency

Selectable from one of eight frequencies (crystal oscillator: 75 kHz)

1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz

Phase comparator

Supports dead zone control

Built-in unlock detection circuit

Built-in deadlock clear circuit

Built-in MOS transistor for forming an active low-pass filter

I/O ports

Dedicated output ports: 6

I/O ports: 2

Supports clock time base output

Serial Data I/O

Supports CCB format communication with the system controller.

Operating ranges

Supply voltage: 4.5 to 5.5 V

Operating temperature: –20 to +70°C

Packages —DIP22S/MFP24S

CCB is a trademark of SANYO ELECTRIC CO., LTD.

CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Package Dimensions

unit: mm

3059-DIP22S

[LC72136]

SANYO: DIP22S

unit: mm

3112-MFP24S

[LC72136M]

SANYO: MFP24S

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

O3195HA (OT) No. 5038-1/23

LC72136, 72136M

Pin Assignments

No. 5038-2/23

SANYO LC72136M, LC72136 Datasheet

LC72136, 72136M

Block Diagram

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter

Symbol

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Conditions

Ratings

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum supply voltage

VDD max

 

VDD

–0.3 to +7.0

V

 

VIN1 max

 

CE, CL, DI, AIN

–0.3 to +7.0

V

Maximum input voltage

VIN2 max

 

XIN, FMIN, AMIN, IFIN

–0.3 to VDD + 0.3

V

 

VIN3 max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–0.3 to +15

V

 

 

IO1,

 

 

 

IO2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VO1 max

 

DO

–0.3 to +7.0

V

Maximum output voltage

VO2 max

 

XOUT, PD

–0.3 to VDD + 0.3

V

 

VO3 max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BO1 to BO5,

BOF,

 

 

IO1,

IO2,

AOUT

–0.3 to +15

V

 

IO1 max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BO1

0 to 3.0

mA

Maximum output current

IO2 max

 

AOUT, DO

0 to 6.0

mA

 

IO3 max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BO2 to BO5, BOF,

IO1,

 

 

IO2

 

0 to 10.0

mA

Allowable power dissipation

Pd max

 

Ta 70°C: LC72136 (DIP22S)

350

mW

 

Ta 70°C: LC72136M (MFP24S)

200

mW

 

 

 

Operating temperature

Topr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–20 to +70

°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Storage temperature

Tstg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–40 to +125

°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

No. 5038-3/23

LC72136, 72136M

Allowable Operating Ranges at Ta = –20 to +70°C, VSS = 0 V

Parameter

Symbol

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Conditions

min

typ

max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Supply voltage

VDD

 

VDD

4.5

 

5.5

V

Input high-level voltage

VIH1

 

CE, CL, DI

0.7 VDD

 

6.5

V

VIH2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IO1, IO2

0.7 VDD

 

13

V

Input low-level voltage

VIL

 

 

 

 

 

 

 

 

 

 

 

CE, CL, DI,

IO1,

IO2

0

 

0.3 VDD

V

Output voltage

VO1

 

DO

0

 

6.5

V

VO2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BO1 to BO5, BOF, IO1, IO2, AOUT

0

 

13

V

 

fIN1

 

XIN: VIN1

 

75

 

kHz

 

fIN2

 

FMIN: VIN2

10

 

160

MHz

Input frequency

fIN3

 

AMIN: VIN3, SNS = 1

2

 

40

MHz

 

fIN4

 

AMIN: VIN4, SNS = 0

0.5

 

10

MHz

 

fIN5

 

IFIN: VIN5

0.4

 

12

MHz

 

VIN1

 

XIN: fIN1

400

 

1500

mVrms

 

VIN2-1

 

FMIN: f = 10 to 130 MHz

40

 

1500

mVrms

 

VIN2-2

 

FMIN: f = 130 to 160 MHz

70

 

1500

mVrms

Input amplitude

VIN3

 

AMIN: fIN3, SNS = 1

40

 

1500

mVrms

 

VIN4

 

AMIN: fIN4, SNS = 0

40

 

1500

mVrms

 

VIN5-1

 

IFIN: fIN5, IFS = 1

40

 

1500

mVrms

 

VIN5-2

 

IFIN: fIN6, IFS = 0

70

 

1500

mVrms

Guaranteed crystal

Xtal

 

XIN, XOUT*

 

75

 

kHz

oscillator frequency

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: * Crystal oscillator recommended CI value CI ≤ 35 kΩ (for a 75 kHz crystal)

The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and other items. Therefore we recommend consulting with the manufacturer of the crystal for evaluation and reliability.

The extremely high input impedance of the XIN pins means that applications must take the possibility of leakage into account.

Sample Oscillator Circuits

1. Seiko-Epson C-2-75kHz (CL = 11 pF)

2. Kyocera Corporation KF-38R5-09P0300 (CL = 9 pF)

No. 5038-4/23

LC72136, 72136M

Electrical Characteristics at Ta = –20 to +70°C, VSS = 0 V

Parameter

Symbol

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Conditions

min

typ

max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rf1

 

 

XIN

 

8.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Internal feedback resistors

Rf2

 

 

FMIN

 

500

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rf3

 

 

AMIN

 

500

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rf4

 

 

IFIN

 

250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Internal pull-down resistors

Rpd1

 

 

FMIN

 

200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rpd2

 

 

AMIN

 

200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Internal output resistor

Rd

 

 

XOUT

 

250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hysteresis

VHIS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE, CL, DI, IO1, IO2

 

0.1 VDD

 

V

Output high-level voltage

VOH1

 

 

PD: IO = –1 mA

VDD – 1.0

 

 

V

 

VOL1

 

 

PD: IO = 1 mA

 

 

1.0

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOL2

 

 

BO1: IO = 0.5 mA

 

 

0.5

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BO1: IO = 1 mA

 

 

1.0

V

 

 

 

 

 

 

 

VOL3

 

 

DO: IO = 1 mA

 

 

0.2

V

Output low-level voltage

 

 

DO: IO = 5 mA

 

 

1.0

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BO2 to BO5, BOF, IO1, IO2: IO = 1 mA

 

 

0.2

V

 

VOL4

 

 

BO2 to BO5, BOF, IO1, IO2: IO = 5 mA

 

 

1.0

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BO2 to BO5, BOF, IO1, IO2: IO = 8 mA

 

 

1.6

V

 

VOL5

 

 

AOUT: IO = 1 mA, AIN = 1.3 V

 

 

0.5

V

 

IIH1

 

 

CE, CL, DI: VI = 6.5 V

 

 

5.0

µA

 

IIH2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IO1, IO2: VI = 13 V

 

 

5.0

µA

Input high-level voltage

IIH3

 

 

XIN: VI = VDD

0.3

0.6

1.4

µA

IIH4

 

 

FMIN, AMIN: VI = VDD

4.0

 

22

µA

 

 

 

 

 

IIH5

 

 

IFIN: VI = VDD

8.0

 

44

µA

 

IIH6

 

 

AIN: VI = 6.5 V

 

 

200

nA

 

IIL1

 

 

CE, CL, DI: VI = 0 V

 

 

5.0

µA

 

IIL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IO1, IO2: VI = 0 V

 

 

5.0

µA

Input low-level current

IIL3

 

 

XIN: VI = 0 V

0.3

0.6

1.4

µA

IIL4

 

 

FMIN, AMIN: VI = 0 V

4.0

 

22

µA

 

 

 

 

 

IIL5

 

 

IFIN: VI = 0 V

8.0

 

44

µA

 

IIL6

 

 

AIN: VI = 0 V

 

 

200

nA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output off leakage current

IOFF1

 

 

BO1 to BO5, BOF, AOUT, IO1, IO2: VO = 13 V

 

 

5.0

µA

IOFF2

 

 

DO: VO = 6.5 V

 

 

5.0

µA

 

 

 

 

 

High-level tree-state off

IOFFH

 

 

PD: VO = VDD

 

0.01

200

nA

leakage current

 

 

 

Low-level tree-state off

IOFFL

 

 

PD: VO = 0 V

 

0.01

200

nA

leakage current

 

 

 

Input capacitance

CIN

 

 

FMIN

 

6

 

pF

 

IDD1

 

 

VDD: Xtal = 75 kHz, fIN2 = 130 MHz, VIN2 = 40 mVrms

 

5

10

mA

Current drain

IDD2

 

 

VDD: PLL block stopped (PLL inhibit),

 

0.1

 

mA

 

 

Xtal oscillator operating (Xtal = 75 kHz)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD3

 

 

VDD: PLL block stopped, Xtal oscillator stopped

 

 

10

µA

No. 5038-5/23

LC72136, 72136M

Pin Functions

 

Pin No.

 

 

 

 

Symbol

(MFP pin numbers

Type

 

Functions

Circuit configuration

 

are in parentheses.)

 

 

 

 

 

 

 

 

 

 

XIN

1 (1)

 

Crystal oscillator connections (75 kHz)

 

Xtal

• The extremely high input impedance of the XIN pins

 

XOUT

22 (24)

 

means that applications must take the possibility of

 

 

 

 

 

 

 

 

leakage into account.

 

 

 

 

 

 

 

 

 

 

FMIN is selected when the serial data input DVS bit is

 

 

 

 

 

set to 1.

 

 

 

 

• The input frequency range is from 10 to 160 MHz.

 

FMIN

16 (17)

Local oscillator

The input signal passes through the internal divide-by-

 

signal input

 

two prescaler and is input to the swallow counter.

 

 

 

 

 

 

 

 

• The divisor can be in the range 272 to 65535. However,

 

 

 

 

 

since the signal has passed through the divide-by-two

 

 

 

 

 

prescaler, the actual divisor is twice the set value.

 

 

 

 

 

 

 

 

 

 

AMIN is selected when the serial data input DVS bit is

 

 

 

 

 

set to 0.

 

 

 

 

When the serial data input SNS bit is set to 1:

 

 

 

 

 

— The input frequency range is 2 to 40 MHz.

 

 

 

 

 

— The signal is directly input to the swallow counter.

 

 

 

Local oscillator

 

— The divisor can be in the range 272 to 65535, and

 

AMIN

15 (16)

 

the divisor used will be the value set.

 

signal input

 

 

 

 

When the serial data input SNS bit is set to 0:

 

 

 

 

 

 

 

 

 

— The input frequency range is 0.5 to 10 MHz.

 

 

 

 

 

— The signal is directly input to a 12-bit programmable

 

 

 

 

 

divider.

 

 

 

 

 

— The divisor can be in the range 4 to 4095, and the

 

 

 

 

 

divisor used will be the value set.

 

 

 

 

 

 

 

CE

3 (4)

Chip enable

Set this pin high when inputting (DI) or outputting (DO)

 

 

serial data.

 

 

 

 

 

 

 

 

 

 

 

 

CL

5 (6)

Clock

Used as the synchronization clock when inputting (DI) or

 

 

outputting (DO) serial data.

 

 

 

 

 

 

 

 

 

 

 

 

DI

4 (5)

Input data

Inputs serial data transferred from the controller to the

 

 

LC72136.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Outputs serial data transferred from the LC72136 to the

 

DO

6 (7)

Output data

 

controller. The data output is determined by the DOC0 to

 

 

 

 

 

DOC2 bits in the serial data.

 

 

 

 

 

 

VDD

17 (18)

 

• The LC72136 power supply pin. (VDD = 4.5 to 5.5 V)

 

Power supply

The power on reset circuit operates when power is first

 

 

 

 

 

applied.

 

 

 

 

 

 

VSS

21 (22)

Ground

• The LC72136 ground

 

Continued on next page.

No. 5038-6/23

LC72136, 72136M

Continued from preceding page.

 

 

 

 

 

Pin No.

 

 

 

 

 

 

 

 

 

 

Symbol

(MFP pin numbers

Type

 

Functions

Circuit configuration

 

 

 

 

 

are in parentheses.)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dedicated outputs

 

 

 

 

 

 

 

 

• The output states are determined by the BO1 to BO5

 

 

 

 

 

 

 

 

 

bits in the serial data.

 

 

 

 

 

 

 

 

 

Data: 0 = open, 1= low

 

 

 

 

BO1

7 (8)

 

• A time base signal (8 Hz) can be output from the BO1

 

 

 

 

 

 

 

 

 

pin. (When the serial data TBC bit is set to 1.)

 

 

BO2

8 (9)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Care is required when using the BO1 pin, since it has a

 

 

 

 

 

 

 

 

 

 

BO3

9 (10)

 

 

 

 

 

higher on impedance that the other output ports (pins

 

 

 

 

 

 

 

 

 

 

 

BO4

10 (11)

Output ports

 

BO2 to BO5).

 

 

 

 

 

 

 

 

 

 

The output state of the BOF pin is determined by the

 

 

BO5

14 (15)

 

 

 

 

 

serial data DVS bit. Thus this pin can be used as an FM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

band selection switch. (Note that it should not be used

 

BOF

2 (3)

 

 

as an AM band selection switch since it is susceptible to

 

 

 

 

 

 

 

 

 

noise from the crystal oscillator.)

 

 

 

 

 

 

 

 

 

DVS data: 0 = open, 1 = low

 

 

 

 

 

 

 

 

All output ports are set to the open state following a

 

 

 

 

 

 

 

 

 

power on reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O dual-use pins

 

 

 

 

 

 

 

 

The direction (input or output) is determined by bits IOC1

 

 

 

 

 

 

 

 

 

and IOC2 in the serial data.

 

 

 

 

 

 

 

 

 

Data: 0 = input port, 1 = output port

 

 

 

 

 

 

 

 

When specified for use as input ports:

 

 

 

 

 

 

 

 

 

The state of the input pin is transmitted to the controller

 

 

 

 

 

 

 

 

 

over the DO pin.

 

 

IO1

11 (12)

Input or output

 

 

 

 

Input state: low = 0 data value

 

 

 

 

 

 

 

ports

 

 

 

IO2

13 (14)

 

 

 

 

high = 1 data value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When specified for use as output ports:

 

 

 

 

 

 

 

 

 

The output states are determined by the IO1 and IO2

 

 

 

 

 

 

 

 

 

bits in the serial data.

 

 

 

 

 

 

 

 

 

Data: 0 = open, 1 = low

 

 

 

 

 

 

 

 

These pins function as input pins following a power on

 

 

 

 

 

 

 

 

 

reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• PLL charge pump output

 

 

 

 

 

 

 

 

 

When the frequency generated by dividing the local

 

 

 

 

 

 

 

Charge pump

 

oscillator signal frequency by N is higher than the

 

 

 

PD

18 (19)

 

reference frequency, a high level is output from the PD

 

 

 

output

 

 

 

 

 

 

 

 

 

pin. Similarly, when that frequency is lower, a low level is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

output. The PD pin goes to the high-impedance state

 

 

 

 

 

 

 

 

 

when the frequencies match.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AIN

19 (20)

LPF amplifier

• The n-channel MOS transistor used for the PLL active

 

 

transistor

 

AOUT

20 (21)

 

low-pass filter.

 

connections

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Accepts an input in the frequency range 0.4 to 12 MHz.

 

 

 

 

 

 

 

 

The input signal is directly transmitted to the IF counter.

 

 

IFIN

12 (13)

IF counter

The result is output starting the MSB of the IF counter

 

 

 

using the DO pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Four measurement periods are supported: 4, 8, 32, and

 

 

 

 

 

 

 

 

 

64 ms.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

No. 5038-7/23

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