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DATA SHEET
TFT COLOR LCD MODULE
NL6448AC33-29
26 cm (10.4 inches), 640 × 480 pixels, 262,144 colors,
Incorporated two-lamp/Edge-light type backlight Ultra Wide viewing angle
DESCRIPTION
NL6448AC33-29 is a TFT (thin film transistor) active matrix color liquid crystal display (LCD) comprising amorphous silicon TFT attached to each signal electrode, a driving circuit and a backlight. NL6448AC33-29 has a built-in backlight. Backlight includes long-life-lamps and the lamps are replaceable.
The 26 cm (10.4 inches) diagonal display area contains 640 × 480 pixels and can display 262,144 colors simultaneously.
NL6448AC33-29 is suitable for industrial application use, because the viewing angle is ultra wide and the luminance is high. Also the viewing direction is selectable either upper or lower side changing scan direction.
FEATURES
•Ultra wide viewing angle with lateral electric field
•High luminance (250 cd/m2, typ.)
•Low reflection
•6-bit digital RGB interface
•Data enable (DE) function
•Incorporated edge type backlight with lamps (Two lamps, with inverter)
•Lamp holder replaceable (Type No.: 104LHS31)
•Reversible scan direction
•Variable luminance control
•Easy to assemble a touch panel
•No antiglare treatment
APPLICATIONS
•Display terminals for control system
•Monitors for process controller
•Industrial PC
The information in this document is subject to change without notice.
Document No. EN0439EJ1V0DS00 |
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Date Published May 1999 P |
© |
1999 |
Printed in Japan |
NL6448AC33-29
STRUCTURE AND FUNCTIONS
A color TFT (thin film transistor) LCD module is comprised of a TFT liquid crystal panel structure, LSIs for driving the TFT array, and a backlight assembly. The TFT panel structure is created by sandwiching liquid crystal material in the narrow gap between a TFT array glass substrate and a color filter glass substrate. After the driver LSIs are connected to the panel, the backlight assembly is attached to the backside of the panel.
RGB (red, green, blue) data signals from a source system is modulated into a form suitable for active matrix addressing by the onboard signal processor and sent to the driver LSIs which in turn addresses the individual TFT cells.
Acting as an electro-optical switch, each TFT cell regulates light transmission from the backlight assembly when activated by the data source. By regulating the amount of light passing through the array of red, green, and blue dots, color images are created with clarity.
BLOCK DIAGRAM
<1> In case of use the inverter of NEC
R0 - R5
G0 - G5
B0 - B5
CLK
Hsync
Vsync
DPS
DE
VCC
VDDB
GNDB
BRTHL
BRTC
BRTH
BRTL
Frame
GND (SG)
Digital signal processor
LCD timing controller
Power supply circuit
Level shift
V-driver |
480 lines |
Scan select
LSIs
Drivers
Inverter
H-driver
1920 lines
TFT LCD panel
H: 640 × 3 (R, G, B) V: 480
Backlight
Note Both frame and GNDB (Backlight ground) are not contacted to the lamp holder.
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Data Sheet EN0439EJ1V0DS00 |
NL6448AC33-29
<2> In case of use the inverter of customers
R0 - R5 |
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signal |
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Level |
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G0 - G5 |
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shift |
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B0 - B5 |
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processor |
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V-driver |
480 lines |
CLK |
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Hsync |
LCD timing |
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Vsync |
Scan select |
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controller |
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DPS |
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DE |
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Power |
LSIs |
VCC |
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supply |
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circuit |
Drivers |
VH
VL
Frame
GND (SG)
H-driver
1920 lines
TFT LCD panel
H: 640 × 3 (R, G, B) V: 480
Backlight
Note Both frame and GNDB (Backlight ground) are not contacted to the lamp holder.
Data Sheet EN0439EJ1V0DS00 |
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NL6448AC33-29
OUTLINE OF CHARACTERISTICS (at room temperature)
Display area |
211.2 (H) × 158.4 (V) mm |
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Drive system |
a-Si TFT active matrix |
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Display colors |
262,144 colors |
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Number of pixels |
640 × 480 pixels |
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Pixel arrangement |
RGB vertical stripe |
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Pixel pitch |
0.33 (H) × 0.33 (V) mm |
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Module size |
243.0 (H) × 185.1 (V) × 10.5 typ. (D) mm |
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Inverter size |
25.0 (H) × 105.0 (V) × 10.2 max. (D) mm |
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Weight |
510 g (typ.) + 15 g (typ., inverter) |
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Contrast ratio |
150 : 1 (typ.) |
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Viewing angle (more than the contrast ratio of 10 : 1) |
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Horizontal |
: 80° (typ., left side, right side) |
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Vertical |
: 80° (typ., up side, down side) |
Designed viewing direction |
Optimum grayscale (γ = 2.2): perpendicular |
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Color gamut |
45% (typ., At center, to NTSC) |
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Response time |
50 ms (typ.), black to white |
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Luminance |
250 cd/m2 (typ.) |
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Signal system |
6-bit digital signals for each of RGB primary colors, synchronous signals |
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(Hsync, Vsync), dot clock (CLK) |
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Supply voltages |
3.3 V [5.0 V] (Logic, LCD driving), 12.0 V (Backlight) |
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Backlight |
Edge light type, two cold cathode fluorescent lamp |
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Power consumption |
7.1 W (typ., 3.3 V, 12.0 V) |
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4 |
Data Sheet EN0439EJ1V0DS00 |
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NL6448AC33-29 |
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GENERAL SPECIFICATIONS |
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Item |
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Specification |
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Unit |
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Module size |
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243.0 ± 0.5 (H) × 185.1 ± 0.5 (V) × 11.2 max. (D) |
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mm |
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Inverter size |
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25.0 ± 0.5 (H) × 105.0–0.3+0.7 (V) × 10.2 max. (D) |
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mm |
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Display area |
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211.2 (H) × 158.4 (V) |
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mm |
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Number of dots |
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640 × 3 (H) × 480 (V) |
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dot |
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Number of pixels |
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640 (H) × 480 (V) |
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pixel |
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Dot pitch |
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0.11 (H) × 0.33 (V) |
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mm |
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Pixel pitch |
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0.33 (H) × 0.33 (V) |
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mm |
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Pixel arrangement |
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RGB (Red, Green, Blue) vertical stripe |
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– |
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Display colors |
262,144 |
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color |
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Weight |
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Module: |
530 (max.) + Inverter: 20 (max.) |
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g |
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ABSOLUTE MAXIMUM RATINGS |
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Parameter |
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Symbol |
Rating |
Unit |
Remarks |
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Supply voltage |
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VCC |
–0.3 to 6.5 |
V |
Ta = 25°C |
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VI – VCC < 0.3 |
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Input voltage |
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VI |
–0.3 to 6.5 |
V |
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Supply voltage |
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VDDB |
–0.3 to 15.0 |
V |
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Input voltage |
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BRTC |
–0.3 to 7.0 |
V |
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Lamp voltage |
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VL |
2000 |
Vrms |
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Storage temp. |
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TST |
–20 to 60 |
°C |
− |
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Operating temp. |
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TOP |
0 to 50 |
°C |
Module surfaceNote |
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Humidity |
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RH |
≤ 95% relative humidity |
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Ta ≤ 40°C |
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(No condensation) |
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≤ 85% relative humidity |
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40 < Ta ≤ 50°C |
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Absolute humidity shall not |
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Ta > 50°C |
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exceed Ta = 50°C, |
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85% relative humidity level. |
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Note Measured at the display area
Data Sheet EN0439EJ1V0DS00 |
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NL6448AC33-29 |
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ELECTRICAL CHARACTERISTICS |
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(1) Logic, LCD driving |
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Ta = 25°C |
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Parameter |
Symbol |
MIN. |
TYP. |
MAX. |
Unit |
Remarks |
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Supply voltage |
VCC |
3.0 |
3.3 |
3.6 |
V |
VCC = 3.3 V |
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(4.75) |
(5.0) |
(5.25) |
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(VCC = 5.0 V) |
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Logic input Low voltage |
VIL |
0 |
– |
VCC × 0.3 |
V |
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Logic input High voltage |
VIH |
VCC × 0.7 |
– |
5.25 |
V |
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Supply current |
ICC |
– |
400Note |
600 |
mA |
VCC = 3.3 V |
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– |
(300) |
(400) |
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(VCC = 5.0 V) |
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Note Checkered flag pattern (in EIAJ ED-2522)
(2) Backlight
<1> |
Inventer |
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Ta = 25°C |
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Parameter |
Symbol |
MIN. |
TYP. |
MAX. |
Unit |
Remarks |
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Supply voltage |
VDDB |
11.4 |
12.0 |
12.6 |
V |
– |
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Logic input “L” voltage |
V IL |
0 |
– |
0.8 |
V |
BRTC |
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Logic input “H” voltage |
V IH |
2.0 |
– |
5.0 |
V |
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Luminance control |
– |
– |
2.5 |
– |
V |
Minimum luminance |
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voltage |
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– |
– |
1.2 |
– |
V |
Maximum luminance |
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Supply current |
IDDB |
– |
480 |
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mA |
250 cd/m2 |
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<2> |
Lamp |
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Parameter |
Symbol |
MIN. |
TYP. |
MAX. |
Unit |
Remarks |
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Lamp current |
IL |
2.0 × 2 |
5.0 × 2 |
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mArms |
With two lamps |
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Lamp voltage |
VL |
– |
510 |
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Vrms |
IL = 5 mArms |
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Power supply |
PL |
– |
2.55 |
– |
W |
– |
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Lamp turn on voltage |
Vs |
840 |
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mA |
Ta = 25°C |
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1265 |
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mA |
Ta = 0°C |
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Oscillator frequency |
Ft |
50 |
54 |
58 |
kHz |
Note |
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Note
th: Hsync period
n : a natural number (1, 2, 3, ···)
If Ft is out of the recommended value, interference between Ft frequency and Hsync frequency may cause beat on the display.
6 |
Data Sheet EN0439EJ1V0DS00 |
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NL6448AC33-29 |
SUPPLY VOLTAGE SEQUENCE |
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Notes 1. |
The supply voltage for input signals should |
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3.0 V (4.75 V) |
0 < t < 35 ms |
0 < t < 35 ms |
3.0 V (4.75 V) |
be the same as VCC. |
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VCC |
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Signals Notes 1, 2, 3 |
VALID |
2. |
Apply VDDB within the LCD operation period. |
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When the |
backlight turns on before LCD |
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ON |
OFF |
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operation |
or the LCD operation turns off |
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Time |
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before the backlight turns off, the display |
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may momentarily become white. |
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3. |
While the power is off, please keep whole |
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signals (Hsync, Vsync, CLK, DE, and DATA) |
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at low level or high impedance. |
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INTERFACE AND PIN CONNECTION
(1) Interface signals, power supply |
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Module side connector |
Mating connector |
CN1 ··· DF9C-31P-1V (No.1 to 31) |
DF9-31S-1V, DF9M-31S-1R ······ (1) |
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IL-310-T31S-VF ························· (2) |
Supplier: (1) HIROSE ELECTRIC CO., LTD., (2) Japan Aviation Electronics Industry Limited (JAE)
Pin No. |
Symbol |
Function |
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1 |
GND |
Ground (SG)Note 4 |
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CLK |
Dot clock |
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3 |
Hsync |
Horizontal sync. |
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4 |
Vsync |
Vertical sync. |
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5 |
GND |
GroundNote 4 |
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6 |
R0 |
Red data (LSB) |
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7 |
R1 |
Red data |
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8 |
R2 |
Red data |
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9 |
R3 |
Red data |
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10 |
R4 |
Red data |
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11 |
R5 |
Red data (MSB) |
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12 |
GND |
Ground Note 4 |
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13 |
G0 |
Green data (LSB) |
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14 |
G1 |
Green data |
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15 |
G2 |
Green data |
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16 |
G3 |
Green data |
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17 |
G4 |
Green data |
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18 |
G5 |
Green data (MSB) |
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Pin No. |
Symbol |
Function |
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19 |
GND |
GroundNote 4 |
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20 |
B0 |
Blue data (LSB) |
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21 |
B1 |
Blue data |
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22 |
B2 |
Blue data |
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23 |
B3 |
Blue data |
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24 |
B4 |
Blue data |
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25 |
B5 |
Blue data (MSB) |
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26 |
GND |
Ground Note 4 |
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27 |
DE |
Data enableNote 2 |
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28 |
VCC |
Power supplyNote 1 |
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29 |
VCC |
Power supplyNote 1 |
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30 |
N. C. |
Non-connection |
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31 |
DPS |
Scan direction selectNote 3 |
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LSB : Least Significant Bit
MSB : Most Significant Bit
Data Sheet EN0439EJ1V0DS00 |
7 |
NL6448AC33-29
Notes 1. |
VCC: All VCC terminals should be connected to 3.3 V or 5.0 V. |
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2. |
DE: DE/Fixed mode select is as follows. |
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Data enabled signal = DE mode |
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VCC or Open |
= Fixed mode |
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DPS: DPS changes display scan direction. |
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GND or Open = Scan direction will be decided by the setting of SW1. |
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VCC |
= Reverse scan |
INPUT SIGNAL TIMING See (4) DISPLAY POSITION about another way for reversible scan. (DPS is Open)
When DPS is VCC, reverse scan is selected even if SW1 is set at normal scan.
When DPS is GND, normal scan is selected even if SW1 is set at reverse scan.
4.GND is connected to the frame of the LCD module.
(2)Inverter
• Inverter side connector 1 |
Mating connector 1 |
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CN1 ··· LZ-5P-SL-SMT |
LZ-5S-SC3 |
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Supplier: Japan Aviation Electronics Industry Limited (JAE) |
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Pin No. |
Symbol |
Function |
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Pin No. |
Symbol |
Function |
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1 |
VDDB |
Power supply |
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4 |
GNDB |
Backlight ground |
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2 |
VDDB |
Power supply |
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5 |
BRTHL |
Luminance selectNote |
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3 |
GNDB |
Backlight ground |
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Note High luminance (100%): BRTHL = High or open
Low luminance (60%): BRTHL = Low (GNDB level)
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• Inverter side connector 2 |
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Mating connector 2 |
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CN3 ··· IL-Z-3PL-SMTY |
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IL-Z-3S-S125C3 |
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Supplier: Japan Aviation Electronics Industry Limited (JAE) |
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Pin No. |
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Symbol |
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Function |
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1 |
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BRTC |
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Backlight ON/OFF signalNote 1 |
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2 |
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BRTH |
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Luminance control inputNote 2 |
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3 |
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BRTL |
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Luminance control inputNote 2 |
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Notes 1. C-MOS level |
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Backlight ON |
: BRTC = High or open |
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Backlight OFF : BRTC = Low |
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2. |
<1> |
A way of luminance control by a variable resistor |
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This way works when BRTHL (No.5 pin) of CN1 is opened. |
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Mating variable resistor |
: 10 kΩ ±5% |
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BRTL |
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BRTH |
Minimum luminance (50%) |
: R = 0 Ω |
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Maximum luminance (100%) : R = 10 kΩ |
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R |
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<2> |
A way of luminance control by a voltage |
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This way works when BRTHL and BRTL are opened. The range of input voltage between |
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BRTH and GNDB is as follows. |
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Minimum luminance (50%) : 2.5 V |
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Maximum luminance (100%): ≤ 1.2 V |
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Data Sheet EN0439EJ1V0DS00 |
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NL6448AC33-29
<3> Connector location
Upper side
CN2 
LCD Module |
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<Rear view> |
CN1 |
Inverter
CN1
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1 |
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2 |
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CN3 |
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Lower side |
3 |
4 |
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• |
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• |
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1 |
1 |
31 |
30 |
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1 |
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<Pin arrangement of CN1> |
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2 |
2 |
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2 |
3 |
3 |
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3 |
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4 |
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<Pin arrangement of CN3> |
5 |
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<Pin arrangement of CN2>
<Pin arrangement of CN1>
Data Sheet EN0439EJ1V0DS00 |
9 |
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