NEC PD78056FY, PD78058F-A, PD78058FY, PD78P058FY, PD78056F User Manual

User’s Manual

µ

PD78058F, 78058FY Subseries

8-Bit Single-Chip Microcontrollers

µ

PD78056F

µ

PD78058F

µ

PD78P058F

µ

PD78058F(A)

µ

PD78056FY

µ

PD78058FY

µ

PD78P058FY

µ

PD78058FY(A)

Document No. U12068EJ2V0UM00 (2nd edition)
Date Published April 1998 N CP (K)

©

Printed in Japan

1997

[MEMO]

2

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.

DD or GND with a resistor, if it is considered to have a

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.

FIP, EEPROM, and IEBus are trademarks of NEC Corporation.
MS-DOS, Windows, and WindowsNT are either registered trademarks or trademarks of Microsoft Corpo­ration in the United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of XEROX Corporation.
NEWS and NEWS-OS are trademarks of SONY Corporation.
OSF/Motif is a trademark of Open Software Foundation, Inc.
TRON is an abbreviation of The Realtime Operating System Nucleus.
ITRON is an abbreviation of Industrial TRON.

3

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without
governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country
other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these

components in an I

2

C system, provided that the system conforms to the I2C Standard Specification as defined

by Philips.

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M7 96.5

4

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]

800-366-9782

Fax: [phone]

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel:[phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil
Tel: [phone]
Fax: [phone]

J98. 2

5

MAJOR REVISIONS IN THIS EDITION

Page Major Revision from Previous Edition

Throughout The following products have already been developed:

µ

PD78056FGC-×××-8BT, 78058FGC-×××-8BT, 78P058FGC-8BT, 78056FYGC-×××-8BT,

78058FYGC-×××-8BT

P133 to The block diagrams of the following ports were changed.
P137, P143 Figures 6-5 and 6-7 P20, P21, P23 to P26 Block Diagram, Figures 6-6 and 6-8 P22 and P27 Block

Diagram, Figure 6-9 P30 to P37 Block Diagram, Figure 6-16 P71 and P72 Block Diagram
P159 Table 7-2 Relationship between CPU Clock and Minimum Instruction Execution Time was added.
P230, P235 Figures 9-10 and 9-13 Square-Wave Output Operation Timing were added.
P295 Note related to operation controls when using the SBI mode of serial interface channel 0 was added.
P297 Note related to BSYE in Figure 16-5 Serial Bus Interface Control Register Format was changed.
P308 Cautions were added to 16.4.3 (2) (a) Bus release signal (REL), and (b) Command signal (CMD)
P435, P436 CSCK was deleted from Figure 19-1 Serial Interface Channel 2 Block Diagram, and Figure 19-2

Baud Rate Generator Block Diagram.
P438 Figure 19-3 Serial Operating Mode Register 2 Format was changed.
P440 Table 19-2 Serial Interface Channel 2 Operating Mode Settings (2) 3-wire serial I/O mode was

P459 Figure 19-10 Receive Error Timing was changed.
P468 19.4.4 Restrictions on using UART mode was added.
P565 APPENDIX A DIFFERENCES AMONG µPD78054, 78058F, AND 780058 SUBSERIES was added.
P567 APPENDIX B DEVELOPMENT TOOLS

P582 APPENDIX C EMBEDDED SOFTWARE

P591 APPENDIX E REVISION HISTORY was added.

changed.

Overall revision: Contents were adapted to correspond to in-circuit emulators IE-78K0-NS and

IE-78001-R-A

Overall revision: Fuzzy inference development support system was deleted.

The mark shows major revised points.

6

PREFACE

Readers This manual has been prepared for user engineers who want to understand the

functions of the µPD78058F and 78058FY Subseries and design and develop its
application systems and programs.
Affected versions are each of the versions in the following Subseries.

µ

PD78058F Subseries :µPD78056F, 78058F, 78P058F, 78058F(A)

µ

PD78058FY Subseries : µPD78056FY, 78058FY, 78P058FY, 78058FY(A)

Purpose This manual is intended for users to understand the functions described in the

Organization below.

µ

Organization The

PD78058F, 78058FY Subseries manual is organized by two volumes: this

manual and the instruction edition (common to the 78K/0 Series).

µ

PD78058F, 78058FY

Subseries
User’s Manual
(This Manual)

78K/0 Series

User’s Manual

Instructions

Pin functions CPU functions
Internal block functions Instruction set
Interrupt Explanation of each instruction
Other on-chip peripheral functions

7

How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic

circuits and microcontrollers.

For persons who use this manual as the manual for the µPD78058F(A) and
78058FY(A),

µ

→ The

When you want to understand the functions in general:
→ Read this manual in the order of the contents.
To know the µPD78058F and 78058FY Subseries instruction function in detail:
→ Refer to the 78K/0 Series User's Manual: Instructions (U12326E)
How to interpret the register format:
→

To learn the function of a register whose register name is known:
→ Refer to APPENDIX D REGISTER INDEX.
To know the electrical specifications of the µPD78058F and 78058FY Subseries:
→ Refer to separately available Data Sheet.
To know the details regarding the functions of the µPD78058F and 78058FY
Subseries:
→ Refer to separately available Application Notes.

PD78058F and 78058FY differ from the µPD78058F(A) and 78058FY(A)
only in their quality grades. For products with (A), please change the readings
for the product name as follows.

µ

PD78058F → µPD78058F(A)

µ

PD78058FY → µPD78058FY(A)

For the circled bit number, the bit name is defined as a reserved word in
RA78K/

0, and in CC78K/0, already defined in the header file named sfrbit.h.

Caution Examples used in this manual are prepared for “Standard” product

quality grade products for general electronic equipment. If the

examples of use in this manual are utilized in applications where a

“Special” product quality grade is required, please study concern-

ing the quality grade of each part and each circuit that will actually

be used.

8

Chapter Organization This manual divides the descriptions for the µPD78058F and 78058FY Subseries into

different chapters as shown below. Read only the chapters related to the device you use.

Chapter
Chapter 1 Outline (µPD78058F Subseries) √ —
Chapter 2 Outline (µPD78058FY Subseries) — √
Chapter 3 Pin Function (µPD78058F Subseries) √ —
Chapter 4 Pin Function (µPD78058FY Subseries) — √
Chapter 5 CPU Architecture √√
Chapter 6 Port Functions √√
Chapter 7 Clock Generator √√
Chapter 8 16-Bit Timer/Event Counter √√
Chapter 9 8-Bit Timer/Event Counter √√
Chapter 10 Watch Timer √√
Chapter 11 Watchdog Timer √√
Chapter 12 Clock Output Control Circuit √√
Chapter 13 Buzzer Output Control Circuit √√
Chapter 14 A/D Converter √√
Chapter 15 D/A Converter √√
Chapter 16 Serial Interface Channel 0 √ —

(µPD78058F Subseries)

Chapter 17 Serial Interface Channel 0 — √

(µPD78058FY Subseries)
Chapter 18 Serial Interface Channel 1 √√
Chapter 19 Serial Interface Channel 2 √√
Chapter 20 Real-Time Output Port √√
Chapter 21 Interrupt and Test Functions √√
Chapter 22 External Device Expansion Function √√
Chapter 23 Standby Function √√
Chapter 24 Reset Function √√
Chapter 25 ROM Correction √√
Chapter 26µPD78P058F, µPD78P058FY √√
Chapter 27 Instruction Set √√

µ

PD78058F SubseriesµPD78058FY Subseries

9

Differences between µPD78058F and µPD78058FY Subseries:

The µPD78058F and µPD78058FY Subseries are different in the following functions
of the serial interface channel 0.

Modes of Serial Interface Channel 0µPD78058FµPD78058FY

Subseries Subseries

3-wire serial I/O mode √√
2-wire serial I/O mode √√
SBI (serial bus interface) mode √ —

I2C bus mode — √
√ : Supported
— : Not supported

Conventions Data significance : Higher digits on the left and lower digits on the right

Active low representations : ××× (overscore over pin or signal names)

Note : Footnotes for item marked with Note in the text
Caution : Information requiring particular attention
Remarks : Supplementary information

Numeral representations : Binary ... ×××× or ×××× B

Decimal ... ××××
Hexadecimal ... ××××H

10

Related Documents The related documents indicated in this publication may include preliminary

versions. However, preliminary versions are not marked as such.

Related Documents for µPD78058F Subseries

Document Name

µ

PD78056F, 78058F Data Sheet U11795J U11795E

µ

PD78P058F Data Sheet U11796J U11796E

µ

PD78058F(A) Data Sheet U12325J U12325E

µ

PD78058F, 78058FY Subseries User’s Manual U12068J This manual
78K/0 Series User’s Manual—Instruction U12326J U12326E
78K/0 Series Instruction Table U10903J —
78K/0 Series Instruction Set U10904J —
78K/0 Series Application Note Basic (III) U10182J U10182E

Document No.

Japanese English

Related Documents for µPD78058FY Subseries

Document Name

µ

PD78056FY, 78058FY Data Sheet U12142J U12142E

µ

PD78P058FY Data Sheet U12076J U12076E

µ

PD78058F, 78058FY Subseries User’s Manual U12068J This manual
78K/0 Series User’s Manual — Instructions U12326J U12326E

78K/0 Series Instruction Table U10903J —
78K/0 Series Instruction Set U10904J —
78K/0 Series Application Note Basic (III) U10182J U10182E

Document No.

Japanese English

Caution The above documents are subject to change without prior notice. Be sure to use the latest

document for designing.

11

Development Tool Documents (User’s Manuals)

Document Name

RA78K0 Assembler Package Operation U11802J U11802E

Assembly language U11801J U11801E

Structured assembler language U11789J U11789E
RA78K Series Structured Assembler Preprocessor U12323J EEU-1402
CC78K0 C Compiler Operation U11517J U11517E

Language U11518J U11518E
CC78K0 C Compiler Application Note Programming know-how U13034J EEA-1208
CC78K Series Library Source File U12322J —
PG-1500 PROM Programmer U11940J U11940E
PG-1500 Controller PC-9800 Series (MS-DOS™) Base EEU-704 EEU-1291
PG-1500 Controller IBM PC Series (PC DOS™) Base EEU-5008 U10540E
IE-78K0-NS To be prepared To be prepared
IE-78001-R-A To be prepared To be prepared
IE-780308-NS-EM1 To be prepared To be prepared
IE-78064-R-EM EEU-905 EEU-1443
IE-780308-R-EM U11362J U11362E
EP-78230 EEU-985 EEU-1515
EP-78054GK-R EEU-932 EEU-1468
SM78K0 System Simulator Windows™ Base Reference U10181J U10181E
SM78K Series System Simulator External component user U10092J U10092E

open interface specifications
ID78K0-NS Integrated Debugger U12900J To be prepared

ID78K0 Integrated Debugger EWS Base Reference U11151J —
ID78K0 Integrated Debugger PC Base Reference U11539J —
ID78K0 Integrated Debugger Windows Base Guide U11649J —

Document No.

Japanese English

Caution The above documents are subject to change without prior notice. Be sure to use the latest

document for designing.

12

Documents for Embedded Software (User’s Manual)

Document Name

78K/0 Series Real-Time OS Basics U11537J U11537E

Installation U11536J U11536E

OS for 78K/0 Series MX78K0 Basics U12257J U12257E

Document No.

Japanese English

Other Documents

Document Name

IC PACKAGE MANUAL C10943X
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grade on NEC Semiconductor Devices C11531J C11531E
Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E
Guide to Quality Assurance for Semiconductor Devices — MEI-1202
Microcontroller Related Product Guide — Third Party Manufacturers U11416J —

Document No.

Japanese English

Caution The above documents are subject to change without prior notice. Be sure to use the latest

document for designing.

13

[MEMO]

14

CONTENTS

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) ............................................................................. 35

1.1 Features .................................................................................................................................. 35

1.2 Applications ........................................................................................................................... 36

1.3 Ordering Information ............................................................................................................. 36

1.4 Quality Grade ......................................................................................................................... 37

1.5 Pin Configuration (Top View)................................................................................................ 38

1.6 78K/0 Series Expansion ........................................................................................................ 41

1.7 Block Diagram ........................................................................................................................ 43

1.8 Outline of Function ................................................................................................................ 44

1.9 Differences Between the µPD78058F and µPD78058F(A) .................................................. 45

1.10 Mask Options ......................................................................................................................... 46

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) ........................................................................... 47

2.1 Features .................................................................................................................................. 47

2.2 Applications ........................................................................................................................... 48

2.3 Ordering Information ............................................................................................................. 48

2.4 Quality Grade ......................................................................................................................... 49

2.5 Pin Configuration (Top View)................................................................................................ 50

2.6 78K/0 Series Expansion ........................................................................................................ 53

2.7 Block Diagram ........................................................................................................................ 55

2.8 Outline of Function ................................................................................................................ 56

2.9 Differences Between the µPD78058FY and µPD78058FY(A) ............................................. 57

2.10 Mask Options ......................................................................................................................... 58

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES).................................................................... 59

3.1 Pin Function List .................................................................................................................... 59

3.1.1 Normal operating mode pins ........................................................................................................ 59

3.1.2 PROM programming mode pins (PROM versions only)............................................................... 64

3.2 Description of Pin Functions ................................................................................................ 65

3.2.1 P00 to P07 (Port 0) ...................................................................................................................... 65

3.2.2 P10 to P17 (Port 1) ...................................................................................................................... 66

3.2.3 P20 to P27 (Port 2) ...................................................................................................................... 66

3.2.4 P30 to P37 (Port 3) ...................................................................................................................... 67

3.2.5 P40 to P47 (Port 4) ...................................................................................................................... 68

3.2.6 P50 to P57 (Port 5) ...................................................................................................................... 68

3.2.7 P60 to P67 (Port 6) ...................................................................................................................... 68

3.2.8 P70 to P72 (Port 7) ...................................................................................................................... 69

3.2.9 P120 to P127 (Port 12) ................................................................................................................ 70

3.2.10 P130 and P131 (Port 13) ............................................................................................................. 70

3.2.11 AV

3.2.12 AVREF1........................................................................................................................................... 70

3.2.13 AV

REF0........................................................................................................................................... 70

DD ............................................................................................................................................. 71

15

3.2.14 AVSS.............................................................................................................................................. 71

3.2.15 RESET ......................................................................................................................................... 71

3.2.16 X1 and X2 .................................................................................................................................... 71

3.2.17 XT1 and XT2 ................................................................................................................................ 71

3.2.18 V

3.2.19 V

DD ............................................................................................................................................... 71

SS ................................................................................................................................................ 71

3.2.20 VPP (PROM versions only)............................................................................................................ 71

3.2.21 IC (Mask ROM version only) ........................................................................................................ 72

3.3 Input/output Circuits and Recommended Connection of Unused Pins ........................... 73

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) ................................................................. 77

4.1 Pin Function List .................................................................................................................... 77

4.1.1 Normal operating mode pins ........................................................................................................ 77

4.1.2 PROM programming mode pins (PROM versions only)............................................................... 82

4.2 Description of Pin Functions ................................................................................................ 83

4.2.1 P00 to P07 (Port 0) ...................................................................................................................... 83

4.2.2 P10 to P17 (Port 1) ...................................................................................................................... 84

4.2.3 P20 to P27 (Port 2) ...................................................................................................................... 84

4.2.4 P30 to P37 (Port 3) ...................................................................................................................... 85

4.2.5 P40 to P47 (Port 4) ...................................................................................................................... 86

4.2.6 P50 to P57 (Port 5) ...................................................................................................................... 86

4.2.7 P60 to P67 (Port 6) ...................................................................................................................... 86

4.2.8 P70 to P72 (Port 7) ...................................................................................................................... 87

4.2.9 P120 to P127 (Port 12) ................................................................................................................ 88

4.2.10 P130 and P131 (Port 13) ............................................................................................................. 88

4.2.11 AV

REF0........................................................................................................................................... 88

4.2.12 AVREF1........................................................................................................................................... 88

4.2.13 AVDD ............................................................................................................................................. 89

4.2.14 AV

SS.............................................................................................................................................. 89

4.2.15 RESET ......................................................................................................................................... 89

4.2.16 X1 and X2 .................................................................................................................................... 89

4.2.17 XT1 and XT2 ................................................................................................................................ 89

4.2.18 V

DD ............................................................................................................................................... 89

4.2.19 VSS ................................................................................................................................................ 89

4.2.20 V

PP (PROM versions only)............................................................................................................ 89

4.2.21 IC (Mask ROM version only) ........................................................................................................ 90

4.3 Input/output Circuits and Recommended Connection of Unused Pins ........................... 91

CHAPTER 5 CPU ARCHITECTURE.....................................................................................................95

5.1 Memory Spaces...................................................................................................................... 95

5.1.1 Internal program memory space .................................................................................................. 98

5.1.2 Internal data memory space......................................................................................................... 99

5.1.3 Special Function Register (SFR) area ......................................................................................... 99

5.1.4 External memory space ............................................................................................................... 99

5.1.5 Data memory addressing ............................................................................................................. 100

5.2 Processor Registers .............................................................................................................. 103

16

5.2.1 Control registers ........................................................................................................................... 103

5.2.2 General registers.......................................................................................................................... 106

5.2.3 Special Function Register (SFR).................................................................................................. 108

5.3 Instruction Address Addressing .......................................................................................... 112

5.3.1 Relative addressing...................................................................................................................... 112

5.3.2 Immediate addressing .................................................................................................................. 113

5.3.3 Table indirect addressing ............................................................................................................. 114

5.3.4 Register addressing ..................................................................................................................... 115

5.4 Operand Address Addressing .............................................................................................. 116

5.4.1 Implied addressing ....................................................................................................................... 116

5.4.2 Register addressing ..................................................................................................................... 117

5.4.3 Direct addressing ......................................................................................................................... 118

5.4.4 Short direct addressing ................................................................................................................ 119

5.4.5 Special-Function Register (SFR) addressing ............................................................................... 121

5.4.6 Register indirect addressing......................................................................................................... 122

5.4.7 Based addressing ........................................................................................................................ 123

5.4.8 Based indexed addressing ........................................................................................................... 124

5.4.9 Stack addressing.......................................................................................................................... 124

CHAPTER 6 PORT FUNCTIONS.......................................................................................................... 125

6.1 Port Functions........................................................................................................................ 125

6.2 Port Configuration ................................................................................................................. 130

6.2.1 Port 0............................................................................................................................................ 130

6.2.2 Port 1............................................................................................................................................ 132

6.2.3 Port 2 (µPD78058F Subseries) .................................................................................................... 133

µ

6.2.4 Port 2 (

6.2.5 Port 3............................................................................................................................................ 137

6.2.6 Port 4............................................................................................................................................ 138

6.2.7 Port 5............................................................................................................................................ 139

6.2.8 Port 6............................................................................................................................................ 140

6.2.9 Port 7............................................................................................................................................ 142

6.2.10 Port 12 .......................................................................................................................................... 144

6.2.11 Port 13.......................................................................................................................................... 145

PD78058FY Subseries).................................................................................................. 135

6.3 Port Function Control Registers .......................................................................................... 146

6.4 Port Function Operations...................................................................................................... 152

6.4.1 Writing to input/output port ........................................................................................................... 152

6.4.2 Reading from input/output port..................................................................................................... 152

6.4.3 Operations on input/output port.................................................................................................... 153

6.5 Selection of Mask Option ...................................................................................................... 153

CHAPTER 7 CLOCK GENERATOR ..................................................................................................... 155

7.1 Clock Generator Functions ................................................................................................... 155

7.2 Clock Generator Configuration ............................................................................................ 155

7.3 Clock Generator Control Register ........................................................................................ 157

7.4 System Clock Oscillator ........................................................................................................ 161

7.4.1 Main system clock oscillator......................................................................................................... 161

17

7.4.2 Subsystem clock oscillator ........................................................................................................... 162

7.4.3 Scaler ........................................................................................................................................... 164

7.4.4 When no subsystem clocks are used........................................................................................... 164

7.5 Clock Generator Operations ................................................................................................. 165

7.5.1 Main system clock operations ...................................................................................................... 166

7.5.2 Subsystem clock operations ........................................................................................................ 167

7.6 Changing System Clock and CPU Clock Settings .............................................................. 167

7.6.1 Time required for switchover between system clock and CPU clock ........................................... 167

7.6.2 System clock and CPU clock switching procedure ...................................................................... 169

CHAPTER 8 16-BIT TIMER/EVENT COUNTER................................................................................... 171

8.1 Overview of the µPD78058F and 78058FY Subseries On-Chip Timers............................. 171

8.2 16-Bit Timer/Event Counter Functions ................................................................................ 173

8.3 16-Bit Timer/Event Counter Configuration .......................................................................... 174

8.4 16-Bit Timer/Event Counter Control Registers ................................................................... 178

8.5 16-Bit Timer/Event Counter Operations............................................................................... 187

8.5.1 Interval timer operations............................................................................................................... 187

8.5.2 PWM output operations................................................................................................................ 189

8.5.3 PPG output operation................................................................................................................... 192

8.5.4 Pulse width measurement operations .......................................................................................... 193

8.5.5 External event counter operation ................................................................................................. 200

8.5.6 Square-wave output operation ..................................................................................................... 202

8.5.7 One-shot pulse output operation .................................................................................................. 204

8.6 16-Bit Timer/Event Counter Operating Precautions ........................................................... 208

CHAPTER 9 8-BIT TIMER/EVENT COUNTERS .................................................................................. 211

9.1 8-Bit Timer/Event Counter Function .................................................................................... 211

9.1.1 8-bit timer/event counter mode .................................................................................................... 211

9.1.2 16-bit timer/event counter mode .................................................................................................. 214

9.2 8-Bit Timer/Event Counter Configuration ............................................................................ 216

9.3 8-Bit Timer/Event Counter Control Registers ..................................................................... 220

9.4 8-Bit Timer/Event Counter Operation................................................................................... 225

9.4.1 8-bit timer/event counter mode .................................................................................................... 225

9.4.2 16-bit timer/event counter mode .................................................................................................. 230

9.5 Cautions on 8-Bit Timer/Event Counters ............................................................................. 236

CHAPTER 10 WATCH TIMER .............................................................................................................. 239

10.1 Watch Timer Functions ....................................................................................................... 239

10.2 Watch Timer Configuration................................................................................................. 240

10.3 Watch Timer Control Registers .......................................................................................... 240

10.4 Watch Timer Operations ..................................................................................................... 244

10.4.1 Watch timer operation ............................................................................................................. 244

10.4.2 Interval timer operation............................................................................................................ 244

18

CHAPTER 11 WATCHDOG TIMER ...................................................................................................... 245

11.1 Watchdog Timer Functions ................................................................................................ 245

11.2 Watchdog Timer Configuration .......................................................................................... 247

11.3 Watchdog Timer Control Registers ................................................................................... 248

11.4 Watchdog Timer Operations............................................................................................... 251

11.4.1 Watchdog timer operation ....................................................................................................... 251

11.4.2 Interval timer operation ............................................................................................................ 252

CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT......................................................................... 253

12.1 Clock Output Control Circuit Functions............................................................................ 253

12.2 Clock Output Control Circuit Configuration ..................................................................... 254

12.3 Clock Output Function Control Registers......................................................................... 254

CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................... 257

13.1 Buzzer Output Control Circuit Functions.......................................................................... 257

13.2 Buzzer Output Control Circuit Configuration ................................................................... 257

13.3 Buzzer Output Function Control Registers....................................................................... 258

CHAPTER 14 A/D CONVERTER .......................................................................................................... 261

14.1 A/D Converter Functions .................................................................................................... 261

14.2 A/D Converter Configuration .............................................................................................. 262

14.3 A/D Converter Control Registers ....................................................................................... 265

14.4 A/D Converter Operations................................................................................................... 269

14.4.1 Basic operations of A/D converter ........................................................................................... 269

14.4.2 Input voltage and conversion results ....................................................................................... 271

14.4.3 A/D converter operating mode ................................................................................................ 272

14.5 A/D Converter Cautions ...................................................................................................... 274

CHAPTER 15 D/A CONVERTER .......................................................................................................... 279

15.1 D/A Converter Functions .................................................................................................... 279

15.2 D/A Converter Configuration .............................................................................................. 280

15.3 D/A Converter Control Registers ....................................................................................... 282

15.4 Operations of D/A Converter .............................................................................................. 283

15.5 Cautions Related to D/A Converter.................................................................................... 284

CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES)................................... 285

16.1 Serial Interface Channel 0 Functions................................................................................. 286

16.2 Serial Interface Channel 0 Configuration .......................................................................... 288

16.3 Serial Interface Channel 0 Control Registers.................................................................... 292

16.4 Serial Interface Channel 0 Operations............................................................................... 299

16.4.1 Operation stop mode ............................................................................................................... 299

16.4.2 3-wire serial I/O mode operation ............................................................................................. 300

19

16.4.3 SBI mode operation.................................................................................................................305

16.4.4 2-wire serial I/O mode operation.............................................................................................331

16.4.5 SCK0/P27 pin output manipulation.........................................................................................336

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES).................................337

17.1 Serial Interface Channel 0 Functions.................................................................................338

17.2 Serial Interface Channel 0 Configuration..........................................................................340

17.3 Serial Interface Channel 0 Control Registers....................................................................345

17.4 Serial Interface Channel 0 Operations...............................................................................353

17.4.1 Operation stop mode...............................................................................................................353

17.4.2 3-wire serial I/O mode operation.............................................................................................354

17.4.3 2-wire serial I/O mode operation.............................................................................................358

2

17.4.4 I

17.4.5 Cautions on use of I

17.4.6 Restrictions in I2C bus mode...................................................................................................383

17.4.7 SCK0/SCL/P27 pin output manipulation.................................................................................385

C bus mode operation...........................................................................................................363

2

C bus mode............................................................................................380

CHAPTER 18 SERIAL INTERFACE CHANNEL 1...............................................................................387

18.1 Serial Interface Channel 1 Functions.................................................................................387

18.2 Serial Interface Channel 1 Configuration..........................................................................388

18.3 Serial Interface Channel 1 Control Registers....................................................................391

18.4 Serial Interface Channel 1 Operations...............................................................................399

18.4.1 Operation stop mode...............................................................................................................399

18.4.2 3-wire serial I/O mode operation.............................................................................................400

18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function.............................403

CHAPTER 19 SERIAL INTERFACE CHANNEL 2...............................................................................433

19.1 Serial Interface Channel 2 Functions.................................................................................433

19.2 Serial Interface Channel 2 Configuration..........................................................................434

19.3 Serial Interface Channel 2 Control Registers....................................................................438

19.4 Serial Interface Channel 2 Operation.................................................................................446

19.4.1 Operation stop mode...............................................................................................................446

19.4.2 Asynchronous serial interface (UART) mode..........................................................................448

19.4.3 3-wire serial I/O mode.............................................................................................................461

19.4.4 Restrictions on using UART mode..........................................................................................468

CHAPTER 20 REAL-TIME OUTPUT PORT.........................................................................................471

20.1 Real-Time Output Port Functions......................................................................................471

20.2 Real-Time Output Port Configuration................................................................................472

20.3 Real-Time Output Port Control Registers.........................................................................474

CHAPTER 21 INTERRUPT AND TEST FUNCTIONS..........................................................................477

21.1 Interrupt Function Types....................................................................................................477

20

21.2 Interrupt Sources and Configuration................................................................................. 478

21.3 Interrupt Function Control Registers................................................................................. 482

21.4 Interrupt Servicing Operations........................................................................................... 491

21.4.1 Non-maskable interrupt acknowledge operation ..................................................................... 491

21.4.2 Maskable Interrupt request reception ...................................................................................... 494

21.4.3 Software interrupt request acknowledge operation ................................................................. 497

21.4.4 Multiple interrupt servicing....................................................................................................... 497

21.4.5 Interrupt request reserve ......................................................................................................... 501

21.5 Test Functions ..................................................................................................................... 502

21.5.1 Registers controlling the test function ..................................................................................... 502

21.5.2 Test input signal acknowledge operation................................................................................. 504

CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ............................................................ 505

22.1 External Device Expansion Functions............................................................................... 505

22.2 External Device Expansion Function Control Register ................................................... 508

22.3 External Device Expansion Function Timing.................................................................... 510

CHAPTER 23 STANDBY FUNCTION................................................................................................... 515

23.1 Standby Function and Configuration ................................................................................ 515

23.1.1 Standby function...................................................................................................................... 515

23.1.2 Standby function control register ............................................................................................. 516

23.2 Standby Function Operations ............................................................................................ 517

23.2.1 HALT mode.............................................................................................................................. 517

23.2.2 STOP mode............................................................................................................................. 520

CHAPTER 24 RESET FUNCTION ........................................................................................................ 523

24.1 Reset Function..................................................................................................................... 523

CHAPTER 25 ROM CORRECTION ...................................................................................................... 527

25.1 ROM Correction Functions ................................................................................................. 527

25.2 ROM Correction Configuration........................................................................................... 527

25.3 ROM Correction Control Registers .................................................................................... 529

25.4 ROM Correction Application............................................................................................... 530

25.5 ROM Correction Example ................................................................................................... 533

25.6 Program Execution Flow..................................................................................................... 534

25.7 Cautions on ROM Correction ............................................................................................. 536

CHAPTER 26 µPD78P058F, 78P058FY ............................................................................................... 537

26.1 Memory Size Switching Register ....................................................................................... 538

26.2 Internal Expansion RAM Size Switching Register............................................................ 539

26.3 PROM Programming............................................................................................................ 540

26.3.1 Operating modes ..................................................................................................................... 540

26.3.2 PROM write procedure ............................................................................................................ 542

21

26.3.3 PROM read procedure............................................................................................................546

26.4 Screening of One-Time PROM Versions...........................................................................547

CHAPTER 27 INSTRUCTION SET.......................................................................................................549

27.1 Legends Used in Operation List.........................................................................................550

27.1.1 Operand identifiers and description methods..........................................................................550

27.1.2 Description of “operation” column...........................................................................................551

27.1.3 Description of “flag” column.....................................................................................................551

27.2 Operation List......................................................................................................................552

27.3 Instructions Listed by Addressing Type...........................................................................560

APPENDIX A DIFFERENCES AMONG µPD78054, 78058F, AND 780058 SUBSERIES ................... 565

APPENDIX B DEVELOPMENT TOOLS...............................................................................................567

B.1Language Processing Software...........................................................................................570

B.2PROM Programming Tool.....................................................................................................571

B.2.1 Hardware......................................................................................................................................571

B.2.2 Software.......................................................................................................................................571

B.3Debugging Tool......................................................................................................................572

B.3.1 Hardware......................................................................................................................................572

B.3.2 Software.......................................................................................................................................574

B.4OS for IBM PC........................................................................................................................576

B.5Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A.......................576

APPENDIX C EMBEDDED SOFTWARE..............................................................................................581

C.1Real-time OS...........................................................................................................................582

APPENDIX D REGISTER INDEX..........................................................................................................585

D.1Register Index........................................................................................................................585

APPENDIX E REVISION HISTORY......................................................................................................591

22

LIST OF FIGURES (1/8)

Figure No. Title Page

3-1 List of Pin Input/Output Circuit .......................................................................................................... 75

4-1 List of Pin Input/Output Circuit .......................................................................................................... 93

µ

5-1 Memory Map (

5-2 Memory Map (µPD78058F, 78058FY) .............................................................................................. 96

5-3 Memory Map (

5-4 Data Memory Addressing (µPD78056F, 78056FY)........................................................................... 100

5-5 Data Memory Addressing (µPD78058F, 78058FY)........................................................................... 101

5-6 Data Memory Addressing (

5-7 Program Counter Format .................................................................................................................. 103

5-8 Program Status Word Format ........................................................................................................... 103

5-9 Stack Pointer Format ........................................................................................................................ 105

5-10 Data to Be Saved to Stack Memory.................................................................................................. 105

5-11 Data to Be Reset from Stack Memory .............................................................................................. 105

5-12 General Register Configuration ........................................................................................................ 107

PD78056F, 78056FY) .............................................................................................. 95

µ

PD78P058F, µPD78P058FY) .................................................................................. 97

µ

PD78P058F, 78P058FY)...................................................................... 102

6-1 Port Types......................................................................................................................................... 125

6-2 P00 and P07 Block Diagram............................................................................................................. 131

6-3 P01 to P06 Block Diagram................................................................................................................ 131

6-4 P10 to P17 Block Diagram................................................................................................................ 132

6-5 P20, P21, P23 to P26 Block Diagram ............................................................................................... 133

6-6 P22 and P27 Block Diagram............................................................................................................. 134

6-7 P20, P21, P23 to P26 Block Diagram ............................................................................................... 135

6-8 P22 and P27 Block Diagram............................................................................................................. 136

6-9 P30 to P37 Block Diagram................................................................................................................ 137

6-10 P40 to P47 Block Diagram................................................................................................................ 138

6-11 Block Diagram of Falling Edge Detection Circuit .............................................................................. 138

6-12 P50 to P57 Block Diagram................................................................................................................ 139

6-13 P60 to P63 Block Diagram................................................................................................................ 141

6-14 P64 to P67 Block Diagram................................................................................................................ 141

6-15 P70 Block Diagram ........................................................................................................................... 142

6-16 P71 and P72 Block Diagram............................................................................................................. 143

6-17 P120 to P127 Block Diagram............................................................................................................ 144

6-18 P130 and P131 Block Diagram......................................................................................................... 145

6-19 Port Mode Register Format .............................................................................................................. 148

6-20 Pull-Up Resistor Option Register Format ......................................................................................... 149

6-21 Memory Expansion Mode Register Format ...................................................................................... 150

6-22 Key Return Mode Register Format ................................................................................................... 151

7-1 Block Diagram of Clock Generator ................................................................................................... 156

7-2 Subsystem Clock Feedback Resistor ............................................................................................... 157

7-3 Processor Clock Control Register Format ........................................................................................ 158

23

LIST OF FIGURES (2/8)

Figure No. Title Page

7-4 Oscillation Mode Selection Register Format..................................................................................... 159

7-5 Main System Clock Waveform due to Writing to OSMS ................................................................... 160

7-6 External Circuit of Main System Clock Oscillator.............................................................................. 161

7-7 External Circuit of Subsystem Clock Oscillator................................................................................. 162

7-8 Examples of Resonator with Incorrect Connection ........................................................................... 162

7-9 Main System Clock Stop Function .................................................................................................... 166

7-10 System Clock and CPU Clock Switching.......................................................................................... 169

8-1 16-Bit Timer/Event Counter Block Diagram ...................................................................................... 175

8-2 16-Bit Timer/Event Counter Output Control Circuit Block Diagram .................................................. 176

8-3 Timer Clock Selection Register 0 Format ......................................................................................... 179

8-4 16-Bit Timer Mode Control Register Format ..................................................................................... 181

8-5 Capture/Compare Control Register 0 Format ................................................................................... 182

8-6 16-Bit Timer Output Control Register Format ................................................................................... 183

8-7 Port Mode Register 3 Format ........................................................................................................... 184

8-8 External Interrupt Mode Register 0 Format ...................................................................................... 185

8-9 Sampling Clock Select Register Format ........................................................................................... 186

8-10 Control Register Settings for Interval Timer Operation ..................................................................... 187

8-11 Interval Timer Configuration Diagram ............................................................................................... 188

8-12 Interval T imer Operation Timings...................................................................................................... 188

8-13 Control Register Settings for PWM Output Operation ...................................................................... 190

8-14 Example of D/A Converter Configuration with PWM Output............................................................. 191

8-15 TV Tuner Application Circuit Example .............................................................................................. 191

8-16 Control Register Settings for PPG Output Operation ....................................................................... 192

8-17 Control Register Settings for Pulse Width Measurement with Free-Running Counter and

One Capture Register ....................................................................................................................... 193

8-18 Configuration Diagram for Pulse Width Measurement by Free-Running Counter............................ 194

8-19 Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture

Register (with Both Edges Specified) ............................................................................................... 194

8-20 Control Register Settings for Two Pulse Width Measurements with Free-Running Counter ............ 195

8-21 Timing of Pulse Width Measurement Operation with Free-Running Counter

(with Both Edges Specified).............................................................................................................. 196

8-22 Control Register Settings for Pulse Width Measurement with Free-Running Counter and

Two Capture Registers ..................................................................................................................... 197

8-23 Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture

Registers (with Rising Edge Specified)............................................................................................. 198

8-24 Control Register Settings for Pulse Width Measurement by Means of Restart ................................ 199

8-25 Timing of Pulse Width Measurement Operation by Means of Restart

(with Rising Edge Specified) ............................................................................................................. 199

8-26 Control Register Settings in External Event Counter Mode.............................................................. 200

8-27 External Event Counter Configuration Diagram................................................................................ 201

8-28 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 201

8-29 Control Register Settings in Square-Wave Output Mode ................................................................. 202

8-30 Square-Wave Output Operation Timing............................................................................................ 203

24

LIST OF FIGURES (3/8)

Figure No. Title Page

8-31 Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ................ 204

8-32 Timing of One-Shot Pulse Output Operation Using Software Trigger............................................... 205

8-33 Control Register Settings for One-Shot Pulse Output Operation Using External Trigger ................. 206

8-34 Timing of One-Shot Pulse Output Operation Using External Trigger (with Rising Edge Specified).. 207

8-35 16-Bit Timer Register Start Timing.................................................................................................... 208

8-36 Timings After Change of Compare Register during Timer Count Operation..................................... 208

8-37 Capture Register Data Retention Timing .......................................................................................... 209

8-38 Operation Timing of OVF0 Flag ........................................................................................................ 210

9-1 8-Bit Timer/Event Counter Block Diagram ........................................................................................ 217

9-2 Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 ............................................. 218

9-3 Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 ............................................. 218

9-4 Timer Clock Select Register 1 Format .............................................................................................. 221

9-5 8-Bit Timer Mode Control Register Format ....................................................................................... 222

9-6 8-Bit Timer Output Control Register Format ..................................................................................... 223

9-7 Port Mode Register 3 Format ........................................................................................................... 224

9-8 Interval Timer Operation Timings...................................................................................................... 225

9-9 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 228

9-10 Square-Wave Output Operation Timing............................................................................................ 230

9-11 Interval T imer Operation Timing........................................................................................................ 231

9-12 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 233

9-13 Square-Wave Output Operation Timing............................................................................................ 235

9-14 8-Bit Timer Registers Start Timing .................................................................................................... 236

9-15 Event Counter Operation Timing ...................................................................................................... 236

9-16 Timing After Compare Register Change During Timer Count Operation.......................................... 237

10-1 Watch Timer Block Diagram ............................................................................................................. 241

10-2 Timer Clock Select Register 2 Format .............................................................................................. 242

10-3 Watch Timer Mode Control Register Format .................................................................................... 243

11-1 Watchdog Timer Block Diagram ....................................................................................................... 247

11-2 Timer Clock Select Register 2 Format .............................................................................................. 249

11-3 Watchdog Timer Mode Register Format........................................................................................... 250

12-1 Remote Controlled Output Application Example............................................................................... 253

12-2 Clock Output Control Circuit Block Diagram..................................................................................... 254

12-3 Timer Clock Select Register 0 Format .............................................................................................. 255

12-4 Port Mode Register 3 Format ........................................................................................................... 256

13-1 Buzzer Output Control Circuit Block Diagram................................................................................... 257

13-2 Timer Clock Select Register 2 Format .............................................................................................. 259

13-3 Port Mode Register 3 Format ........................................................................................................... 260

25

LIST OF FIGURES (4/8)

Figure No. Title Page

14-1 A/D Converter Block Diagram........................................................................................................... 263

14-2 A/D Converter Mode Register Format .............................................................................................. 266

14-3 A/D Converter Input Select Register Format .................................................................................... 267

14-4 External Interrupt Mode Register 1 Format ...................................................................................... 268

14-5 A/D Converter Basic Operation ........................................................................................................ 270

14-6 Relationship Between Analog Input Voltage and A/D Conversion Result......................................... 271

14-7 A/D Conversion by Hardware Start................................................................................................... 272

14-8 A/D Conversion by Software Start .................................................................................................... 273

14-9 Example of Method of Reducing Current Consumption in Standby Mode ....................................... 274

14-10 Connection of Analog Input Pin ........................................................................................................ 275

14-11 A/D Conversion End Interrupt Request Generation Timing .............................................................. 276

14-12 Connection of AV

15-1 D/A Converter Block Diagram........................................................................................................... 280

15-2 D/A Converter Mode Register Format .............................................................................................. 282

15-3 Use Example of Buffer Amplifier ....................................................................................................... 284

DD Pin..................................................................................................................... 277

16-1 Serial Bus Interface (SBI) System Configuration Example............................................................... 287

16-2 Serial Interface Channel 0 Block Diagram........................................................................................ 289

16-3 Timer Clock Select Register 3 Format .............................................................................................. 293

16-4 Serial Operating Mode Register 0 Format ........................................................................................ 294

16-5 Serial Bus Interface Control Register Format ................................................................................... 296

16-6 Interrupt Timing Specify Register Format ......................................................................................... 298

16-7 3-Wire Serial I/O Mode Timings........................................................................................................ 303

16-8 RELT and CMDT Operations ............................................................................................................ 303

16-9 Circuit of Switching in Transfer Bit Order.......................................................................................... 304

16-10 Example of Serial Bus Configuration with SBI .................................................................................. 305

16-1 1 SBI Transfer Timings ........................................................................................................................ 307

16-12 Bus Release Signal .......................................................................................................................... 308

16-13 Command Signal .............................................................................................................................. 308

16-14 Addresses ......................................................................................................................................... 309

16-15 Slave Selection with Address............................................................................................................ 309

16-16 Commands........................................................................................................................................ 310

16-17 Data .................................................................................................................................................. 310

16-18 Acknowledge Signal ......................................................................................................................... 311

16-19 BUSY and READY Signals ............................................................................................................... 312

16-20 RELT, CMDT, RELD, and CMDD Operations (Master)..................................................................... 317

16-21 RELT and CMDD Operations (Slave) ............................................................................................... 317

16-22 ACKT Operation................................................................................................................................ 318

16-23 ACKE Operations ............................................................................................................................. 319

16-24 ACKD Operations ............................................................................................................................. 320

16-25 BSYE Operation ............................................................................................................................... 320

16-26 Pin Configuration .............................................................................................................................. 323

26

LIST OF FIGURES (5/8)

Figure No. Title Page

16-27 Address Transmission from Master Device to Slave Device (WUP = 1) .......................................... 325

16-28 Command Transmission from Master Device to Slave Device ......................................................... 326

16-29 Data Transmission from Master Device to Slave Device.................................................................. 327

16-30 Data Transmission from Slave Device to Master Device.................................................................. 328

16-31 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode .................................................... 331

16-32 2-Wire Serial I/O Mode Timings ........................................................................................................ 334

16-33 RELT and CMDT Operations ............................................................................................................ 335

16-34 SCK0/P27 Pin Configuration ............................................................................................................ 336

2

17-1 Serial Bus Configuration Example Using I

17-2 Serial Interface Channel 0 Block Diagram........................................................................................ 341

17-3 Timer Clock Select Register 3 Format .............................................................................................. 346

17-4 Serial Operating Mode Register 0 Format ........................................................................................ 348

17-5 Serial Bus Interface Control Register Format ................................................................................... 349

17-6 Interrupt Timing Specify Register Format ......................................................................................... 351

17-7 3-Wire Serial I/O Mode Timings........................................................................................................ 356

17-8 RELT and CMDT Operations ............................................................................................................ 356

17-9 Circuit of Switching in Transfer Bit Order.......................................................................................... 357

17-10 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode .................................................... 358

17-11 2-Wire Serial I/O Mode Timings........................................................................................................ 361

17-12 RELT and CMDT Operations ............................................................................................................ 362

17-13 Example of Serial Bus Configuration Using I

17-14 I2C Bus Serial Data Transfer Timing ................................................................................................. 364

17-15 Start Condition .................................................................................................................................. 365

17-16 Address ............................................................................................................................................. 365

17-17 Transfer Direction Specification ........................................................................................................ 365

17-18 Acknowledge Signal ......................................................................................................................... 366

17-19 Stop Condition .................................................................................................................................. 366

17-20 Wait Signal ........................................................................................................................................ 367

17-21 Pin Configuration .............................................................................................................................. 372

17-22 Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)............. 374

17-23 Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)............. 377

17-24 Start Condition Output ...................................................................................................................... 380

17-25 Slave Wait Release (Transmission) .................................................................................................. 381

17-26 Slave Wait Release (Reception) ....................................................................................................... 382

17-27 SCK0/SCL/P27 Pin Configuration .................................................................................................... 385

17-28 SCK0/SCL/P27 Pin Configuration .................................................................................................... 385

17-29 Logic Circuit of SCL Signal ............................................................................................................... 386

C Bus............................................................................. 339

2

C Bus......................................................................... 363

18-1 Serial Interface Channel 1 Block Diagram........................................................................................ 389

18-2 Timer Clock Select Register 3 Format .............................................................................................. 392

18-3 Serial Operating Mode Register 1 Format ........................................................................................ 393

18-4 Automatic Data Transmit/Receive Control Register Format ............................................................. 394

27

LIST OF FIGURES (6/8)

Figure No. Title Page

18-5 Automatic Data Transmit/Receive Interval Specify Register Format ................................................ 395

18-6 3-Wire Serial I/O Mode Timings........................................................................................................ 401

18-7 Circuit of Switching in Transfer Bit Order.......................................................................................... 402

18-8 Basic Transmission/Reception Mode Operation Timings ................................................................. 411

18-9 Basic Transmission/Reception Mode Flowchart ............................................................................... 412

18-10 Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive

Mode)................................................................................................................................................ 413

18-11 Basic Transmission Mode Operation Timings................................................................................... 415

18-12 Basic Transmission Mode Flowchart ................................................................................................ 416

18-13 Internal Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ........................... 417

18-14 Repeat Transmission Mode Operation Timing.................................................................................. 419

18-15 Repeat Transmission Mode Flowchart ............................................................................................. 420

18-16 Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode)......................... 421

18-17 Automatic Transmission/Reception Suspension and Restart ........................................................... 423

18-18 System Configuration When the Busy Control Option Is Used ......................................................... 424

18-19 Operation Timings When Using Busy Control Option (BUSY0 = 0).................................................. 425

18-20 Busy Signal and Wait Cancel (When BUSY0 = 0) ............................................................................ 426

18-21 Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0)................................... 427

18-22 Operation Timing of the Bit Slippage Detection Function Through the Busy Signal

(When BUSY0 = 1) ........................................................................................................................... 428

18-23 Automatic Transmit/Receive Interval Time ....................................................................................... 429

18-24 Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock .... 430

19-1 Serial Interface Channel 2 Block Diagram........................................................................................ 435

19-2 Baud Rate Generator Block Diagram ............................................................................................... 436

19-3 Serial Operating Mode Register 2 Format ........................................................................................ 438

19-4 Asynchronous Serial Interface Mode Register Format ..................................................................... 439

19-5 Asynchronous Serial Interface Status Register Format.................................................................... 441

19-6 Baud Rate Generator Control Register Format ................................................................................ 442

19-7 Asynchronous Serial Interface Transmit/Receive Data Format ........................................................ 455

19-8 Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing ..... 457

19-9 Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing .......... 458

19-10 Receive Error Timing ........................................................................................................................ 459

19-11 Receive Buffer Register (RXB) Status and Receive Completion Interrupt Request (INTSR)

Generation When Receiving Is Terminated ...................................................................................... 460

19-12 3-Wire Serial I/O Mode Timing.......................................................................................................... 466

19-13 Circuit of Switching in Transfer Bit Order .......................................................................................... 467

19-14 Receive Completion Interrupt Request Generation Timing (When ISRM = 1).................................. 468

19-15 Period that Reading Receive Buffer Register Is Prohibited .............................................................. 469

20-1 Real-time Output Port Block Diagram............................................................................................... 472

20-2 Real-time Output Buffer Register Configuration ............................................................................... 473

20-3 Port Mode Register 12 Format ......................................................................................................... 474

28

LIST OF FIGURES (7/8)

Figure No. Title Page

20-4 Real-time Output Port Mode Register Format .................................................................................. 474

20-5 Real-time Output Port Control Register Format................................................................................ 475

21-1 Basic Configuration of Interrupt Function ......................................................................................... 480

21-2 Interrupt Request Flag Register Format ........................................................................................... 483

21-3 Interrupt Mask Flag Register Format ................................................................................................ 484

21-4 Priority Specify Flag Register Format ............................................................................................... 485

21-5 External Interrupt Mode Register 0 Format ...................................................................................... 486

21-6 External Interrupt Mode Register 1 Format ...................................................................................... 487

21-7 Sampling Clock Select Register Format ........................................................................................... 488

21-8 Noise Elimination Circuit Input/Output Timing (During Rising Edge Detection)................................ 489

21-9 Program Status Word Format........................................................................................................... 490

21-10 Flowchart from the Time a Non-maskable Interrupt Request Is Generated Until It Is Received ...... 492

21-11 Non-Maskable Interrupt Request Acknowledge Timing .................................................................... 492

21-12 Non-Maskable Interrupt Request Acknowledge Operation ............................................................... 493

21-13 Interrupt Request Acknowledge Processing Algorithm ..................................................................... 495

21-14 Interrupt Request Acknowledge Timing (Minimum Time) ................................................................. 496

21-15 Interrupt Request Acknowledge Timing (Maximum Time) ................................................................ 496

21-16 Multiple Interrupt Example ................................................................................................................ 499

21-17 Interrupt Request Hold ...................................................................................................................... 501

21-18 Basic Configuration of Test Function ................................................................................................ 502

21-19 Format of Interrupt Request Flag Register 1L .................................................................................. 503

21-20 Format of Interrupt Mask Flag Register 1L ....................................................................................... 503

21-21 Key Return Mode Register Format ................................................................................................... 504

22-1 Memory Map When Using External Device Expansion Function ..................................................... 506

22-2 Memory Expansion Mode Register Format ...................................................................................... 508

22-3 Memory Size Switching Register Format.......................................................................................... 509

22-4 Instruction Fetch from External Memory........................................................................................... 511

22-5 External Memory Read Timing ......................................................................................................... 512

22-6 External Memory Write Timing.......................................................................................................... 513

22-7 External Memory Read Modify Write Timing..................................................................................... 514

23-1 Oscillation Stabilization Time Select Register Format ...................................................................... 516

23-2 HALT Mode Clear upon Interrupt Request Generation ..................................................................... 518

23-3 HALT Mode Release by RESET Input .............................................................................................. 519

23-4 STOP Mode Release by Interrupt Request Generation.................................................................... 521

23-5 Release by STOP Mode RESET Input ............................................................................................. 522

24-1 Block Diagram of Reset Function ..................................................................................................... 523

24-2 Timing of Reset Input by RESET Input ............................................................................................. 524

24-3 Timing of Reset due to Watchdog Timer Overflow............................................................................ 524

24-4 Timing of Reset Input in STOP Mode by RESET Input..................................................................... 524

29

LIST OF FIGURES (8/8)

Figure No. Title Page

25-1 Block Diagram of ROM Correction ................................................................................................... 527

25-2 Correction Address Registers 0 and 1 Format.................................................................................. 528

25-3 Correction Control Register Format.................................................................................................. 529

25-4 Storing Example to EEPROM (When One Place Is Corrected)........................................................ 530

25-5 Connecting Example with EEPROM (Using 2-Wire Serial I/O Mode) .............................................. 530

25-6 Initialization Routine.......................................................................................................................... 531

25-7 ROM Correction Operation ............................................................................................................... 532

25-8 ROM Correction Example................................................................................................................. 533

25-9 Program Transition Diagram (When One Place Is Corrected).......................................................... 534

25-10 Program Transition Diagram (When Two Places Are Corrected)...................................................... 535

26-1 Memory Size Switching Register Format.......................................................................................... 538

26-2 Internal Expansion RAM Size Switching Register Format................................................................ 539

26-3 Page Program Mode Flowchart ........................................................................................................ 542

26-4 Page Program Mode Timing ............................................................................................................. 543

26-5 Byte Program Mode Flowchart ......................................................................................................... 544

26-6 Byte Program Mode Timing .............................................................................................................. 545

26-7 PROM Read Timing.......................................................................................................................... 546

B-1 Development Tool Configuration....................................................................................................... 568

B-2 EV-9200GC-80 Drawings (For Reference Only)............................................................................... 577

B-3 EV-9200GC-80 Footprints (For Reference Only).............................................................................. 578

B-4 TGK-080SDW Drawings (For Reference) (unit: mm) ....................................................................... 579

30

LIST OF TABLES (1/3)

Table No. Title Page

1-1 Differences Between the µPD78058F and µPD78058F(A) .............................................................. 45

1-2 Mask Options of Mask POM Versions .............................................................................................. 46

µ

2-1 Differences Between the

2-2 Mask Options of Mask ROM Versions .............................................................................................. 58

3-1 Pin Input/Output Circuit Types .......................................................................................................... 73

4-1 Pin Input/Output Circuit Types .......................................................................................................... 91

5-1 Vector Table ...................................................................................................................................... 98

5-2 Corresponding of General Register Absolute Address ..................................................................... 106

5-3 Special-Function Register List .......................................................................................................... 109

µ

6-1 Port Functions (

6-2 Port Functions (µPD78058FY Subseries)......................................................................................... 128

6-3 Port Configuration ............................................................................................................................. 130

6-4 Pull-up Resistor of Port 6 .................................................................................................................. 140

6-5 Port Mode Register and Output Latch Settings When Using Alternate Functions............................ 147

6-6 Comparison Between Mask ROM Version and PROM Version........................................................ 153

PD78058F Subseries) ........................................................................................... 126

PD78058FY and µPD78058FY(A).......................................................... 57

7-1 Clock Generator Configuration ......................................................................................................... 155

7-2 Relationship Between CPU Clock and Minimum Instruction Execution Time................................... 159

7-3 Maximum Time Required for CPU Clock Switchover ....................................................................... 168

8-1 Timer/Event Counter Operation ........................................................................................................ 172

8-2 16-Bit Timer/Event Counter Interval Times ....................................................................................... 173

8-3 16-Bit Timer/Event Counter Square-Wave Output Ranges .............................................................. 174

8-4 16-Bit Timer/Event Counter Configuration ........................................................................................ 174

8-5 INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge.................................................. 177

8-6 16-Bit Timer/Event Counter Interval Times ....................................................................................... 189

8-7 16-Bit Timer/Event Count Square-Wave Output Ranges.................................................................. 203

9-1 8-Bit Timer/Event Counter Interval Times ......................................................................................... 212

9-2 8-Bit Timer/Event Counter Square-Wave Output Ranges ................................................................ 213

9-3 Interval Times When 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter ............ 214

9-4 Square-Wave Output Ranges When 8-Bit Timer/Event Counters are Used as

16-Bit Timer/Event Counter .............................................................................................................. 215

9-5 8-Bit Timer/Event Counter Configuration .......................................................................................... 216

9-6 8-Bit Timer/Event Counter 1 Interval Time........................................................................................ 226

9-7 8-Bit Timer/Event Counter 2 Interval Time........................................................................................ 227

9-8 8-Bit Timer/Event Counter Square-Wave Output Ranges ................................................................ 229

9-9 Interval Times When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used

as 16-Bit Timer/Event Counter.......................................................................................................... 232

31

LIST OF TABLES (2/3)

Table No. Title Page

9-10 Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters

(TM1 and TM2) are Used as 16-Bit Timer/Event Counter ................................................................ 234

10-1 Interval T imer Interval Time .............................................................................................................. 239

10-2 W atch Timer Configuration ............................................................................................................... 240

10-3 Interval T imer Interval Time .............................................................................................................. 244

11-1 Watchdog Timer Runaway Detection Times..................................................................................... 245

1 1-2 Interval Times.................................................................................................................................... 246

1 1-3 Watchdog Timer Configuration ......................................................................................................... 247

11-4 Watchdog Timer Runaway Detection Time....................................................................................... 251

1 1-5 Interval Timer Interval Time .............................................................................................................. 252

12-1 Clock Output Control Circuit Configuration....................................................................................... 254

13-1 Buzzer Output Control Circuit Configuration..................................................................................... 257

14-1 A/D Converter Configuration............................................................................................................. 262

15-1 D/A Converter Configuration............................................................................................................. 280

16-1 Differences Among Channels 0, 1, and 2 ......................................................................................... 285

16-2 Serial Interface Channel 0 Configuration.......................................................................................... 288

16-3 Various Signals in SBI Mode............................................................................................................. 321

17-1 Differences Among Channels 0, 1, and 2 ......................................................................................... 337

17-2 Serial Interface Channel 0 Configuration.......................................................................................... 340

17-3 Serial Interface Channel 0 Interrupt Request Signal Generation...................................................... 344

2

17-4 Signals in I

C Bus Mode ................................................................................................................... 371

18-1 Serial Interface Channel 1 Configuration.......................................................................................... 388

18-2 Interval Timing Through CPU Processing (When the Internal Clock Is Operating) .......................... 430

18-3 Interval Timing Through CPU Processing (When the External Clock Is Operating) ......................... 431

19-1 Serial Interface Channel 2 Configuration.......................................................................................... 434

19-2 Serial Interface Channel 2 Operating Mode Settings ....................................................................... 440

19-3 Relationship Between Main System Clock and Baud Rate .............................................................. 444

19-4 Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H) .... 445

19-5 Relationship Between Main System Clock and Baud Rate .............................................................. 453

19-6 Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H) .... 454

19-7 Receive Error Causes....................................................................................................................... 459

20-1 Real-time Output Port Configuration................................................................................................. 472

32

LIST OF TABLES (3/3)

Table No. Title Page

20-2 Operation in Real-time Output Buffer Register Manipulation............................................................ 473

20-3 Real-time Output Port Operating Mode and Output Trigger ............................................................. 475

21-1 Interrupt Source List ......................................................................................................................... 478

21-2 Various Flags Corresponding to Interrupt Request Sources............................................................. 482

21-3 Times from Maskable Interrupt Request Generation to Interrupt Service......................................... 494

21-4 Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing ..................................... 498

21-5 Test Input Factors ............................................................................................................................. 502

21-6 Flags Corresponding to Test Input Signals ....................................................................................... 502

22-1 Pin Functions in External Memory Expansion Mode ........................................................................ 505

22-2 State of Ports 4 to 6 Pins in External Memory Expansion Mode ...................................................... 505

22-3 Values When the Memory Size Switching Register Is Reset............................................................ 509

23-1 HALT Mode Operating Status ........................................................................................................... 517

23-2 Operation After HALT Mode Release................................................................................................ 519

23-3 STOP Mode Operating Status .......................................................................................................... 520

23-4 Operation After STOP Mode Release............................................................................................... 522

24-1 Hardware Status After Reset ............................................................................................................ 525

25-1 ROM Correction Configuration ......................................................................................................... 527

µ

26-1 Differences Between

26-2 Examples of Memory Size Switching Register Settings ................................................................... 538

26-3 Value Set to the Internal Expansion RAM Size Switching Register.................................................. 539

26-4 PROM Programming Operating Modes............................................................................................ 540

27-1 Operand Identifiers and Description Methods .................................................................................. 550

A-1 Major Differences Among

B-1 OS for IBM PC .................................................................................................................................. 576

B-2 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A ....................................... 576

PD78P058F, 78P058FY and Mask ROM Versions....................................... 537

µ

PD78054, 78058F, and 780058 Subseries............................................ 565

33

[MEMO]

34

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

1.1 Features

Compared to the conventional µPD78054 Subseries, EMI (Electro Magnetic Interference) noise has been
reduced.
On-chip high-capacity ROM and RAM

Part Number

µ

PD78056F

µ

PD78058F

µ

PD78P058F

Item

Program Memory

(ROM)

48 Kbytes
60 Kbytes
60 Kbytes

Note 1

Internal High-Speed RAM Internal Buffer RAM Internal Expansion RAM

1024 bytes 32 bytes None

1024 bytes

Note 1

Data Memory

1024 bytes

1024 bytes

Note 2

Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the

memory size switching register (IMS).

2. The capacity of internal expansion RAM can be changed by means of the internal expansion RAM
size switching register (IXS).

External Memory Expansion Space: 64 Kbytes
Minimum instruction execution time changeable from high speed (0.4 µs: In main system clock 5.0 MHz operation)
to ultra-low speed (122 µs: In subsystem clock 32.768-kHz operation)
Instruction set suited to system control

• Bit manipulation possible in all address spaces

• Multiply and divide instructions
69 I/O ports: (4 N-ch open-drain ports)
8-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
Serial interface: 3 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel

• 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel

• 3-wire serial I/O/UART mode: 1 channel
Timer: 5 channels

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel
22 vectored interrupt sources
Two test inputs
Two types of on-chip clock oscillators (main system clock and subsystem clock)
Supply voltage: VDD = 2.7 to 6.0 V

35

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

1.2 Applications

In the case of the µPD78056F, 78058F and 78P058F,

Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPC’s, fuzzy home appliances,

vending machines, etc.

µ

In the case of the

PD78058F (A),

Controllers for car electronics, gas detection and shut-off devices, various safety devices, etc.

1.3 Ordering Information

Part Number Package Internal ROM

µ

PD78056FGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

µ

PD78056FGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78058FGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

µ

PD78058FGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78058FGK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Mask ROM

µ

PD78058FGC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

µ

PD78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) One-time PROM

µ

PD78P058FGC-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) One-time PROM

Remark ××× indicates ROM code suffix.

36

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

1.4 Quality Grade

Part Number Package Quality Grade

µ

PD78056FGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard

µ

PD78056FGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78058FGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard

µ

PD78058FGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78058FGK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard

µ

PD78058FGC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Special

µ

PD78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard

µ

PD78P058FGC-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

Remark ××× indicates ROM code suffix.

Please refer to Quality grade on NEC Semiconductor Devices (Document number C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

37

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

1.5 Pin Configuration (Top View)

(1) Normal operating mode

80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)

µ

PD78056FGC-×××-3B9, 78058FGC-×××-3B9, 78058FGC(A)-×××-3B9, 78P058FGC-3B9

80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

µ

PD78056FGC-×××-8BT, 78058FGC-×××-8BT, 78P058FGC-8BT

80-pin plastic TQFP (Fine pitch) (12 ×

µ

PD78058FGK-×××-BE9

P14/ANI4

P13/ANI3

P12/ANI2

REF0AVDD

P11/ANI1

P10/ANI0

AV

12 mm)

)

PP

XT1/P07

XT2

IC (V

X1X2V

DD

P06/INTP6

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2

P01/INTP1/TI01

P00/INTP0/TI00

P15/ANI5
P16/ANI6
P17/ANI7

AV
P130/ANO0
P131/ANO1

AV

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P25/SI0/SB0

P26/SO0/SB1

REF1

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P27/SCK0

P40/AD0
P41/AD1

SS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

SS

V

P60

P61

P50/A8

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

P62

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

P63

P64/RD

RESET
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR

Cautions 1. Be sure to connect Internally Connected (IC) pin to VSS directly.

2. The AVDD pin is used in common as the power supply for the A/D converter and port. If
this device is used in application fields where reduction of noise generated internally in
the microprocessor is required, please connect to a separate power supply with the same
electrical potential as V

DD.

3. The AVSS pin is used in common as the ground for the A/D converter, D/A converter and
port. If this device is used in application fields where reduction of noise generated
internally in the microprocessor is required, please connect it to a ground line which is
separate from V

SS.

Remark Pin connection in parentheses is intended for the

38

µ

PD78P058F.

Pin Identifications

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

A8 to A15 : Address Bus
AD0 to AD7 : Address/Data Bus
ANI0 to ANI7 : Analog Input
ANO0, ANO1 : Analog Output
ASCK : Asynchronous Serial Clock
ASTB : Address Strobe

DD : Analog Power Supply

AV
AVREF0, 1 : Analog Reference Voltage
AVSS : Analog Ground
BUSY : Busy
BUZ : Buzzer Clock
IC : Internally Connected
INTP0 to INTP6 : Interrupt from Peripherals
P00 to P07 : Port0
P10 to P17 : Port1
P20 to P27 : Port2
P30 to P37 : Port3
P40 to P47 : Port4
P50 to P57 : Port5
P60 to P67 : Port6
P70 to P72 : Port7
P120 to P127 : Port12

P130, P131 : Port13
PCL : Programmable Clock
RD : Read Strobe
RESET : Reset
RTP0 to RTP7 : Real-Time Output Port
RxD : Receive Data
SB0, SB1 : Serial Bus
SCK0 to SCK2 : Serial Clock
SI0 to SI2 : Serial Input
SO0 to SO2 : Serial Output
STB : Strobe
TI00, TI01 : Timer Input
TI1, TI2 : Timer Input
TO0 to TO2 : Timer Output
TxD : Transmit Data

DD : Power Supply

V

PP : Programming Power Supply

V
VSS : Ground
WAIT : Wait
WR : Write Strobe
X1, X2 : Crystal (Main System Clock)
XT1, XT2 : Crystal (Subsystem Clock)

39

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

(2) PROM programming mode

80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)

µ

PD78P058FGC-3B9

80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

µ

PD78P058FGC-8BT

(L)

(L)

(L)

(L)

VSS VDD (L)

Open

VPP (L)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2

V

SS

V

DD

A0
A1

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A2A3A4A5A6A7A8

A16

A10

A11

A12

A13

DD

Open

V

SS

V

A14

(L)

A15

PGM

(L)

(L)

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

A9

RESET

(L)

D7
D6
D5
D4
D3
D2
D1
D0

(L)

CE

OE

Cautions 1. (L) : Connect independently to V

SS via a pull-down resistor.

2. VSS : Connect to the ground.

3. RESET : Set to the low level.

4. Open : Do not connect anything.

A0 to A16 : Address Bus RESET : Reset
CE : Chip Enable V

DD : Power Supply

D0 to D7 : Data Bus VPP : Programming Power Supply
OE : Output Enable V

SS : Ground

PGM : Program

40

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

1.6 78K/0 Series Expansion

The 78K/0 Series expansion is shown below. The names in frames are subseries.

Products in mass production
Products under development

Y subseries products are compatible with I

Control

PD78075B

100-pin
100-pin

100-pin
100-pin
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42-/44-pin

µ

µµ

PD78078

µµ

PD78070A

PD780058

µµ

PD78058F

µµ

PD78054

µµ

µµ

PD780034

µµ

PD780024

µ

PD78014H
PD78018F

µµ

PD78014

µµ

PD780001

µ

PD78002

µ
µ

PD78083

PD78078Y

PD78070AY

µ

PD780018AY
PD780058Y
PD78058FY

PD78054Y

PD780034Y
PD780024Y

PD78018FY

PD78014Y

PD78002Y

µ

Note

EMI-noise reduced version of the PD78078
Timer was added to the PD78054 and the external interface function was enhanced
ROM-less versions of the PD78078
Serial I/O of the PD78078Y was enhanced and only selected functions are provided
Serial I/O of the PD78054 was enhanced. EMI-noise reduced version
EMI-noise reduced version of the PD78054
UART and D/A converter were added to the PD78014 and I/O was enhanced
A/D converter of the PD780024 was enhanced
Serial I/O of the PD78018F was enhanced
EMI-noise reduced version of the PD78018F
Low-voltage (1.8 V) operation versions of the PD78014 with choice of several ROM and RAM capacities

A/D converter and 16-bit timer were added to the PD78002
A/D converter was added to the PD78002
Basic subseries for control

On-chip UART, capable of operation at a low voltage (1.8 V)

µ

µ
µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

2

C bus.

64-pin
64-pin

78K/0

Series

100-pin
100-pin
80-pin

100-pin
100-pin
100-pin

80-pin
80-pin IEBus controller was added to the PD78054

Note Under planning

Inverter control

µ

PD78098864-pin
PD780964

µ

PD780924

µ

TM

FIP drive

PD780208

µ
µ

PD780228

µ

PD78044H
PD78044F80-pin Basic subseries for driving FIP. Display output total: 34

µ

LCD drive

PD780308

µµ

PD78064B

µ

µµ

PD78064

IEBus

PD78098B

µ

µ

PD78098

Meter control

PD78097380-pin

µ

TM

supported

PD780308Y

PD78064Y

The inverter control, timer, and SIO of the PD780964 were enhanced. ROM size and RAM size were expanded
A/D converter of the PD780924 was enhanced
On-chip inverter control circuit and UART. EMI-noise reduced version

I/O and FIP C/D of the PD78044F were enhanced. Display output total: 53
I/O and FIP C/D of the PD78044H were enhanced. Display output total: 48
N-ch open-drain I/O was added to the PD78044F. Display output total: 34

SIO of the PD78064 was enhanced. ROM size and RAM size were expanded
EMI-noise reduced version of the PD78064
Subseries for driving LCDs. On-chip UART

EMI-noise reduced version of the PD78098

µ

µ

µ
µ

µ

µ

µ

µ

µ

On-chip controller/driver for driving automobile meters

41

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

The differences between the major functions of each subseries are shown below.

Function

Subseries

ControlµPD78075B

µ

PD78078

µ

PD78070A — 61 2.7 V

µ

PD780058

µ

PD78058F

µ

PD78054

µ

PD780034

µ

PD780024 8 ch —

µ

PD78014H 2 ch 53

µ

PD78018F

µ

PD78014

µ

PD780001

µ

PD78002

µ

PD78083 — 8 ch 1 ch (UART: 1 ch) 33 1.8 V —

InverterµPD780988
control

FIP
drive

LCD
drive UART: 1 ch)

IEBUSµPD78098B
support

MeterµPD780973
control

µ

PD780964

µ

PD780924 8 ch —

µ

PD780208

µ

PD780228

µ

PD78044H

µ

PD78044F

µ

PD780308

µ

PD78064B

µ

PD78064

µ

PD78098

ROM

Capacity

32 K to 40 K
48 K to 60 K

24 K to 60 K

48 K to 60 K
16 K to 60 K
8 K to 32 K

8 K to 60 K
8 K to 32 K
8 K
8 K to 16 K

32 K to 60 K
8 K to 32 K Note 2

32 K to 60 K
48 K to 60 K
32 K to 48 K
16 K to 40 K
48 K to 60 K

32 K
16 K to 32 K
40 K to 60 K
32 K to 60 K

24 K to 32 K

8-bit 16-bit Watch WDT
4 ch 1 ch 1 ch 1 ch 8 ch — 2 ch 3 ch (UART: 1 ch) 88 1.8 V √

2 ch

3 ch

2 ch 1 ch 1 ch 1 ch 8 ch — — 2 ch 74 2.7 V —
3 ch — — 1 ch 72 4.5 V
2 ch 1 ch 1 ch 68 2.7 V

2 ch 1 ch 1 ch 1 ch 8 ch — — 3 ch (time-division 57 2.0 V —

2 ch 1 ch 1 ch 1 ch 8 ch — 2 ch 3 ch (UART: 1 ch) 69 2.7 V √

3 ch 1 ch 1 ch 1 ch 5 ch — — 2 ch (UART: 1 ch) 56 4.5 V —

Timer

— — 1 ch 39 —

1 ch — 53 √

Note 1

— 1 ch — 8 ch — 3 ch (UART: 2 ch) 47 4.0 V √

8-bit 10-bit 8-bit
A/D A/D D/A

—8 ch—

Serial Interface I/O

3 ch (time-division
UART: 1 ch)

3 ch (UART: 1 ch) 69 2.7 V

3 ch (UART: 1 ch, time

-division 3-wire: 1 ch)

2 ch (UART: 2 ch) 2.7 V

2 ch

2 ch (UART: 1 ch)

VDD External

MIN. value

68 1.8 V

2.0 V

51 1.8 V

2.7 V

extension

Notes 1. 16-bit timer: 2 channels

10-bit timer: 1 channel

2. 10-bit timer: 1 channel

42

1.7 Block Diagram

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

16-bit TIMER/
EVENT COUNTER

8-bit TIMER/
EVENT COUNTER 1

8-bit TIMER/
EVENT COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL
INTERFACE 0

SERIAL
INTERFACE 1

78K/0
CPU CORE

ROM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

P00
P01 to P06
P07

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P72

SI2/RxD/P70
SO2/TxD/P71
SCK2/ASCK/P72

ANI0/P10 to

ANI7/P17

AVREF0

ANO0/P130,

ANO1/P131

AV

REF1

INTP0/P00 to

INTP6/P06

BUZ/P36

PCL/P35

SERIAL
INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT
CONTROL

BUZZER OUTPUT

CLOCK OUTPUT
CONTROL

P120 to P127

P130, P131

RTP0/P120 to
RTP7/P127

RAM

PORT 12

PORT 13

REAL-TIME
OUTPUT PORT

AD0/P40 to
AD7/P47

A8/P50 to

EXTERNAL
ACCESS

A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67

RESET

SYSTEM
CONTROL

VSS

AV

DD

SS

AV

IC

(V

PP)

V

DD

X1
X2
XT1/P07
XT2

Remarks 1. The internal ROM and RAM capacities depend on the product.

2. Pin connection in parentheses is intended for the µPD78P058F.

43

1.8 Outline of Function

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

Part Number

Item

Internal
memory

Memory space 64 Kbytes
General register 8 bits × 8 × 4 banks

Minimum
instruction
execution
time

Instruction set • 16-bit operation

I/O port • Total : 69

A/D converter 8-bit resolution × 8 channels

ROM Mask ROM PROM

High-speed RAM 1024 bytes 1024 bytes
Buffer RAM 32 bytes
Expansion RAM None 1024 bytes 1024 bytes

With main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0-MHz operation)
With subsystem clock selected 122 µs (at 32.768-kHz operation)

µ

PD78056F

48 Kbytes 60 Kbytes 60 Kbytes

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc.

• CMOS input : 2

• CMOS I/O : 63

• N-ch open-drain I/O : 4

µ

PD78058F

µ

PD78P058F

Note 1

Note 1

Note 2

D/A converter 8-bit resolution × 2 channels
Serial interface • 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible : 1 channel

• 3-wire serial I/O mode (Max. 32-byte on-chip auto-transmit/receive) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

Timer • 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel
Timer output Three outputs: (14-bit PWM output enable: 1)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,

2.5 MHz, 5.0 MHz (at 5.0-MHz operation with main system clock)

32.768 kHz (at 32.768-kHz operation with subsystem clock)

Notes 1. The capacities of the internal PROM and the internal high-speed RAM can be changed using the

memory size switching register (IMS).

2. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size
switching register (IXS).

44

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

Part Number

Item

Buzzer output 1.2 kHz, 2.4 kHz, 4.9 KHz, 9.8 kHz (main system clock at 5.0-MHz

Vectored Maskable Internal: 13
interrupt External: 7
sources Non-maskable Internal: 1

Software 1

Test input Internal: 1

Supply voltage VDD = 2.7 to 6.0 V
Operating ambient temperature TA = –40 to +85 °C
Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness : 2.7 mm)

µ

PD78056F

operation)

External: 1

• 80-pin plastic QFP (14 × 14 mm, Resin thickness : 1.4 mm)

• 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) (µPD78058F only)

µ

PD78058F

µ

PD78P058F

1.9 Differences Between the µPD78058F and µPD78058F(A)

Table 1-1. Differences Between the µPD78058F and µPD78058F(A)

Part Number

Item

Quality grade Standard Special

Package • 80-pin Plastic QFP • 80-pin Plastic QFP

(14 × 14 mm, Resin thickness: 2.7 mm)

• 80-pin Plastic QFP
(14 × 14 mm, Resin thickness: 1.4 mm)

• 80-pin Plastic TQFP (Fine Pitch)

(12 × 12 mm)

µ

PD78058F

µ

PD78058F(A)

(14 × 14 mm, Resin thickness: 2.7 mm)

45

CHAPTER 1 OUTLINE (µPD78058F SUBSERIES)

1.10 Mask Options

There are mask options in the mask ROM versions (µPD78056F, 78058F). By specifying the mask option when
ordering, you can have the pull-up resistors shown in Table 1-2 incorporated on-chip. If a mask option is used when
pull-up resistors are required, the number of parts can be reduced and package area can be shrunk.

µ

The mask option provided for the

Table 1-2. Mask Options of Mask POM Versions

Pin Names Mask Options
P60 to P63 Pull-up resistors can be incorporated in 1-bit units.

PD78058F Subseries is shown in Table 1-2.

46

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

2.1 Features

Compared to the conventional µPD78054Y Subseries, EMI (Electro Magnetic Interference) noise has been
reduced.
On-chip high-capacity ROM and RAM

Part Number

µ

PD78056FY

µ

PD78058FY

µ

PD78P058FY

Item

Program Memory

(ROM)

48 Kbytes
60 Kbytes
60 Kbytes

Note 1

Internal High-Speed RAM Internal Buffer RAM Internal Expansion RAM

1024 bytes 32 bytes None

1024 bytes

Note 1

Data Memory

1024 bytes
1024 byes

Note 2

Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the

memory size switching register (IMS).

2. The capacity of internal expansion RAM can be changed by means of the internal expansion RAM
size switching register (IXS).

External Memory Expansion Space: 64 Kbytes
Minimum instruction execution time changeable from high speed (0.4 µs: In main system clock 5.0 MHz operation)
to ultra-low speed (122 µs: In subsystem clock 32.768 kHz operation)
Instruction set suited to system control

• Bit manipulation possible in all address spaces

• Multiply and divide instructions
I/O ports: 69 (N-ch open-drain ports: 4)
8-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
Serial interface: 3 channels

• 3-wire serial I/O/2-wire serial I/O/I2C bus mode: 1 channel

• 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel

• 3-wire serial I/O/UART mode: 1 channel
Timer: 5 channels

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel
22 vectored interrupts
Two test inputs
Two types of on-chip clock oscillators (main system clock and subsystem clock)
Supply voltage: VDD = 2.7 to 6.0 V

47

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

2.2 Applications

In the case of the µPD78056FY, 78058FY and 78P058FY,

Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending

machines, etc.

µ

In the case of the

PD78058FY (A),

Controllers for car electronics, gas detection and shut-off devices, various safety devices, etc.

2.3 Ordering Information

Part Number Package Internal ROM

µ

PD78056FYGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

µ

PD78056FYGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78058FYGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

µ

PD78058FYGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78058FYGK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Mask ROM

µ

PD78058FYGC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

µ

PD78P058FYGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) One-time PROM

µ

PD78P058FYGC-8BT

Note

80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) One-time PROM

Note Under development

Remark ××× indicates ROM code suffix.

48

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

2.4 Quality Grade

Part Number Package Quality Grade

µ

PD78056FYGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard

µ

PD78056FYGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78058FYGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard

µ

PD78058FYGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78058FYGK-×××-BE9 80-pin plastic TQFP (Fine pitch)(12 × 12 mm) Standard

µ

PD78058FYGC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Special

µ

PD78P058FYGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard

µ

PD78P058FYGC-8BT

Note Under development

Remark ××× indicates ROM code suffix.

Note

80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

Please refer to Quality grade on NEC Semiconductor Devices (Document number C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

49

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

2.5 Pin Configuration (Top View)

(1) Normal operating mode

80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)

µ

PD78056FYGC-×××-3B9, 78058FYGC-×××-3B9, 78058FYGC(A)-×××-3B9, µPD78P058FYGC-3B9

80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

µ

PD78056FYGC-×××-8BT, 78058FYGC-×××-8BT, 78P058FYGC-8BT

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

µ

PD78058FYGK-×××-BE9

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

REF0AVDD

AV

)

PP

XT1/P07

XT2

IC (V

X1X2V

DD

P06/INTP6

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2

Note

P01/INTP1/TI01

P00/INTP0/TI00

P15/ANI5
P16/ANI6
P17/ANI7

AV
P130/ANO0
P131/ANO1

AV

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P25/SI0/SB0/SDA0

P26/SO0/SB1/SDA1

P27/SCK0/SCL

REF1

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P40/AD0
P41/AD1

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Note Under development

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

SS

V

P60

P61

P62

P63

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P57/A15

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

P64/RD

RESET
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR

Cautions 1. Be sure to connect Internally Connected (IC) pin to V

2. The AVDD pin is used in common as the power supply for the A/D converter and port. If
this device is used in application fields where reduction of noise generated internally in
the microprocessor is required, please connect to a separate power supply with the same
electrical potential as V

3. The AV

SS pin is used in common as the ground for the A/D converter, D/A converter and

DD.

port. If this device is used in application fields where reduction of noise generated
internally in the microprocessor is required, please connect it to a ground line which is
separate from V

SS.

Remark Pin connection in parentheses is intended for the µPD78P058FY.

50

SS directly.

Pin Identifications

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

A8 to A15 : Address Bus
AD0 to AD7 : Address/Data Bus
ANI0 to ANI7 : Analog Input
ANO0, ANO1 : Analog Output
ASCK : Asynchronous Serial Clock
ASTB : Address Strobe

DD : Analog Power Supply

AV
AVREF0, 1 : Analog Reference Voltage

SS : Analog Ground

AV
BUSY : Busy
BUZ : Buzzer Clock
IC : Internally Connected
INTP0 to INTP6 : Interrupt from Peripherals
P00 to P07 : Port0
P10 to P17 : Port1
P20 to P27 : Port2
P30 to P37 : Port3
P40 to P47 : Port4
P50 to P57 : Port5
P60 to P67 : Port6
P70 to P72 : Port7
P120 to P127 : Port12
P130, P131 : Port13

PCL : Programmable Clock
RD ; Read Strobe
RESET : Reset
RTP0 to RTP7 : Real-Time Output Port
RxD : Receive Data
SB0, SB1 : Serial Bus
SCK0 to SCK2 : Serial Clock
SCL : Serial Clock
SDA0, SDA1 : Serial Data
SI0 to SI2 : Serial Input
SO0 to SO2 : Serial Output
STB : Strobe
TI00, TI01 : Timer Input
TI1, TI2 : Timer Input
TO0 to TO2 : Timer Output
TxD : Transmit Data

DD : Power Supply

V
VPP :

Programming Power Supply
VSS : Ground
WAIT : Wait
WR : Write Strobe
X1, X2 : Crystal (Main System Clock)
XT1, XT2 : Crystal (Subsystem Clock)

51

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

(2) PROM programming mode

80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)

µ

PD78P058FYGC-3B9

80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

µ

PD78P058FYGC-8BT

Note

(L)

(L)

(L)

(L)

VSS VDD (L)

Open

VPP (L)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2

V

SS

V

DD

A0
A1

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A2A3A4A5A6A7A8

A16

A10

A11

A12

DD

Open

V

SS

V

A13

A14

(L)

A15

PGM

(L)

(L)

A9

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

OE

RESET

(L)

D7
D6
D5
D4
D3
D2
D1
D0

(L)

CE

Note Under development

Cautions 1. (L) : Connect independently to VSS via a pull-down resistor.

SS : Connect to the ground.

2. V

3. RESET : Set to the low level.

4. Open : Do not connect anything.

A0 to A16 : Address Bus RESET : Reset
CE : Chip Enable V
D0 to D7 : Data Bus V

DD : Power Supply
PP : Programming Power Supply

OE : Output Enable VSS : Ground
PGM : Program

52

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

2.6 78K/0 Series Expansion

The 78K/0 Series expansion is shown below. The names in frames are subseries.

Products in mass production
Products under development

Y subseries products are compatible with I

Control

PD78075B

100-pin
100-pin

100-pin
100-pin
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42-/44-pin

µ

µµ

PD78078

µµ

PD78070A

PD780058

µµ

PD78058F

µµ

PD78054

µµ

µµ

PD780034

µµ

PD780024

µ

PD78014H

PD78018F

µµ

PD78014

µµ

PD780001

µ

PD78002

µ
µ

PD78083

PD78078Y

PD78070AY

µ

PD780018AY

PD780058Y

PD78058FY

PD78054Y
PD780034Y
PD780024Y

PD78018FY

PD78014Y

PD78002Y

µ

Note

EMI-noise reduced version of the PD78078
Timer was added to the PD78054 and the external interface function was enhanced
ROM-less versions of the PD78078
Serial I/O of the PD78078Y was enhanced and only selected functions are provided
Serial I/O of the PD78054 was enhanced. EMI-noise reduced version
EMI-noise reduced version of the PD78054
UART and D/A converter were added to the PD78014 and I/O was enhanced
A/D converter of the PD780024 was enhanced
Serial I/O of the PD78018F was enhanced
EMI-noise reduced version of the PD78018F
Low-voltage (1.8 V) operation versions of the PD78014 with choice of several ROM and RAM capacities

A/D converter and 16-bit timer were added to the PD78002
A/D converter was added to the PD78002
Basic subseries for control

On-chip UART, capable of operation at a low voltage (1.8 V)

µ

µ
µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

2

C bus.

Inverter control

µ

PD78098864-pin
64-pin
64-pin

78K/0

Series

100-pin
100-pin
80-pin

100-pin
100-pin
100-pin

80-pin
80-pin IEBus controller was added to the PD78054

PD780964

µ

PD780924

µ

FIP

PD780208

µ
µ

PD780228

µ

PD78044H

PD78044F80-pin Basic subseries for driving FIP. Display output total: 34

µ

LCD drive

PD780308

µµ

PD78064B

µ

IEBus

PD78098B

µ

Meter control

PD78097380-pin

µ

Note Under planning

drive

PD780308Y

µµ

PD78064

µ

PD78098

supported

PD78064Y

The inverter control, timer, and SIO of the PD780964 were enhanced. ROM size and RAM size were expanded
A/D converter of the PD780924 was enhanced
On-chip inverter control circuit and UART. EMI noise reduced version

The I/O and FIP C/D of the PD78044F were enhanced. Display output total: 53
The I/O and FIP C/D of the PD78044H were enhanced. Display output total: 48
N-ch open-drain I/O was added to the PD78044F. Display output total: 34

SIO of the PD78064 was enhanced. ROM size and RAM size were expanded
EMI-noise reduced version of the PD78064
Subseries for driving LCDs. On-chip UART

EMI-noise reduced version of the PD78098

µ

µ

µ

µ
µ

µ

µ

µ

µ

On-chip controller/driver for driving automobile meters

53

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

The differences between the major functions of each subseries are shown below.

Function ROM

Subseries Capacity
ControlµPD78078Y 48 K to 60 K 3-wire/2-wire/I2C : 1 ch 88 1.8 V

µ

PD78070AY — 3-wire with automatic send/receive function. : 1 ch 61 2.7 V

3-wire/UART : 1 ch

µ

PD780018AY 48 K to 60 K 3-wire with automatic send/receive function. : 1 ch 88

Time-division 3-wire : 1 ch
I2C Bus (Multi Master compatible) : 1 ch

µ

PD780058Y 24 K to 60 K 3-wire/2-wire/I2C : 1 ch 68 1.8 V

3-wire with automatic send/receive function. : 1 ch
3-wire/Time division UART : 1 ch

µ

PD78058FY 48 K to 60 K 3-wire/2-wire/I2C : 1 ch 69 2.7 V

µ

PD78054Y 16 K to 60 K

µ

PD780034Y 8 K to 32 K UART : 1 ch 51 1.8 V

µ

PD780024Y

µ

PD78018FY 8 K to 60 K 3-wire/2-wire/I2C : 1 ch 53

µ

PD78014Y 8 K to 32 K 3-wire/2-wire/SBI/I2C : 1 ch 2.7 V

µ

PD78002Y 8 K to 16 K 3-wire/2-wire/SBI/I2C : 1 ch
LCD
drive 3-wire/Time division UART : 1 ch

µ

PD780308Y 48 K to 60 K 3-wire/2-wire/I2C : 1 ch 57 2.0 V

µ

PD78064Y 16 K to 32 K 3-wire/2-wire/I2C : 1 ch

3-wire with automatic send/receive function. : 1 ch
3-wire/UART : 1 ch

3-wire : 1 ch
I2C Bus (Multi Master compatible) : 1 ch

3-wire with automatic send/receive function. : 1 ch

3-wire with automatic send/receive function. : 1 ch

3-wire : 1 ch

3-wire/UART : 1 ch

Serial Interface I/O

VDD

MIN. Value

2.0 V

Remark Functions other than the serial interface are common with Subseries without the Y.

54

2.7 Block Diagram

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

TO0/P30

TI00/INTP0/P00
TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

16-bit TIMER/
EVENT COUNTER

8-bit TIMER/
EVENT COUNTER 1

8-bit TIMER/
EVENT COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL
INTERFACE 0

SERIAL
INTERFACE 1

78K/0
CPU CORE

ROM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

P00
P01 to P06
P07

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P72

SI2/RxD/P70
SO2/TxD/P71
SCK2/ASCK/P72

ANI0/P10 to

ANI7/P17

AV

REF0

ANO0/P130,

ANO1/P131

SS

AV

AV

REF1

INTP0/P00 to

INTP6/P06

BUZ/P36

PCL/P35

SERIAL
INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT
CONTROL

BUZZER OUTPUT

CLOCK OUTPUT
CONTROL

V

RAM

DD

PORT 12

PORT 13

REAL-TIME
OUTPUT PORT

P120 to P127

P130, P131

RTP0/P120 to
RTP7/P127

AD0/P40 to
AD7/P47

A8/P50 to

EXTERNAL
ACCESS

A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67

RESET

SYSTEM
CONTROL

DD

AV

SS

AV

V

SS

IC

(V

PP

)

X1
X2
XT1/P07
XT2

Remarks 1. The internal ROM and RAM capacities depend on the product.

2. Pin connection in parentheses is intended for the µPD78P058FY.

55

2.8 Outline of Function

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

Part Number

Item

Internal
memory

Memory space 64 Kbytes
General register 8 bits × 8 × 4 banks

Minimum
instruction
execution
time

Instruction set • 16-bit operation

I/O port • Total : 69

ROM Mask ROM PROM

High-speed RAM 1024 bytes 1024 bytes
Buffer RAM 32 bytes
Expansion RAM None 1024 bytes 1024 bytes

With main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0-MHz operation)
With subsystem clock selected 122 µs (at 32.768-kHz operation)

µ

PD78056FY

48 Kbytes 60 Kbytes 60 Kbytes

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc.

• CMOS input : 2

• CMOS I/O : 63

• N-ch open-drain I/O : 4

µ

PD78058FY

µ

PD78P058FY

Note 1

Note 1

Note 2

A/D converter 8-bit resolution × 8 channels
D/A converter 8-bit resolution × 2 channels
Serial interface

Timer • 16-bit timer/event counter : 1 channel

Timer output Three outputs: (14-bit PWM output enable: 1)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,

Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at 5.0-MHz operation with main system

• 3-wire serial I/O/2-wire serial I/O/I2C bus mode selection possible : 1 channel

• 3-wire serial I/O mode (Max. 32-byte on-chip auto-transmit/receive) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel

2.5 MHz, 5.0 MHz (at 5.0-MHz operation with main system clock)

32.768 kHz (at 32.768-kHz operation with subsystem clock)

clock)

Notes 1. The capacities of the internal PROM and the internal high-speed RAM can be changed using the

memory switching register (IMS).

2. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size
switching register (IXS).

56

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

Part Number

Item

Vectored Maskable Internal: 13
interrupt External: 7
sources Non-maskable Internal: 1

Software 1

Test input Internal: 1

Supply voltage VDD = 2.7 to 6.0 V
Operating ambient temperature TA = –40 to +85°C
Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)

µ

PD78056FY

External: 1

• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

• 80-pin plastic TQFP (Fine pitch)(12 × 12 mm) (µPD78058FY only)

µ

PD78058FY

Note Under development for the µPD78P058FY only.

2.9 Differences Between the µPD78058FY and µPD78058FY(A)

Table 2-1. Differences Between the µPD78058FY and µPD78058FY(A)

µ

PD78P058FY

Note

Part Number

Item

Quality grade Standard Special

Package • 80-pin Plastic QFP • 80-pin Plastic QFP

(14 × 14 mm, Resin thickness: 2.7 mm)

• 80-pin Plastic QFP
(14 × 14 mm, Resin thickness: 1.4 mm)

• 80-pin Plastic TQFP (Fine Pitch)

(12 × 12 mm)

µ

PD78058FY

µ

PD78P058FY(A)

(14 × 14 mm, Resin thickness: 2.7 mm)

57

CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES)

2.10 Mask Options

The mask ROM versions (µPD78056FY, 78058FY) provide pull-up resistor mask options which allow users to
specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device
production. Using this mask option when pull-up resistors are required reduces the number of components to add
to the device, resulting in board space saving.

µ

The mask options provided in the

Table 2-2. Mask Options of Mask ROM Versions

Pin Names Mask Options
P60 to P63 Pull-up resistor connection can be specified in 1-bit units.

PD78058FY Subseries are shown in Table 2-2.

58

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.1 Pin Function List

3.1.1 Normal operating mode pins

(1) Port pins (1/3)

Pin Name

P00 Input Port 0. Input only Input INTP0/TI00
P01 Input/ 8-bit input/output port. Input/output mode can be specified Input INTP1/TI01
P02 output bit-wise. INTP2
P03 If used as an input port, an on-chip INTP3
P04 pull-up resistor can be used by INTP4
P05 software. INTP5
P06 INTP6

P07

P10 to P17 Input/ Port 1. Input ANI0 to ANI7

P20 Input/ Port 2. Input SI1
P21 output 8-bit input/output port. SO1
P22 Input/output mode can be specified bit-wise. SCK1
P23 If used as an input port, an on-chip pull-up resistor can be used by STB
P24 software. BUSY
P25 SI0/SB0
P26 SO0/SB1
P27 SCK0

Note 1

Input/Output

Input Input only Input XT1

output 8-bit input/output port.

Input/output mode can be specified bit-wise.
If used as input port, an on-chip pull-up resistor can be used by
software

Note 2

.

Function After Reset

Alternate Function

Notes 1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register

(PCC) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator).

2. When using pins P10/ANI0 to P17/ANI7 as analog input for the A/D converter, set port 1 to the input
mode. The on-chip pull-up resistor will be automatically disabled.

59

(1) Port pins (2/3)

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

Pin Name

P30 Input/ Port 3. Input TO0
P31 output 8-bit input/output port. TO1
P32 Input/output mode can be specified bit-wise. TO2
P33 If used as an input port, an on-chip pull-up resistor can be used by TI1
P34 software. TI2
P35 PCL
P36 BUZ
P37 —

P40 to P47 Input/ Port 4. Input AD0 to AD7

P50 to P57 Input/ Port 5. Input A8 to A15

P60 Input/ Port 6. Input —
P61 output 8-bit input/output port.
P62 Input/output mode can be
P63 specified bit-wise.
P64 If used as an input port, an on-chip RD
P65 pull-up resistor can be used by WR
P66 software. WAIT
P67 ASTB
P70 Input SI2/RxD

P71 SO2/TxD

P72 SCK2/ASCK

Input/Output

output 8-bit input/output port.

Input/output mode can be specified in 8-bit units.
If used as an input port, an on-chip pull-up resistor can be used by
software.
Test input flag (KRIF) is set to 1 by falling edge detection.

output 8-bit input/output port.

LED can be driven directly.
Input/output mode can be specified bit-wise.
If used as an input port, an on-chip pull-up resistor can be used by software.

Input/ Port 7.

output 3-bit input/output port.

Input/output mode can be specified bit-wise.
If used as an input port, an on-chip pull-up resistor can be used by software.

Function After Reset

N-ch open-drain input/output port.
On-chip pull-up resistor can be
specified by mask option (Mask
ROM version only).
LEDs can be driven directly.

Alternate Function

60

(1) Port pins (3/3)

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

Pin Name

P120 to P127

P130, P131 Input/ Port 13. Input ANO0 to ANO1

Input/Output

Input/ Port 12. Input RTP0 to RTP7

output 8-bit input/output port.

Input/output mode can be specified bit-wise.
If used as an input port, an on-chip pull-up resistor can be used by software.

output

2-bit input/output port.
Input/output mode can be specified bit-wise.
If used as an input port, an on-chip pull-up resistor can be used by software.

Function After Reset

Alternate Function

Cautions For pins which have alternate functions as port output, do not execute the following

operations during A/D conversion. If performed, then the general error standards cannot
be maintained during A/D conversion.
<1> If it is used as a port, rewriting the output latch of its output.
<2> Even if it is not used as a port, changing the output level of pins used as outputs.

61

(2) Non-port pins (1/2)

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

Pin Name

INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI00
INTP1 edge, falling edge, both rising and falling edges). P01/TI01
INTP2 P02
INTP3 P03
INTP4 P04
INTP5 P05
INTP6 P06

SI0 Input Serial interface serial data input Input P25/SB0
SI1 P20

SI2 P70/RxD
SO0 Output Serial interface serial data output Input P26/SB1
SO1 P21
SO2 P71/TxD
SB0 Input/ Serial interface serial data input/output Input P25/SI0
SB1 output P26/SO0

SCK0 Input/ Serial interface serial clock input/output Input P27
SCK1 output P22
SCK2 P72/ASCK

STB Output Serial interface automatic transmit/receive strobe output Input P23

BUSY Input Serial interface automatic transmit/receive busy input Input P24

RxD Input Asynchronous serial interface serial data input Input P70/SI2
TxD Output Asynchronous serial interface serial data output Input P71/SO2

ASCK Input Asynchronous serial interface serial clock input Input P72/SCK2

TI00 Input External count clock input to 16-bit timer (TM0) Input P00/INTP0
TI01 Capture trigger signal input to capture register (CR00) P01/INTP1

TI1 External count clock input to 8-bit timer (TM1) P33

TI2 External count clock input to 8-bit timer (TM2) P34
TO0 Output 16-bit timer (TM0) output (also used for 14-bit PWM output) Input P30
TO1 8-bit timer (TM1) output P31
TO2 8-bit timer (TM2) output P32
PCL Output Clock output (for main system clock and subsystem clock trimming) Input P35
BUZ Output Buzzer output Input P36

RTP0 to RTP7

Input/Output

Output Real-time output port outputting data in synchronization with trigger Input P120 to P127

Function After Reset

Alternate Function

62

(2) Non-port pins (2/2)

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

Pin Name

AD0 to AD7

A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57

RD Strobe signal output for read operation from external memory P64
WR Strobe signal output for write operation to external memory P65

WAIT Input Wait insertion when accessing external memory Input P66

ASTB Output Input P67

ANI0 to ANI7
ANO0, ANO1

AVREF0 Input A/D converter reference voltage input — —
AVREF1 Input D/A converter reference voltage input — —

AVDD —
AVSS — Ground potential (common with the port’s ground potential) of the A/D — —

RESET Input System reset input — —

X1 Input Crystal connection for main system clock oscillation — —

X2 — ——
XT1 Input Crystal connection for subsystem clock osicllation Input P07
XT2 — ——

VDD — Positive power supply (Except the port) — —

VPP —

VSS — Ground potential (Except the port) — —

Input/Output
Input/Output

Output Input

Input A/D converter analog input Input P10 to P17

Output D/A converter analog output Input P130, P131

IC — Internally connected. Connect directly to VSS.——

Low-order address/data bus when expanding external memory Input P40 to P47

Strobe output externally latching address information output to ports 4,
5 to access external memory

A/D converter analog power supply. (Common with the port power supply)

converter and D/A converter.

High-voltage application for program write/verify.
Connect directly to VSS in the normal operation mode.

Function After Reset

——

——

Alternate Function

Cautions 1. The AVDD pin is used in common as the power supply for the A/D converter and port. If

this device is used in application fields where reduction of noise generated internally in
the microprocessor is required, please connect to a separate power supply with the same
electrical potential as V

DD.

2. The AVSS pin is used as the ground potential for the A/D converter and D/A converter,
and also as the ground potential for the ports. If this device is used in application fields
where reduction of noise generated internally in the microprocessor is required, please
connect it to a ground line which is separate from V

SS.

63

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.1.2 PROM programming mode pins (PROM versions only)

Pin Name

RESET Input PROM programming mode setting.

VPP Input High-voltage application for PROM programming mode setting and program write/verify.

A0 to A16 Input Address bus

D0 to D7

CE Input PROM enable input/program pulse input
OE Input Read strobe input to PROM

PGM Input Program/program inhibit input in PROM programming mode

VDD — Positive power supply
VSS — Ground potential

Input/Output

Input/output

Function

When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,
the PROM programming mode is set.

Data bus

64

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.2 Description of Pin Functions

3.2.1 P00 to P07 (Port 0)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt
request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for
subsystem oscillation.

The following operating modes can be specified bit-wise.

(1) Port mode

P00 and P07 function as input-only ports and P01 to P06 function as input/output ports.
P01 to P06 can be specified for input or output ports bit-wise with a port mode register 0 (PM0). When they
are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor option
register L (PUOL).

(2) Control mode

In this mode, these ports function as an external interrupt request input, an external count clock input to the
timer, and crystal connection for subsystem clock oscillation.

(a) INTP0 to INTP6

INTP0 to INTP6 are external interrupt request input pins which can specify valid edges (rising edge, falling
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture
trigger signal input pin with a valid edge input.

(b) TI00

Pin for external count clock input to 16-bit timer/event counter

(c) TI01

Pin for capture trigger signal to capture register (CR00) of 16-bit timer/event counter

(d) XT1

Crystal connect pin for subsystem clock oscillation

65

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.2.2 P10 to P17 (Port 1)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog

input.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
a port mode register 1 (PM1). If used as input ports, on-chip pull-up resistors can be used to these ports by
defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as A/D converter analog input pins (ANI0 to ANI7). The on-chip pull-up resistor is
automatically disabled when the pins specified for analog input.

3.2.3 P20 to P27 (Port 2)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/

from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 2 (PM2). When they are used as input ports, on-chip pull-up resistors can be used to them
by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy
input, and strobe output functions.

(a) SI0, SI1, SO0, SO1

Serial interface serial data input/output pins

(b) SCK0 and SCK1

Serial interface serial clock input/output pins

(c) SB0 and SB1

NEC standard serial bus interface input/output pins

66

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

(d) BUSY

Serial interface automatic transmit/receive busy input pins

(e) STB

Serial interface automatic transmit/receive strobe output pins

Caution When this port is used as a serial interface pin, the I/O and output latches must be set

according to the function the user requires. For the setting, refer to Figure 16-4 “Serial
Operating Mode Register 0 Format” and Figure 18-3 “Serial Operating Mode Register
1 Format.”

3.2.4 P30 to P37 (Port 3)

These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock
output and buzzer output.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used by
defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as timer input/output, clock output, and buzzer output.

(a) TI1 and TI2

Pin for external count clock input to the 8-bit timer/event counter.

(b) TO0 to TO2

Timer output pins.

(c) PCL

Clock output pin.

(d) BUZ

Buzzer output pin.

67

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.2.5 P40 to P47 (Port 4)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus.
The test input flag (KRIF) can be set to 1 by detecting a falling edge.
The following operating mode can be specified in 8-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports
by using the memory expansion mode register (MM). When they are used as input ports, on-chip pull-up
resistors can be used by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as low-order address/data bus pins (AD0 to AD7) in external memory expansion mode.
When pins are used as an address/data bus, the on-chip pull-up resistor is automatically disabled.

3.2.6 P50 to P57 (Port 5)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus.
Port 5 can drive LEDs directly.
The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port
mode register 5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by defining
the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as high-order address bus pins (A8 to A15) in external memory expansion mode. When
pins are used as an address bus, the on-chip pull-up resistor is automatically disabled.

3.2.7 P60 to P67 (Port 6)

These are 8-bit input/output ports. Besides serving as input/output ports, they are used for control in external

memory expansion mode. P60 to P63 can drive LEDs directly.

The following operating modes can be specified bit-wise.

68

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 6 (PM6).
P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option.
When P64 to P67 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor
option register L (PUOL).

(2) Control mode

These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.
When a pin is used as a control signal output, the on-chip pull-up resistor is automatically disabled.

Caution When external wait is not used in external memory expansion mode, P66 can be used as an

input/output port.

3.2.8 P70 to P72 (Port 7)

This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/
output and clock input/output functions.

The following operating modes can be specified bit-wise.

(1) Port mode

Port 7 functions as a 3-bit input/output port. Bit-wise specification as an input port or output port is possible
by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register L (PUOL).

(2) Control mode

Port 7 functions as serial interface data input/output and clock input/output.

(a) SI2, SO2

Serial interface serial data input/output pins

(b) SCK2

Serial interface serial clock input/output pin.

(c) RxD, TxD

Asynchronous serial interface serial data input/output pins.

(d) ASCK

Asynchronous serial interface serial clock input/output pin.

Caution When this port is used as a serial interface pin, the I/O and output latches must be set

according to the function the user requires.
For the setting, refer to Table 19-2 “Serial Interface Channel 2 Operating Mode Settings of
List”.

69

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.2.9 P120 to P127 (Port 12)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port.
The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 12 (PM12). When they are used as input ports, on-chip pull-up resistors can be used by
defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports function as real-time output ports (RTP0 to RTP7) outputting data in synchronization with a
trigger.

3.2.10 P130 and P131 (Port 13)

These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog

output.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 2-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 13 (PM13). When they are used as input ports, on-chip pull-up resistors can be used by
defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports allow D/A converter analog output (ANO0 and ANO1).

Caution When only either one of the D/A converter channels is used with AV

that are not used as analog outputs must be set as follows:

• Set PM13× bit of the port mode register 13 (PM13) to 1 (input mode) and connect the pin

SS.

to V

• Set PM13× bit of the port mode register 13 (PM13) to 0 (output mode) and the output latch

to 0, to output low level from the pin.

3.2.11 AV

REF0

A/D converter reference voltage input pin.
When A/D converter is not used, connect this pin to V

3.2.12 AVREF1

D/A converter reference voltage input pin.
When D/A converter is not used, connect this pin to VDD.

REF1 > VDD, the other pins

SS.

70

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.2.13 AVDD

This is the analog power supply pin of the A/D converter and the port’s power supply pin. Always use the same
voltage as that of the V

DD pin even when the A/D converter is not used.

3.2.14 AVSS

This is the ground potential pin for the A/D converter and D/A converter, and the ground potential pin for the port.
Even when the A/D converter and D/A converter are not used, always use the same potential as that of the VSS pin.

3.2.15 RESET

This is a low-level active system reset input pin.

3.2.16 X1 and X2

Crystal resonator connect pins for main system clock oscillation.

For external clock supply, input it to X1 and its inverted signal to X2.

3.2.17 XT1 and XT2

Crystal resonator connect pins for subsystem clock oscillation.

For external clock supply, input it to XT1 and its inverted signal to XT2.

3.2.18 V

DD

Positive power supply pin (Except the port)

3.2.19 VSS

Ground potential pin (Except the port)

3.2.20 VPP (PROM versions only)

High-voltage apply pin for PROM programming mode setting and program write/verify. When in the normal
operating mode, connect directly to V

SS.

71

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.2.21 IC (Mask ROM version only)

The IC (Internally Connected) pin is provided to set the test mode to check the µPD78058F Subseries at delivery.

Connect it directly to the V

SS with the shortest possible wire in the normal operating mode.

When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins

is too long or an external noise is input to the IC pin, the user's program may not run normally.

Connect IC pins to VSS pins directly.

VSSIC

As short as possible

72

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

3.3 Input/output Circuits and Recommended Connection of Unused Pins

Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.

Refer to Figure 3-1 for the configuration of the input/output circuit of each type.

Table 3-1. Pin Input/Output Circuit Types (1/2)

Pin Name

P00/INTP0/TI00 2 Input Connect to VSS.
P01/INTP1/TI01 8-D Input/output
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
P07/XT1 16 Input Connect to VDD.
P10/ANI0 to P17/ANI7 11-C Input/output Connect independently via a resistor
P20/SI1 8-D Input/output to VDD or VSS.
P21/SO1 5-J
P22/SCK1 8-D
P23/STB 5-J
P24/BUSY 8-D
P25/SI0/SB0
P26/SO0/SB1 10-C
P27/SCK0
P30/TO0 5-J Input/output
P31/TO1
P32/TO2
P33/TI1 8-D
P34/TI2
P35/PCL 5-J
P36/BUZ
P37
P40/AD0 to P47/AD7 5-O Input/output Connect independently via a

P50/A8 to P57/A15 5-J Input/output

Input/Output

Circuit Type

Input/Output Recommended Connection of Unused Pins

Connect independently via a resistor to V

resistor to VDD.
Connect independently via a resistor to VDD or VSS.

SS.

73

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

Table 3-1. Pin Input/Output Circuit Types (2/2)

Pin Name

P60 to P63 (Mask ROM version) 13-I Input/output
P60 to P63 (PROM version) 13-H
P64/RD 5-D Input/output
P65/WR
P66/WAIT
P67/ASTB
P70/SI2/RxD 8-D
P71/SO2/TxD 5-J
P72/SCK2/ASCK 8-D
P120/RTP0 to P127/RTP7 5-J
P130/ANO0, P131/ANO1 12-B Input/output
RESET 2 Input —
XT2 16 — Leave open.
AVREF0
AVREF1 Connect to VDD.

AVDD

AVSS

IC (Mask ROM version) Connect directly to VSS.
VPP (PROM version)

Input/Output
Circuit Type

—

Input/Output Recommended Connection of Unused Pins

Connect independently via a resistor to VDD.

Connect independently via a resistor to VDD or VSS.

Connect independently via a resistor to VSS.

Connect to VSS.

Connect to a separate power supply with
the same potential as VDD.
Connect to a separate ground with the
same potential as VSS.

74

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

Figure 3-1. List of Pin Input/Output Circuit (1/2)

Type 2

Type 8-D

pull-up
enable

IN

data

Schmitt-Triggered Input with
Hysteresis Characteristics

output
disable

Type 5-J

pull-up
enable

data

AV

DD

P-ch

AV

DD

P-ch

Type 10-C

pull-up
enable

data

IN/OUT

output
disable

AV

N-ch

SS

open drain

output disable

input
enable

AV

Type 5-O Type 11-C

DD

AV

AV

DD

P-ch

N-ch

SS

AV

AV

AV

DD

P-ch

N-ch

SS

DD

P-ch

AV

AV

IN/OUT

DD

P-ch

IN/OUT

DD

pull-up
enable

data

output
disable

AV

AV

P-ch

N-ch

SS

pull-up

P-ch

DD

enable

data

AV

DD

P-ch

P-ch

IN/OUT

IN/OUT

output

disable

comparator

P-ch

+

–

AV

V

REF

(Threshold voltage)

N-ch

SS

AV

N-ch

SS

input
enable

75

CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES)

Figure 3-1. List of Pin Input/Output Circuit (2/2)

Type 12-B

pullup
enable

data

output

disable

input
enable

Type 13-H

output disable

data

analog output
voltage

RD

P-ch

N-ch

AVDD

P-ch

N-ch

AVSS

AVSS

N-ch

AVDD

P-ch

AV

AV

SS

DD

P-ch

IN/OUT

IN/OUT

Type 13-I

output disable

data

Type 16

RD

medium breakdown
input buffer

feedback
cut-off

P-ch

Mask
Option

N-ch

AVSS

AVDD

P-ch

AV

DD

IN/OUT

medium breakdown
input buffer

XT2XT1

76

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.1 Pin Function List

4.1.1 Normal operating mode pins

(1) Port pins (1/3)

Pin Name

P00 Input Port 0. Input only Input INTP0/TI00
P01 Input/ 8-bit input/output port. Input/output mode can be specified Input INTP1/TI01
P02 output bit-wise. INTP2
P03 If used as an input port, an on-chip INTP3
P04 pull-up resistor can be used by INTP4
P05 software. INTP5
P06 INTP6

P07

P10 to P17 Input/ Port 1. Input ANI0 to ANI7

P20 Input/ Port 2. Input SI1
P21 output 8-bit input/output port. SO1
P22 Input/output mode can be specified bit-wise. SCK1
P23 If used as an input port, an on-chip pull-up resistor can be used by STB
P24 software. BUSY
P25 SI0/SB0/SDA0
P26 SO0/SB1/SDA1
P27 SCK0/SCL

Note 1

Input/Output

Input Input only Input XT1

output 8-bit input/output port.

Input/output mode can be specified bit-wise.
If used as input port, an on-chip pull-up resistor can be used by
software

Note 2

.

Function After Reset

Alternate Function

Notes 1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register

(PCC) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator).

2. When using pins P10/ANI0 to P17/ANI7 as analog input for the A/D converter, set port 1 to the input
mode. The on-chip pull-up resistor will be automatically disabled.

77

(1) Port pins (2/3)

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

Pin Name

P30 Input/ Port 3. Input TO0
P31 output 8-bit input/output port. TO1
P32 Input/output mode can be specified bit-wise. TO2
P33 If used as an input port, an on-chip pull-up resistor can be used by TI1
P34 software. TI2
P35 PCL
P36 BUZ
P37 —

P40 to P47 Input/ Port 4. Input AD0 to AD7

P50 to P57 Input/ Port 5. Input A8 to A15

P60 Input/ Port 6. Input —
P61 output 8-bit input/output port.
P62 Input/output mode can be
P63 specified bit-wise.
P64 If used as an input port, an on-chip RD
P65 pull-up resistor can be used by WR
P66 software. WAIT
P67 ASTB
P70 Input/ Port 7. Input SI2/RxD
P71 output 3-bit input/output port. SO2/TxD
P72 Input/output mode can be specified bit-wise. SCK2/ASCK

Input/Output

output 8-bit input/output port.

Input/output mode can be specified in 8-bit units.
If used as an input port, an on-chip pull-up resistor can be used by
software.
Test input flag (KRIF) is set to 1 by falling edge detection.

output 8-bit input/output port.

LED can be driven directly.
Input/output mode can be specified bit-wise.
If used as an input port, an on-chip pull-up resistor can be used by software.

If used as an input port, an on-chip pull-up resistor can be used by software.

Function After Reset

N-ch open drain input/output port.
On-chip pull-up resistor can be
specified by mask option.
(Mask ROM version only).
LEDs can be driven directly.

Alternate Function

78

(1) Port pins (3/3)

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

Pin Name

P120 to P127

P130 to P131

Input/Output

Input/ Port 12. Input RTP0 to RTP7

output 8-bit input/output port.

Input/output mode can be specified bit-wise.
If used as an input port, an on-chip pull-up resistor can be used by software.

Input/ Port 13. Input

output 2-bit input/output port.

Input/output mode can be specified bit-wise.
If used as an input port, an on-chip pull-up resistor can be used by software.

Function After Reset

Cautions For pins which have alternate functions as port output, do not execute the following

operations during A/D conversion. If performed, then the general error standards cannot
be maintained during A/D conversion.
<1> If it is used as a port, rewriting the output latch of its output.
<2> Even if it is not used as a port, changing the output level of pins used as outputs.

Alternate Function

ANO0 to ANO1

79

(2) Non-port pins (1/2)

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

Pin Name

INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI00
INTP1 edge, falling edge, both rising and falling edges). P01/TI01
INTP2 P02
INTP3 P03
INTP4 P04
INTP5 P05
INTP6 P06

SI0 Input Serial interface serial data input Input P25/SB0/SDA0
SI1 P20

SI2 P70/RxD
SO0 Output Serial interface serial data output Input P26/SB1/SDA1
SO1 P21
SO2 P71/TxD
SB0 Input/ Serial interface serial data input/output Input P25/SI0/SDA0
SB1 output P26/SO0/SDA1

SDA0 P25/SI0/SB0
SDA1 P26/SO0/SB1
SCK0 Input/ Serial interface serial clock input/output Input P27/SCL
SCK1 output P22
SCK2 P72/ASCK

SCL P27/SCK0
STB Output Serial interface automatic transmit/receive strobe output Input P23

BUSY Input Serial interface automatic transmit/receive busy input Input P24

RxD Input Asynchronous serial interface serial data input Input P70/SI2
TxD Output Asynchronous serial interface serial data output Input P71/SO2

ASCK Input Asynchronous serial interface serial clock input Input P72/SCK2

TI00 Input External count clock input to 16-bit timer (TM0) Input P00/INTP0
TI01 Capture trigger signal input to capture register (CR00) P01/INTP1

TI1 External count clock input to 8-bit timer (TM1) P33

TI2 External count clock input to 8-bit timer (TM2) P34
TO0 Output 16-bit timer (TM0) output (also used for 14-bit PWM output) Input P30
TO1 8-bit timer (TM1) output P31
TO2 8-bit timer (TM2) output P32
PCL Output Clock output (for main system clock and subsystem clock trimming) Input P35
BUZ Output Buzzer output Input P36

RTP0 to RTP7

Input/Output

Output Real-time output port outputting data in synchronization with trigger Input P120 to P127

Function After Reset

Alternate Function

80

(2) Non-port pins (2/2)

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

Pin Name

AD0 to AD7

A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57

RD Output Strobe signal output for read operation from external memory Input P64
WR Strobe signal output for write operation to external memory P65

WAIT Input Wait insertion when accessing external memory Input P66

ASTB Output Strobe output externally latching address information output to ports 4, Input P67

ANI0 to ANI7
ANO0, ANO1

AVREF0 Input A/D converter reference voltage input — —
AVREF1 Input D/A converter reference voltage input — —

AVDD —
AVSS — Ground potential (common with the port’s ground potential) of the A/D — —

RESET Input System reset input — —

X1 Input Crystal connection for main system clock oscillation — —

X2 — ——
XT1 Input Crystal connection for subsystem clock oscillation Input P07
XT2 — ——

VDD — Positive power supply (Except the port) — —
VPP — High-voltage application for program write/verify. Connect directly to — —

VSS — Ground potential (Except the port) — —

Input/Output
Input/Output

Input A/D converter analog input Input P10 to P17

Output D/A converter analog output Input P130, P131

IC — Internally connected. Connect directly to VSS.——

Low-order address/data bus when expanding external memory Input P40 to P47

5 to access external memory

A/D converter analog power supply. (Common with the port power supply)

converter and D/A converter.

VSS in the normal operating mode.

Function After Reset

——

Alternate Function

Cautions 1. The AVDD pin is used in common as the power supply for the A/D converter and port.

If this device is used in application fields where reduction of noise generated internally
in the microprocessor is required, please connect to a separate power supply with the
same electrical potential as V

DD.

2. The AVSS pin is used as the ground potential for the A/D converter and
D/A convertor, and as the ground potential for the ports. If this device is used in
application fields where reduction of noise generated internally in the microprocessor
is required, please connect it to a ground line which is separate from V

SS.

81

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.1.2 PROM programming mode pins (PROM versions only)

Pin Name

RESET Input PROM programming mode setting.

VPP Input High-voltage application for PROM programming mode setting and program write/verify.

A0 to A16 Input Address bus

D0 to D7

CE Input PROM enable input/program pulse input
OE Input Read strobe input to PROM

PGM Input Program/program inhibit input in PROM programming mode

VDD — Positive power supply
VSS — Ground potential

Input/Output

Input/output

Function

When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,
the PROM programming mode is set.

Data bus

82

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.2 Description of Pin Functions

4.2.1 P00 to P07 (Port 0)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt
request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for
subsystem oscillation.

The following operating modes can be specified bit-wise.

(1) Port mode

P00 and P07 function as input-only ports and P01 to P06 function as input/output ports.
P01 to P06 can be specified for input or output ports bit-wise with a port mode register 0 (PM0). When they
are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor option
register L (PUOL).

(2) Control mode

In this mode, these ports function as an external interrupt request input, an external count clock input to the
timer, and crystal connection for subsystem clock oscillation.

(a) INTP0 to INTP6

INTP0 to INTP6 are external interrupt request input pins which can specify valid edges (rising edge, falling
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture
trigger signal input pin with a valid edge input.

(b) TI00

Pin for external count clock input to 16-bit timer/event counter

(c) TI01

Pin for capture trigger signal to capture register (CR00) of 16-bit timer/event counter

(d) XT1

Crystal connect pin for subsystem clock oscillation

83

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.2.2 P10 to P17 (Port 1)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog

input.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
a port mode register 1 (PM1). If used as input ports, on-chip pull-up resistors can be used to these ports by
defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as A/D converter analog input pins (ANI0 to ANI7). The on-chip pull-up resistor is
automatically disabled when the pins specified for analog input.

4.2.3 P20 to P27 (Port 2)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/

from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 2 (PM2). When they are used as input ports, on-chip pull-up resistors can be used to them
by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy
input, and strobe output functions.

(a) SI0, SI1, SO0, SO1, SB0, SB1, SDA0, SDA1

Serial interface serial data input/output pins

(b) SCK0, SCK1, SCL

Serial interface serial clock input/output pins

(c) BUSY

Serial interface automatic transmit/receive busy input pins

(d) STB

Serial interface automatic transmit/receive strobe output pins

84

Caution When this port is used as a serial interface pin, the I/O and output latches must be set

according to the function the user requires. For the setting, refer to Figure 17-4 “Serial
Operating Mode Register 0 Format” and Figure 18-3 “Serial Operating Mode Register
1 Format.”

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.2.4 P30 to P37 (Port 3)

These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock
output, and buzzer output.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used by
defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as timer input/output, clock output, and buzzer output.

(a) TI1 and TI2

Pin for external count clock input to the 8-bit timer/event counter.

(b) TO0 to TO2

Timer output pins.

(c) PCL

Clock output pin.

(d) BUZ

Buzzer output pin.

85

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.2.5 P40 to P47 (Port 4)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus.
The test input flag (KRIF) can be set to 1 by detecting a falling edge.
The following operating mode can be specified in 8-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports
by using the memory expansion mode register (MM). When they are used as input ports, on-chip pull-up
resistors can be used by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as low-order address/data bus pins (AD0 to AD7) in external memory expansion mode.
When pins are used as an address/data bus, the on-chip pull-up resistor is automatically disabled.

4.2.6 P50 to P57 (Port 5)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus.
Port 5 can drive LEDs directly.
The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input/output ports with port
mode register 5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by defining
the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as high-order address bus pins (A8 to A15) in external memory expansion mode. When
pins are used as an address bus, the on-chip pull-up resistor is automatically disabled.

4.2.7 P60 to P67 (Port 6)

These are 8-bit input/output ports. Besides serving as input/output ports, they are used for control in external

memory expansion mode. P60 to P63 can drive LEDs directly.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 6 (PM6).
P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option.
When P64 to P67 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor
option register L (PUOL).

(2) Control mode

These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.
When a pin is used as a control signal output, the on-chip pull-up resistor is automatically disabled.

Caution When external wait is not used in external memory expansion mode, P66 can be used as an

input/output port.

86

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.2.8 P70 to P72 (Port 7)

This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/
output and clock input/output functions.

The following operating modes can be specified bit-wise.

(1) Port mode

Port 7 functions as a 3-bit input/output port. Bit-wise specification as an input port or output port is possible
by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register L (PUOL).

(2) Control mode

Port 7 functions as serial interface data input/output and clock input/output.

(a) SI2, SO2

Serial interface serial data input/output pins

(b) SCK2

Serial interface serial clock input/output pin.

(c) RxD, TxD

Asynchronous serial interface serial data input/output pins.

(d) ASCK

Asynchronous serial interface serial clock input/output pin.

Caution When this port is used as a serial interface pin, the I/O and output latches must be set

according to the function the user requires.
For the setting, refer to Table 19-2 “Serial Interface Channel 2 Operating Mode Settings of
List.”

87

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.2.9 P120 to P127 (Port 12)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port.
The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 12 (PM12). When they are used as input ports, on-chip pull-up resistors can be used by
defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports function as real-time output ports (RTP0 to RTP7) outputting data in synchronization with a trigger.

4.2.10 P130 and P131 (Port 13)

These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog

output.

The following operating modes can be specified bit-wise.

(1) Port mode

These ports function as 2-bit input/output ports. They can be specified bit-wise as input or output ports with
port mode register 13 (PM13). When they are used as input ports, on-chip pull-up resistors can be used by
defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports allow D/A converter analog output (ANO0 and ANO1).

Caution When only either one of the D/A converter channels is used with AV

that are not used as analog outputs must be set as follows:

• Set PM13× bit of the port mode register 13 (PM13) to 1 (input mode) and connect the pin

SS.

to V

• Set PM13× bit of the port mode register 13 (PM13) to 0 (output mode) and the output latch

to 0, to output low level from the pin.

4.2.11 AV

REF0

A/D converter reference voltage input pin.
When A/D converter is not used, connect this pin to VSS.

4.2.12 AV

REF1

D/A converter reference voltage input pin.
When D/A converter is not used, connect this pin to V

REF1< VDD, the other pins

DD.

88

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.2.13 AVDD

This is the analog power supply pin of the A/D converter and the port’s power supply pin.

DD

voltage as that of the V

pin even when the A/D converter is not used.

Always use the same

4.2.14 AVSS

This is the ground potential pin for the A/D converter and D/A converter, and the ground potential pin for the port.
Even when the A/D converter and D/A converter are not used, always use the same potential as that of the VSS pin.

4.2.15 RESET

This is a low-level active system reset input pin.

4.2.16 X1 and X2

Crystal resonator connect pins for main system clock oscillation.

For external clock supply, input it to X1 and its inverted signal to X2.

4.2.17 XT1 and XT2

Crystal resonator connect pins for subsystem clock oscillation.

For external clock supply, input it to XT1 and its inverted signal to XT2.

4.2.18 V

DD

Positive power supply pin (Except the port)

4.2.19 VSS

Ground potential pin (Except the port)

4.2.20 VPP (PROM versions only)

High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to V
in normal operating mode.

When in the normal operating mode, connect directly to VSS.

SS

89

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.2.21 IC (Mask ROM version only)

The IC (Internally Connected) pin is provided to set the test mode to check the µPD78058FY Subseries at delivery.

Connect it directly to the V

SS with the shortest possible wire in the normal operating mode.

When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins

is too long or an external noise is input to the IC pin, the user's program may not run normally.

Connect IC pins to VSS pins directly.

VSSIC

As short as possible

90

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

4.3 Input/output Circuits and Recommended Connection of Unused Pins

Table 4-1 shows the input/output circuit types of pins and the recommended connection for unused pins.

Refer to Figure 4-1 for the configuration of the input/output circuit of each type.

Table 4-1. Pin Input/Output Circuit Types (1/2)

Pin Name

P00/INTP0/TI00 2 Input Connect to VSS.
P01/INTP1/TI01 8-D Input/output
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
P07/XT1 16 Input Connect to VDD
P10/ANI0 to P17/ANI7 11-C Input/output Connect independently via a resistor
P20/SI1 8-D Input/output to VDD or VSS.
P21/SO1 5-J
P22/SCK1 8-D
P23/STB 5-J
P24/BUSY 8-D
P25/SI0/SB0/SDA0 10-C
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/TO0 5-J Input/output
P31/TO1
P32/TO2
P33/TI1 8-D
P34/TI2
P35/PCL 5-J
P36/BUZ
P37
P40/AD0 to P47/AD7 5-O Input/output
P50/A8 to P57/A15 5-J Input/output

Input/Output

Circuit Type

Input/Output Recommended Connection of Unused Pins

Connect independently via a resistor to V

Connect independently via a resistor to VDD.
Connect independently via a resistor to VDD or VSS.

SS.

91

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

Table 4-1. Pin Input/Output Circuit Types (2/2)

Pin Name

P60 to P63 (Mask ROM version) 13-I Input/output
P60 to P63 (PROM version) 13-H Input/output
P64/RD 5-D
P65/WR
P66/WAIT
P67/ASTB
P70/SI2/RxD 8-D
P71/SO2/TxD 5-J
P72/SCK2/ASCK 8-D
P120/RTP0 to P127/RTP7 5-J
P130/ANO0 to P131/ANO1 12-B Input/output
RESET 2 Input —
XT2 16 — Leave open.
AVREF0 — Connect to VSS.
AVREF1 Connect to VDD.
AVDD Connect to a separate power supply with

AVSS Connect to a separate ground with the

IC (Mask ROM version) Connect directly to VSS.
VPP (PROM version)

Input/Output
Circuit Type

Input/Output Recommended Connection of Unused Pins

Connect independently via a resistor to VDD.
Connect independently via a resistor to VDD or VSS.

Connect independently via a resistor to VSS.

the same potential as VDD.

same potential as VSS.

92

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

Figure 4-1. List of Pin Input/Output Circuit (1/2)

Type 2

Type 8-D

pullup
enable

IN

data

Schmitt-Triggered Input with
Hysteresis Characteristics

output
disable

Type 5-J

pullup
enable

data

AV

DD

P-ch

AV

DD

P-ch

Type 10-C

pullup
enable

data

IN/OUT

output
disable

AV

N-ch

SS

open drain

output disable

input
enable

AV

Type 5-O Type 11-C

DD

AV

AV

DD

P-ch

N-ch

SS

AV

AV

AV

DD

P-ch

N-ch

SS

DD

P-ch

AV

AV

IN/OUT

DD

P-ch

IN/OUT

DD

pullup
enable

data

output
disable

AV

AV

P-ch

N-ch

SS

pullup

P-ch

DD

enable

data

AV

DD

P-ch

P-ch

IN/OUT

IN/OUT

output

disable

comparator

P-ch

+

–

AV

V

REF

(Threshold voltage)

N-ch

AV

SS

N-ch

SS

input
enable

93

CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES)

Figure 4-1. List of Pin Input/Output Circuit (2/2)

Type 12-B

pullup
enable

data

output

disable

input
enable

Type 13-H

output disable

data

analog output
voltage

RD

P-ch

N-ch

AVDD

P-ch

N-ch

AVSS

AVSS

N-ch

AVDD

P-ch

AV

AV

SS

DD

P-ch

IN/OUT

IN/OUT

Type 13-I

output disable

data

Type 16

RD

medium breakdown
input buffer

feedback
cut-off

P-ch

Mask
Option

N-ch

AVSS

AVDD

P-ch

AV

DD

IN/OUT

medium breakdown
input buffer

XT2XT1

94

CHAPTER 5 CPU ARCHITECTURE

5.1 Memory Spaces

64-Kbyte memory spaces can be accessed in the µPD78058F, 78058FY Subseries.
Figures 5-1 to 5-3 show memory maps.

µ

Figure 5-1. Memory Map (

PD78056F, 78056FY)

Data memory
space

Program
memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

FA80H
FA7FH

C000H

BFFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

External Memory

14976 × 8 bits

BFFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

0000H

Internal ROM

49152 × 8 bits

0040H
003FH

Vector Table Area

0000H

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CHAPTER 5 CPU ARCHITECTURE

Figure 5-2. Memory Map (µPD78058F, 78058FY)

Data memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

F800H
F7FFH

F400H
F3FFH

F000H
EFFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

Internal

Expansion RAM

1024 × 8 bits

Reserved

Note

EFFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

Program
memory
space

Internal ROM

61440 × 8 bits

0000H

0040H
003FH

Vector Table Area

0000H

Note When internal ROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH

can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the
memory size switching register (IMS).

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CHAPTER 5 CPU ARCHITECTURE

Figure 5-3. Memory Map (µPD78P058F, µPD78P058FY)

Data memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

F800H
F7FFH

F400H
F3FFH

F000H
EFFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

Internal

Expansion RAM

1024 × 8 bits

Reserved

Note

EFFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

Program
memory
space

Internal PROM

61440 × 8 bits

0000H

0040H
003FH

Vector Table Area

0000H

Note When internal PROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH

can be used as external memory by setting the internal PROM size to less than 56 Kbytes by the
memory size switching register (IMS).

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CHAPTER 5 CPU ARCHITECTURE

5.1.1 Internal program memory space

The µPD78056F and µPD78056FY are Mask ROM with a 49152 x 8 bit configuration, the µPD78058F and

µ

PD78058FY are Mask ROM with a 61440 x 8 bit configuration and the µPD78P058F and µPD78P058FY are PROM
with a 61440 x 8 bit configuration. They store program and table data, etc. Normally, they are addressed by the
program counter (PC).

The areas shown below are allocated to the internal program memory space.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start
addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the
16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.

Table 5-1. Vector Table

Vector Table Address Interrupt Sources

0000H RESET input
0004H INTWDT
0006H INTP0

0008H INTP1
000AH INTP2
000CH INTP3
000EH INTP4

0010H INTP5

0012H INTP6

0014H INTCSI0

0016H INTCSI1

0018H INTSER
001AH INTSR/INTCSI2
001CH INTST
001EH INTTM3

0020H INTTM00

0022H INTTM01

0024H INTTM1

0026H INTTM2

0028H INTAD
003EH BRK

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CHAPTER 5 CPU ARCHITECTURE

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

5.1.2 Internal data memory space

µ

PD78058F and 78058FY Subseries units incorporate the following RAMs.

The

(1) Internal high-speed RAM

This RAM has a 1024 x 8 bit configuration. In this area, four banks of general registers, each bank consisting
of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack memory.

(2) Internal buffer RAM

Internal buffer RAM is allocated to the 32-byte area from FAC0H to FADFH. The internal buffer RAM is used
to store transmit/receive data of serial interface channel 1 (in 3-wire serial I/O mode with automatic transfer/
receive function). If the 3-wire serial I/O mode with automatic transfer/receive function is not used, the internal
buffer RAM can also be used as normal RAM. Internal buffer RAM can also be used as normal RAM.

µ

(3) Internal expansion RAM (

Internal expansion RAM is allocated to the 1024-byte area from F400H to F7FFH.

5.1.3 Special Function Register (SFR) area

An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH. (Refer

to Table 5-3. Special-Function Register List in Section 5.2.3 Special Function Register (SFR)).

Caution Do not access addresses where the SFR is not assigned.

5.1.4 External memory space

The external memory space is accessible by setting the memory expansion mode register (MM). External memory

space can store program, table data, etc. and allocate peripheral devices.

PD78058F, 78058FY, 78P058F, 78P058FY only)

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CHAPTER 5 CPU ARCHITECTURE

5.1.5 Data memory addressing

The method to specify the address of the instruction to be executed next, or the address of a register or memory

to be manipulated when an instruction is executed is called addressing.

The address of the instruction to be executed next is addressed by the program counter PC (for details, refer to

Section 5.3 Instruction Address Addressing).

On the other hand, concerning addressing of memory which is the object of operations during execution of a

µ

command, in the

PD78058F and µPD78058FY Subseries, abundant addressing modes have been provided in
consideration of operability, etc. Particularly in areas (FB00H to FFFFH) where data memory is incorporated special
addressing which matches the respective functions of the special function register (SFR), general purpose register,
etc., is possible. Figure 5-4 to 5-6 show the data memory addressing modes. For details of each addressing, refer
to Section 5.4 Operand Address Addressing.

µ

Figure 5-4. Data Memory Addressing (

PD78056F, 78056FY)

FFFFH

FF20H
FF1FH

FF00H
FEFFH

FEE0H
FEDFH

FE20H
FE1FH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

FA80H
FA7FH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

SFR Addressing

Register Addressing

Short Direct
Addressing

Direct Addressing
Register Indirect

Addressing
Based Addressing

Based Indexed
Addressing

100

External Memory

14976 × 8 bits

C000H
BFFFH

Internal ROM

49152 × 8 bits

0000H