NEC PD70F3709, PD70F3710, PD70F3711, PD70F3712 User Guide

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User’s Manual

V850ES/HJ2

32-bit Single-Chip Microcontrollers

Hardware

μPD70F3709 μPD70F3710 μPD70F3711 μPD70F3712

Document No. U17717EJ3V0UD00 (3rd edition)

Date Published March 2007 N CP(K)

2005

Printed in Japan

[MEMO]

2	User’s Manual U17717EJ3V0UD

NOTES FOR CMOS DEVICES

1VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).

2HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

3PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

4STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

5POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.

6INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

User’s Manual U17717EJ3V0UD

IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America.

Applilet is a registered trademark of NEC Electronics in Japan, Germany, Hong Kong, China, the Republic of Korea, the United Kingdom, and the United States of America.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

TRON is an abbreviation of The Real-Time Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

4	User’s Manual U17717EJ3V0UD

•The information in this document is current as of August, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

•No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.

•NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

•Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

•While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.

•NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note)

(1)"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries.

(2)"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).

M8E	02. 11-1
User’s Manual U17717EJ3V0UD	5

PREFACE

Readers	This manual is intended for	users who wish to understand the functions of the
	V850ES/HJ2 and design application systems using the V850ES/HJ2.
Purpose	This manual is intended to give users an understanding of the hardware functions of
	the V850ES/HJ2 shown in the Organization below.
Organization	This manual is divided into	two parts: Hardware (this manual) and Architecture
	(V850ES Architecture User’s Manual).

	Hardware		Architecture


	• Pin functions		• Data types
	• CPU function		• Register set
	• On-chip peripheral functions		• Instruction format and instruction set
	• Flash memory programming		• Interrupts and exceptions
	• Electrical specifications		• Pipeline operation
How to Read This Manual	It is assumed that the readers of this manual have general knowledge in the fields of
	electrical engineering, logic circuits, and microcontrollers.

To understand the overall functions of the V850ES/HJ2

→ Read this manual according to the CONTENTS.

To find the details of a register where the name is known

→ Use APPENDIX B REGISTER INDEX.

To understand the details of an instruction function

→ Refer to the V850ES Architecture User’s Manual available separately.

To know the electrical specifications of the V850ES/HJ2

→ See CHAPTER 27 ELECTRICAL SPECIFICATIONS.

The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler cannot recognize it correctly.

The mark <R> shows major revised points. The revised points can be easily searched by copying an “<R>” in the PDF file and specifying it in the “Find what:” field.

6	User’s Manual U17717EJ3V0UD

Conventions	Data significance:	Higher digits on the left and lower digits on the right
	Active low representation:		(overscore over pin or signal name)
	Active low representation:	xxx	(overscore over pin or signal name)
	Memory map address:	Higher addresses on the top and lower addresses on
		the bottom
	Note:	Footnote for item marked with Note in the text
	Caution:	Information requiring particular attention
	Remark:	Supplementary information
	Numeric representation:	Binary ... xxxx or xxxxB
		Decimal ... xxxx
		Hexadecimal ... xxxxH
	Prefix indicating power of 2
	(address space, memory
	capacity):	K (kilo): 210 = 1,024
		M (mega): 220 = 1,0242
		G (giga): 230 = 1,0243

User’s Manual U17717EJ3V0UD

Related Documents

The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents related to V850ES/HJ2

Document Name	Document No.

V850ES Architecture User’s Manual	U15943E

V850ES/HJ2 Hardware User’s Manual	This manual

Documents related to development tools (user’s manuals)

Document Name		Document No.

QB-V850MINI On-Chip Debug Emulator		U17638E

QB-MINI2 On-Chip Debug Emulator with Flash Programming Function		To be prepared

CA850 Ver. 3.00 C Compiler Package	Operation	U17293E

	C Language	U17291E

	Assembly Language	U17292E

	Link Directives	U17294E

PM+ Ver. 6.20 Project Manager		U17990E

ID850QB Ver. 3.20 Integrated Debugger	Operation	U17964E

SM850 Ver. 2.50 System Simulator	Operation	U16218E

SM850 Ver. 2.00 or Later System Simulator	External Part User Open	U14873E
	Interface Specification

SM+ System Simulator	Operation	U17246E

	User Open Interface	U17247E
	Specification

RX850 Ver. 3.20 Real-Time OS	Basics	U13430E

	Installation	U17419E

	Technical	U13431E

	Task Debugger	U17420E

RX850 Pro Ver. 3.20 Real-Time OS	Basics	U13773E

	Installation	U17421E

	Technical	U13772E

	Task Debugger	U17422E

AZ850 Ver. 3.30 System Performance Analyzer		U17423E

PG-FP4 Flash Memory Programmer		U15260E

User’s Manual U17717EJ3V0UD

		CONTENTS
CHAPTER 1 INTRODUCTION .................................................................................................................			18
1.1	General .....................................................................................................................................		18
1.2	Features....................................................................................................................................		20
1.3	Application Fields ...................................................................................................................		21
1.4	Ordering Information ..............................................................................................................		21
1.5	Pin Configuration (Top View).................................................................................................		22
1.6	Function Block Configuration................................................................................................		24
	1.6.1	Internal block diagram ...............................................................................................................	24
	1.6.2	Internal units..............................................................................................................................	25
CHAPTER 2 PIN FUNCTIONS................................................................................................................			27
2.1	Pin Function List .....................................................................................................................		27
2.2	Pin Status.................................................................................................................................		35
2.3	Description of Pin Functions .................................................................................................		36
2.4	Pin I/O Circuit Types and Recommended Connection of Unused Pins ............................		45
2.5	Pin I/O Circuits.........................................................................................................................		48
2.6	Cautions ...................................................................................................................................		49
CHAPTER 3 CPU FUNCTION.................................................................................................................			50
3.1	Features....................................................................................................................................		50
3.2	CPU Register Set.....................................................................................................................		51
	3.2.1	Program register set ..................................................................................................................	52
	3.2.2	System register set....................................................................................................................	53
3.3	Operation Modes .....................................................................................................................		59
	3.3.1	Specifying operation mode ........................................................................................................	59
3.4	Address Space ........................................................................................................................		60
	3.4.1	CPU address space...................................................................................................................	60
	3.4.2 Wraparound of CPU address space ..........................................................................................		61
	3.4.3	Memory map..............................................................................................................................	62
	3.4.4	Areas .........................................................................................................................................	64
	3.4.5 Recommended use of address space .......................................................................................		68
	3.4.6	Peripheral I/O registers..............................................................................................................	71
	3.4.7	Special registers ........................................................................................................................	82
	3.4.8	Cautions ....................................................................................................................................	86
CHAPTER 4 PORT FUNCTIONS............................................................................................................			89
4.1	Features....................................................................................................................................		89
4.2	Basic Configuration of Ports .................................................................................................		89
4.3	Port Functions .........................................................................................................................		91
	4.3.1 Operation of port function ..........................................................................................................		91
	4.3.2 Notes on setting port pins..........................................................................................................		92
	4.3.3	Port 0.........................................................................................................................................	93
	4.3.4	Port 1.........................................................................................................................................	97
	4.3.5	Port 3.......................................................................................................................................	100
	4.3.6	Port 4.......................................................................................................................................	106

User’s Manual U17717EJ3V0UD

	4.3.7	Port 5 .......................................................................................................................................	109
	4.3.8	Port 6 .......................................................................................................................................	115
	4.3.9	Port 7 .......................................................................................................................................	122
	4.3.10	Port 8 .......................................................................................................................................	124
	4.3.11	Port 9 .......................................................................................................................................	127
	4.3.12	Port 12 .....................................................................................................................................	137
	4.3.13	Port CD....................................................................................................................................	139
	4.3.14	Port CM ...................................................................................................................................	141
	4.3.15	Port CS ....................................................................................................................................	144
	4.3.16	Port CT ....................................................................................................................................	147
	4.3.17	Port DL ....................................................................................................................................	150
	4.3.18	Port pins that function alternately as on-chip debug function...................................................	153
	4.3.19	Register settings to use port pins as alternate-function pins....................................................	154
4.4	Block Diagrams of Port........................................................................................................		161
4.5	Cautions ................................................................................................................................		190
	4.5.1	Cautions on setting port pins ...................................................................................................	190
CHAPTER 5 BUS CONTROL FUNCTION..........................................................................................			191
5.1	Features.................................................................................................................................		191
5.2	Bus Control Pins...................................................................................................................		192
	5.2.1	Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............	192
	5.2.2	Pin status in each operation mode...........................................................................................	192
5.3	Memory Block Function.......................................................................................................		193
5.4	Bus Access ...........................................................................................................................		194
	5.4.1	Number of clocks for access....................................................................................................	194
	5.4.2	Bus size setting function ..........................................................................................................	194
	5.4.3	Access by bus size ..................................................................................................................	195
5.5	Wait Function........................................................................................................................		202
	5.5.1	Programmable wait function ....................................................................................................	202
	5.5.2	External wait function...............................................................................................................	203
	5.5.3	Relationship between programmable wait and external wait ...................................................	203
	5.5.4	Programmable address wait function.......................................................................................	204
5.6	Idle State Insertion Function ...............................................................................................		205
5.7	Bus Hold Function................................................................................................................		206
	5.7.1	Functional outline.....................................................................................................................	206
	5.7.2	Bus hold procedure..................................................................................................................	207
	5.7.3	Operation in power save mode ................................................................................................	207
5.8	Bus Priority ...........................................................................................................................		208
5.9	Bus Timing ............................................................................................................................		209
CHAPTER 6 CLOCK GENERATION FUNCTION ..............................................................................			212
6.1	Overview................................................................................................................................		212
6.2	Configuration ........................................................................................................................		213
6.3	Registers ...............................................................................................................................		215
6.4	Operation...............................................................................................................................		220
	6.4.1	Operation of each clock ...........................................................................................................	220
	6.4.2	Clock output function ...............................................................................................................	220
6.5	PLL Function.........................................................................................................................		221
10		User’s Manual U17717EJ3V0UD

	6.5.1	Overview .................................................................................................................................	221
	6.5.2	Registers .................................................................................................................................	221
	6.5.3	Usage ......................................................................................................................................	225
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................			226
7.1	Overview.................................................................................................................................		226
7.2	Functions ...............................................................................................................................		226
7.3	Configuration.........................................................................................................................		227
7.4	Registers ................................................................................................................................		229
7.5	Operation................................................................................................................................		243
	7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000).............................................................		244
	7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001).................................................		254
	7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010).....................................		262
	7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) ..............................................		274
	7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100)..............................................................		281
	7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) ....................................................		290
	7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) ........................................		307
	7.5.8	Timer output operations...........................................................................................................	313
7.6	Timer Tuned Operation Function ........................................................................................		314
7.7	Selector Function ..................................................................................................................		318
7.8	Cautions .................................................................................................................................		320
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................			321
8.1	Overview.................................................................................................................................		321
8.2	Functions ...............................................................................................................................		321
8.3	Configuration.........................................................................................................................		322
8.4	Registers ................................................................................................................................		325
8.5	Operation................................................................................................................................		343
	8.5.1 Interval timer mode (TQnMD2 to TQnMD0 bits = 000)............................................................		344
	8.5.2 External event count mode (TQnMD2 to TQnMD0 bits = 001) ................................................		353
	8.5.3 External trigger pulse output mode (TQnMD2 to TQnMD0 bits = 010) ....................................		362
	8.5.4 One-shot pulse output mode (TQnMD2 to TQnMD0 bits = 011) .............................................		375
	8.5.5 PWM output mode (TQnMD2 to TQnMD0 bits = 100).............................................................		384
	8.5.6 Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) ...................................................		395
	8.5.7 Pulse width measurement mode (TQnMD2 to TQnMD0 bits = 110)........................................		415
	8.5.8 Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111) ....................................................		421
	8.5.9	Timer output operations...........................................................................................................	422
8.6	Timer Tuned Operation Function ........................................................................................		423
8.7	Cautions .................................................................................................................................		427
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM).............................................................................			428
9.1	Overview.................................................................................................................................		428
9.2	Configuration.........................................................................................................................		429
9.3	Register ..................................................................................................................................		430
9.4	Operation................................................................................................................................		431
	9.4.1	Interval timer mode..................................................................................................................	431
	9.4.2	Cautions ..................................................................................................................................	435
		User’s Manual U17717EJ3V0UD	11

CHAPTER 10 WATCH TIMER FUNCTIONS ......................................................................................			436
10.1	Functions...............................................................................................................................		436
10.2	Configuration ........................................................................................................................		437
10.3	Registers ...............................................................................................................................		439
10.4	Operation...............................................................................................................................		443
	10.4.1	Operation as watch timer.........................................................................................................	443
	10.4.2	Operation as interval timer.......................................................................................................	444
	10.4.3	Cautions...................................................................................................................................	445
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 ...................................................................			446
11.1	Functions...............................................................................................................................		446
11.2	Configuration ........................................................................................................................		447
11.3	Registers ...............................................................................................................................		448
11.4	Operation...............................................................................................................................		451
CHAPTER 12 A/D CONVERTER .........................................................................................................			452
12.1	Overview................................................................................................................................		452
12.2	Functions...............................................................................................................................		452
12.3	Configuration ........................................................................................................................		453
12.4	Registers ...............................................................................................................................		456
12.5	Operation...............................................................................................................................		464
	12.5.1	Basic operation ........................................................................................................................	464
	12.5.2	Trigger mode ...........................................................................................................................	465
	12.5.3	Operation mode .......................................................................................................................	467
	12.5.4	Power-fail compare mode ........................................................................................................	471
12.6	Cautions ................................................................................................................................		476
12.7	How to Read A/D Converter Characteristics Table...........................................................		480
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) .............................................			484
13.1	Features.................................................................................................................................		485
13.2	Configuration ........................................................................................................................		486
13.3	Registers ...............................................................................................................................		488
13.4	Interrupt Request Signals....................................................................................................		494
13.5	Operation...............................................................................................................................		495
	13.5.1	Data format ..............................................................................................................................	495
	13.5.2	SBF transmission/reception format..........................................................................................	497
	13.5.3	SBF transmission.....................................................................................................................	499
	13.5.4	SBF reception ..........................................................................................................................	500
	13.5.5	UART transmission..................................................................................................................	501
	13.5.6	Continuous transmission procedure.........................................................................................	502
	13.5.7	UART reception .......................................................................................................................	504
	13.5.8	Reception errors ......................................................................................................................	505
	13.5.9	Parity types and operations .....................................................................................................	507
	13.5.10	Receive data noise filter...........................................................................................................	508
13.6	Dedicated Baud Rate Generator .........................................................................................		509
13.7	Cautions ................................................................................................................................		517
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)....................................................			518
12		User’s Manual U17717EJ3V0UD

14.1	Features..................................................................................................................................		518
14.2	Configuration.........................................................................................................................		519
14.3	Registers ................................................................................................................................		521
14.4	Interrupt Request Signals.....................................................................................................		528
14.5	Operation................................................................................................................................		529
	14.5.1	Single transfer mode (master mode, transmission mode) .......................................................	529
	14.5.2	Single transfer mode (master mode, reception mode).............................................................	531
	14.5.3	Single transfer mode (master mode, transmission/reception mode)........................................	533
	14.5.4	Single transfer mode (slave mode, transmission mode)..........................................................	535
	14.5.5	Single transfer mode (slave mode, reception mode) ...............................................................	537
	14.5.6	Single transfer mode (slave mode, transmission/reception mode) ..........................................	539
	14.5.7	Continuous transfer mode (master mode, transmission mode) ...............................................	541
	14.5.8	Continuous transfer mode (master mode, reception mode).....................................................	543
	14.5.9	Continuous transfer mode (master mode, transmission/reception mode)................................	546
	14.5.10	Continuous transfer mode (slave mode, transmission mode)..................................................	550
	14.5.11	Continuous transfer mode (slave mode, reception mode) .......................................................	552
	14.5.12	Continuous transfer mode (slave mode, transmission/reception mode) ..................................	555
	14.5.13	Reception error........................................................................................................................	559
	14.5.14	Clock timing.............................................................................................................................	560
14.6	Output Pin Status with Operation Disabled .......................................................................		562
14.7	Baud Rate Generator ............................................................................................................		563
	14.7.1	Baud rate generation ...............................................................................................................	564
14.8	Cautions .................................................................................................................................		565
CHAPTER 15 DMA FUNCTION (DMA CONTROLLER) ....................................................................			566
15.1	Features..................................................................................................................................		566
15.2	Configuration.........................................................................................................................		567
15.3	Registers ................................................................................................................................		568
15.4	Transfer Targets ....................................................................................................................		576
15.5	Transfer Modes......................................................................................................................		576
15.6	Transfer Types.......................................................................................................................		577
15.7	DMA Channel Priorities ........................................................................................................		578
15.8	Time Related to DMA Transfer.............................................................................................		578
15.9	DMA Transfer Start Factors .................................................................................................		579
15.10	DMA Abort Factors................................................................................................................		580
15.11	End of DMA Transfer.............................................................................................................		580
15.12	Operation Timing...................................................................................................................		580
15.13	Cautions .................................................................................................................................		585
CHAPTER 16 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................			590
16.1	Features..................................................................................................................................		590
16.2	Non-Maskable Interrupts ......................................................................................................		594
	16.2.1	Operation.................................................................................................................................	596
	16.2.2	Restore....................................................................................................................................	597
	16.2.3	NP flag.....................................................................................................................................	598
16.3	Maskable Interrupts ..............................................................................................................		599
	16.3.1	Operation.................................................................................................................................	599
	16.3.2	Restore....................................................................................................................................	601
		User’s Manual U17717EJ3V0UD	13

	16.3.3 Priorities of maskable interrupts...............................................................................................		602
	16.3.4 Interrupt control register (xxICn) ..............................................................................................		606
	16.3.5 Interrupt mask registers 0 to 4 (IMR0 to IMR4)........................................................................		608
	16.3.6 In-service priority register (ISPR).............................................................................................		610
	16.3.7	ID flag ......................................................................................................................................	611
	16.3.8 Watchdog timer mode register 2 (WDTM2) .............................................................................		611
16.4	Software Exception ..............................................................................................................		612
	16.4.1	Operation.................................................................................................................................	612
	16.4.2	Restore ....................................................................................................................................	613
	16.4.3	EP flag .....................................................................................................................................	614
16.5	Exception Trap......................................................................................................................		615
	16.5.1	Illegal opcode definition ...........................................................................................................	615
	16.5.2	Debug trap ...............................................................................................................................	617
16.6	External Interrupt Request Input Pins (NMI and INTP0 to INTP14) .................................		619
	16.6.1	Noise elimination .....................................................................................................................	619
	16.6.2	Edge detection.........................................................................................................................	619
16.7	Interrupt Acknowledge Time of CPU ..................................................................................		628
16.8	Periods in Which Interrupts Are Not Acknowledged by CPU..........................................		629
16.9	Cautions ................................................................................................................................		629
CHAPTER 17 KEY INTERRUPT FUNCTION .....................................................................................			630
17.1	Function.................................................................................................................................		630
17.2	Register .................................................................................................................................		631
17.3	Cautions ................................................................................................................................		631
CHAPTER 18 STANDBY FUNCTION ..................................................................................................			632
18.1	Overview................................................................................................................................		632
18.2	Registers ...............................................................................................................................		634
18.3	HALT Mode............................................................................................................................		637
	18.3.1 Setting and operation status ....................................................................................................		637
	18.3.2	Releasing HALT mode.............................................................................................................	637
18.4	IDLE1 Mode ...........................................................................................................................		639
	18.4.1 Setting and operation status ....................................................................................................		639
	18.4.2	Releasing IDLE1 mode ............................................................................................................	639
18.5	IDLE2 Mode ...........................................................................................................................		641
	18.5.1 Setting and operation status ....................................................................................................		641
	18.5.2	Releasing IDLE2 mode ............................................................................................................	641
	18.5.3 Securing setup time when releasing IDLE2 mode ...................................................................		643
18.6	STOP Mode............................................................................................................................		644
	18.6.1 Setting and operation status ....................................................................................................		644
	18.6.2	Releasing STOP mode ............................................................................................................	644
	18.6.3 Securing oscillation stabilization time when releasing STOP mode .........................................		646
18.7	Subclock Operation Mode ...................................................................................................		647
	18.7.1 Setting and operation status ....................................................................................................		647
	18.7.2 Releasing subclock operation mode ........................................................................................		647
18.8	Sub-IDLE Mode .....................................................................................................................		649
	18.8.1 Setting and operation status ....................................................................................................		649
	18.8.2	Releasing sub-IDLE mode .......................................................................................................	650
14		User’s Manual U17717EJ3V0UD

	CHAPTER 19 RESET FUNCTIONS......................................................................................................					652
	19.1	Overview.................................................................................................................................				652
	19.2	Registers to Check Reset Source........................................................................................				653
	19.3	Operation................................................................................................................................				654

		19.3.1 Reset operation via		RESET	...............................................................................................pin	654
		19.3.2 Reset operation by watchdog timer 2 ......................................................................................				656
		19.3.3 Reset operation by power-on clear circuit................................................................................				657
		19.3.4 Reset operation by low-voltage detector..................................................................................				657
		19.3.5 Reset operation by clock monitor ............................................................................................				657
<R>	19.4	Operation After Reset Release ............................................................................................				658
	CHAPTER 20 CLOCK MONITOR .........................................................................................................					660
	20.1	Functions ...............................................................................................................................				660
	20.2	Configuration.........................................................................................................................				660
	20.3	Register ..................................................................................................................................				661
	20.4	Operation................................................................................................................................				662
	CHAPTER 21 POWER-ON CLEAR CIRCUIT .....................................................................................					665
	21.1	Function .................................................................................................................................				665
	21.2	Configuration.........................................................................................................................				665
	21.3	Operation................................................................................................................................				666
	CHAPTER 22 LOW-VOLTAGE DETECTOR........................................................................................					667
	22.1	Functions ...............................................................................................................................				667
	22.2	Configuration.........................................................................................................................				667
	22.3	Registers ................................................................................................................................				668
	22.4	Operation................................................................................................................................				670
		22.4.1 To use for internal reset signal ................................................................................................				670
		22.4.2 To use for interrupt ..................................................................................................................				672
	22.5	RAM Retention Voltage Detection Operation.....................................................................				673
	22.6	Emulation Function...............................................................................................................				674
	CHAPTER 23 REGULATOR ..................................................................................................................					675
	23.1	Overview.................................................................................................................................				675
	23.2	Operation................................................................................................................................				676
	CHAPTER 24 FLASH MEMORY...........................................................................................................					677
	24.1	Features..................................................................................................................................				677
<R>	24.2	Memory Configuration..........................................................................................................				678
<R>	24.3	Functional Outline.................................................................................................................				679
	24.4	Rewriting by Dedicated Flash Programmer .......................................................................				682
		24.4.1	Programming environment ......................................................................................................			682
		24.4.2	Communication mode..............................................................................................................			683
		24.4.3	Flash memory control ..............................................................................................................			688
		24.4.4 Selection of communication mode...........................................................................................				689
		24.4.5	Communication commands .....................................................................................................			690
		24.4.6	Pin connection .........................................................................................................................			691
	24.5	Rewriting by Self Programming...........................................................................................				695
				User’s Manual U17717EJ3V0UD		15

	24.5.1		Overview..................................................................................................................................	695
	24.5.2		Features...................................................................................................................................	696
	24.5.3 Standard self programming flow ..............................................................................................			697
	24.5.4		Flash functions.........................................................................................................................	698
	24.5.5		Pin processing .........................................................................................................................	698
	24.5.6		Internal resources used ...........................................................................................................	699
CHAPTER 25		OPTION BYTE FUNCTION ..........................................................................................		700
CHAPTER 26		ON-CHIP DEBUG FUNCTION .....................................................................................		702
26.1	Debugging with DCU............................................................................................................			703
	26.1.1		Connection circuit example......................................................................................................	703
	26.1.2		Interface signals.......................................................................................................................	703
	26.1.3		Maskable functions ..................................................................................................................	705
	26.1.4		Register ...................................................................................................................................	705
	26.1.5		Operation.................................................................................................................................	707
	26.1.6		Cautions...................................................................................................................................	708
26.2	Debugging Without Using DCU...........................................................................................			709
	26.2.1		Circuit connection examples ....................................................................................................	709
	26.2.2		Maskable functions ..................................................................................................................	710
	26.2.3 Securement of user resources.................................................................................................			711
	26.2.4		Cautions...................................................................................................................................	717
26.3	ROM Security Function........................................................................................................			718
	26.3.1		Security ID ...............................................................................................................................	718
	26.3.2		Setting .....................................................................................................................................	719
CHAPTER 27		ELECTRICAL SPECIFICATIONS.................................................................................		721
27.1	Electrical Specifications ......................................................................................................			721
27.2	Capacitance...........................................................................................................................			723
27.3	Operating Conditions...........................................................................................................			723
27.4	Oscillator Characteristics....................................................................................................			724
	27.4.1 Main clock oscillator characteristics.........................................................................................			724
	27.4.2		Subclock oscillator characteristics ...........................................................................................	725
	27.4.3		PLL characteristics ..................................................................................................................	726
	27.4.4		Internal oscillator characteristics..............................................................................................	726
27.5	Voltage Regulator Characteristics......................................................................................			726
27.6	DC Characteristics ...............................................................................................................			727
	27.6.1		I/O level ...................................................................................................................................	727
	27.6.2		Pin leakage current..................................................................................................................	728
	27.6.3		Supply current..........................................................................................................................	729
27.7	Data Retention Characteristics ...........................................................................................			731
27.8	AC Characteristics ...............................................................................................................			732
	27.8.1		CLKOUT Output Timing...........................................................................................................	733
	27.8.2		Bus Timing...............................................................................................................................	734
27.9	Basic Operation ....................................................................................................................			739
27.10	Flash Memory Programming Characteristics....................................................................			746
CHAPTER 28		PACKAGE DRAWING ..................................................................................................		747
16			User’s Manual U17717EJ3V0UD


<R>	CHAPTER 29		RECOMMENDED SOLDERING CONDITIONS ...........................................................	748
<R>	APPENDIX A		DEVELOPMENT TOOLS ...............................................................................................	749
	A.1	Software Package..................................................................................................................		751
	A.2	Language Processing Software...........................................................................................		751
	A.3	Control Software ...................................................................................................................		751
	A.4	Debugging Tools (Hardware) ...............................................................................................		752
		A.4.1 When using IECUBE QB-V850ESFX2 ....................................................................................		752
		A.4.2 When using MINICUBE QB-V850MINI....................................................................................		754
		A.4.3 When using MINICUBE2 QB-MINI2 ........................................................................................		755
	A.5	Debugging Tools (Software) ................................................................................................		756
	A.6	Embedded Software..............................................................................................................		757
	A.7	Flash Memory Writing Tools ................................................................................................		758
	APPENDIX B		REGISTER INDEX..........................................................................................................	759
	APPENDIX C		INSTRUCTION SET LIST..............................................................................................	770
	C.1	Conventions...........................................................................................................................		770
	C.2	Instruction Set (in Alphabetical Order) ...............................................................................		773
<R>	APPENDIX D		LIST OF CAUTIONS......................................................................................................	780
	APPENDIX E		REVISION HISTORY ......................................................................................................	814
	E.1 Major Revisions in This Edition...........................................................................................			814
	E.2 Revision History of Previous Editions................................................................................			815

User’s Manual U17717EJ3V0UD

CHAPTER 1 INTRODUCTION

The V850ES/HJ2 is one of the products in the NEC Electronics V850 single-chip microcontrollers designed for lowpower operation for real-time control applications.

1.1General

The V850ES/HJ2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, and an A/D converter.

In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/HJ2 features multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications.

Table 1-1 lists the products of the V850ES/HJ2.

18	User’s Manual U17717EJ3V0UD

CHAPTER 1 INTRODUCTION

Table 1-1. V850ES/HJ2 Product List

	Part Number	μPD70F3709	μPD70F3710		μPD70F3711		μPD70F3712

Internal	Flash memory	128 KB	256 KB		376 KB		512 KB
memory
memory	RAM	12 KB				20 KB
	RAM	12 KB				20 KB

Memory	Logical space			64 MB
space
space	External memory area			15 MB
	External memory area			15 MB
		Address bus: 16 bits
External bus interface		Address bus: 16 bits
		Data bus: 8/16 bits
		Multiplexed bus mode
		32 bits × 32 registers
General-purpose register		32 bits × 32 registers
		Ceramic/crystal/external clock
Main clock (oscillation frequency)		Ceramic/crystal/external clock

•In PLL mode: fX = 4 to 5 MHz

•In clock through mode: fX = 4 to 5 MHz

Subclock (oscillation frequency)	Crystal/external clock: fXT = 32.768 kHz
	RC oscillation: 20 kHz

Internal oscillator	fR = 200 kHz (TYP.)

Minimum instruction execution time	50 ns (main clock (fXX) = 20 MHz operation)
	32 × 32 = 64: 200 to 250 ns (at 20 MHz)
DSP function	32 × 32 = 64: 200 to 250 ns (at 20 MHz)
	32 × 32 + 32 = 32: 300 ns (at 20 MHz)
	16 × 16 = 32: 50 to 100 ns (at 20 MHz)
	16 × 16 + 32 = 32: 150 ns (at 20 MHz)

I/O port	I/O: 128
	16-bit timer/event counter P:				4 channels
Timer	16-bit timer/event counter P:				4 channels
	16-bit timer/event counter Q: 3 channels
	16-bit interval timer M:				1 channel
	Watchdog timer 2:				1 channel
	Watch timer:				1 channel
	10-bit resolution × 24 channels
A/D converter	10-bit resolution × 24 channels

Serial interface	CSIB:			3 channels		CSIB:	3 channels
	UARTA (for LIN):			3 channels		UARTA (for LIN):	4 channels

DMA controller	4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)

Interrupt source	External: 16 (16)Note, internal: 50					External: 16 (16)Note, internal: 52

Power save function	HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode

Reset
Reset		RESET	pin input, watchdog timer 2 (WDT2), clock monitor (CLM), POC circuit, low-voltage
	detector (LVI)

DCU	Provided (RUN/break)

Operating power supply voltage	3.5 to 5.5 V (A/D converter: 4.0 to 5.5 V)
	−40 to +85°C
Operating ambient temperature	−40 to +85°C
	144-pin plastic LQFP (fine pitch) (20 × 20 mm)
Package	144-pin plastic LQFP (fine pitch) (20 × 20 mm)

Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.

User’s Manual U17717EJ3V0UD

CHAPTER 1 INTRODUCTION

1.2Features

Minimum instruction execution time: 50 ns (operating with main clock (fXX) of 20 MHz)

General-purpose registers:		32 bits × 32 registers
CPU features:		Signed multiplication (16		× 16 → 32): 1 to 2 clocks
		Signed multiplication (32		× 32 → 64): 1 to 5 clocks
		Saturated operations (overflow and underflow detection functions included)
		32-bit shift instruction: 1 clock
		Bit manipulation instructions
		Load/store instructions with long/short format
Memory space:		64 MB of linear address space (for programs and data)
		External expansion: Up to 256 KB (including 64 KB used as internal ROM/RAM)
•	Internal memory:	RAM:	12 KB/20 KB (see Table 1-1)
		Flash memory: 128		KB/256 KB/376 KB/512 KB (see Table 1-1)
•	External bus interface: Multiplexed bus output
		8-/16-bit data bus sizing function
		Wait function

•Programmable wait function

•External wait function

	Idle state function
	Bus hold function
Interrupts and exceptions:	Non-maskable interrupts:		2 sources
	Maskable interrupts:		64 sources (μPD70F3709, 70F3710)
			66 sources (μPD70F3711, 70F3712)
	Software exceptions:		32 sources
	Exception trap:		2 sources
I/O lines:	I/O ports:	128
Timer function:	16-bit interval timer M (TMM):			1 channel
	16-bit timer/event counter P (TMP):			4 channels
	16-bit timer/event counter Q (TMQ):			3 channels
	Watch timer:			1 channel
	Watchdog timer 2:			1 channel

Serial interface:	Asynchronous serial interface A (UARTA)
	3-wire variable-length serial interface B (CSIB)
	UARTA (supporting LIN):	4 channels (μPD70F3711, 70F3712)
		3 channels (μPD70F3709, 70F3710)
	CSIB:	3 channels
A/D converter:	10-bit resolution: 24 channels
DMA controller:	4 channels
DCU (debug control unit):	JTAG interface
Clock generator:	During main clock or subclock operation
	7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
	Clock-through mode/PLL mode selectable
Internal oscillation clock:	200 kHz (TYP.)
Power-save functions:	HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Package:	144-pin plastic LQFP (fine pitch) (20 × 20)

20	User’s Manual U17717EJ3V0UD

CHAPTER 1 INTRODUCTION

1.3Application Fields

Consumer devices

1.4Ordering Information

Part Number	Package	On-Chip Flash Memory
μPD70F3709GJ-UEN-A	144-pin plastic LQFP (fine pitch) (20 × 20)	128 KB
μPD70F3710GJ-UEN-A	144-pin plastic LQFP (fine pitch) (20 × 20)	256 KB
μPD70F3711GJ-UEN-A	144-pin plastic LQFP (fine pitch) (20 × 20)	376 KB
μPD70F3712GJ-UEN-A	144-pin plastic LQFP (fine pitch) (20 × 20)	512 KB

Remark Products with -A at the end of the part number are lead-free products.

User’s Manual U17717EJ3V0UD

CHAPTER 1 INTRODUCTION

1.5Pin Configuration (Top View)

144-pin plastic LQFP (fine pitch) (20 × 20)

μPD70F3709GJ-UEN-A	μPD70F3710GJ-UEN-A
μPD70F3711GJ-UEN-A	μPD70F3712GJ-UEN-A

AVREF0

AVSS P10/INTP9 P11/INTP10 EVDD

P00/TIP31/TOP31

P01/TIP30/TOP30 FLMD0Note 1

VDD

REGCNote 2

VSS

X2 RESET XT1 XT2 P02/NMI

P03/INTP0/ADTRG

P04/INTP1

P05/INTP2/DRST

P06/INTP3

P40/SIB0

P41/SOB0

P42/SCKB0

P30/TXDA0

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/TOP00/TOP01

P33/TIP01/TOP01

P34/TIP10/TOP10

P35/TIP11/TOP11

P36

P37

EVSS

EVDD P38/TXDA2 P39/RXDA2/INTP8

144 P70/ANI0 143 P71/ANI1 142 P72/ANI2 141 P73/ANI3 140 P74/ANI4 139 P75/ANI5 138 P76/ANI6 137 P77/ANI7

P50/KR0/TIQ01/TOQ01 37 P51/KR1/TIQ02/TOQ02 38 P52/KR2/TIQ03/TOQ03/DDI 39 P53/KR3/TIQ00/TOQ00/DDO 40 P54/KR4/DCK 41 P55/KR5/DMS 42 P60/INTP11 43 P61/INTP12 44

136 P78/ANI8 135 P79/ANI9

P62/INTP13 45 P63 46

134 P710/ANI10 133 P711/ANI11 132 P712/ANI12 131 P713/ANI13 130 P714/ANI14

P64 47 P65 48 P66 49 P67 50 P68 51

129 P715/ANI15

P69 52

128 P120/ANI16 127 P121/ANI17 126 P122/ANI18

P610/TIQ20/TOQ20 53 P611/TIQ21/TOQ21 54 P612/TIQ22/TOQ22 55

125 P123/ANI19 124 P124/ANI20 123 P125/ANI21 122 P126/ANI22 121 P127/ANI23 120 PDL15/AD15 119 PDL14/AD14 118 PDL13/AD13

56 57 58 59 60 61 62 63
P613/TIQ23/TOQ23	P614 P615 P80/RXDA3	P81/TXDA3	P90/KR6/TXDA1 P91/KR7/RXDA1 P92/TIQ11/TOQ11
	/INTP14	3 Note
	Note3

117 PDL12/AD12

P93/TIQ12/TOQ12 64

116 PDL11/AD11 115 PDL10/AD10

P94/TIQ13/TOQ13 65 P95/TIQ10/TOQ10 66

114 PDL9/AD9

P96/TIP21/TOP21 67

113 PDL8/AD8 112 PDL7/AD7 111 PDL6/AD6

P97/SIB1/TIP20/TOP20 68 P98/SOB1 69 P99/SCKB1 70

110 PDL5/AD5/FLMD1

P910/SIB2 71

PDL4/AD4
109	108
	108
	107
	106
	105
	104
	103
	102
	101
	100
	99
	98
	97
	96
	95
	94
	93
	92
	91
	90
	89
	88
	87
	86
	85
	84
	83
	82
	81
	80
	79
	78
	77
	76
	75
	74
	73
72
P911/SOB2

Notes 1. Connect this pin to VSS in the normal mode.

2.Connect the REGC pin to VSS via a 4.7 μF (recommended value) capacitor.

3.μPD70F3711, 70F3712 only

PDL3/AD3

PDL2/AD2

PDL1/AD1

PDL0/AD0

BVDD

BVSS

PCT7

PCT6/ASTB

PCT5

PCT4/RD

PCT3

PCT2

PCT1/WR1

PCT0/WR0

PCS7

PCS6

PCS5

PCS4

PCM5

PCM4

PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PCS3/CS3 PCS2/CS2 PCS1/CS1 PCS0/CS0 PCD3

PCD2

PCD1

PCD0

P915/INTP6

P914/INTP5 P913/INTP4/PCL P912/SCKB2

22	User’s Manual U17717EJ3V0UD

CHAPTER 1 INTRODUCTION

Pin identification

AD0 to AD15:

Address/data bus

PCL:

Programmable clock output

ADTRG:

A/D trigger input

PCM0 to PCM5:

Port CM

ANI0 to ANI23:

Analog input

PCS0 to PCS7:

Port CS

ASCKA0:

Asynchronous serial clock

PCT0 to PCT7:

Port CT

ASTB:

Address strobe

PDL0 to PDL15:

Port DL

AVREF0:

Analog reference voltage

RD:

Read strobe

AVSS:

Analog VSS

REGC:

Regulator control

BVDD:

Power supply for bus interface

RESET:

Reset

BVSS:

Ground for bus interface

RXDA0 to RXDA3:

Receive data

CLKOUT:

Clock output

SCKB0

SCKB2:

Serial clock

Chip select

SIB0 to SIB2:

Serial input

CS0 to CS3:

DCK:

Debug clock

SOB0 to SOB2:

Serial output

DDI:

Debug data input

TIP00, TIP01,

DDO:

Debug data output

TIP10, TIP11,

DMS:

Debug mode select

TIP20, TIP21,

Debug reset

TIP30, TIP31,

DRST:

EVDD:

Power supply for port

TIQ00 to TIQ03,

EVSS:

Ground for port

TIQ10 to TIQ13,

FLMD0, FLMD1:

Flash programming mode

TIQ20 to TIQ23:

Timer input

Hold acknowledge

TOP00, TOP01,

HLDAK:

Hold request

TOP10, TOP11,

HLDRQ:

INTP0 to INTP14:

External interrupt request

TOP20, TOP21,

KR0 to KR7:

Key return

TOP30, TOP31,

NMI:

Non-maskable interrupt request

TOQ00 to TOQ03,

P00 to P06:

Port 0

TOQ10 to TOQ13,

P10, P11:

Port 1

TOQ20 to TOQ23:

Timer output

P30 to P39:

Port 3

TXDA0 to TXDA3:

Transmit data

P40 to P42:

Port 4

VDD:

Power supply

P50 to P55:

Port 5

VSS:

Ground

Wait

P60 to P615:

Port 6

WAIT:

P70 to P715:

Port 7

Write strobe low level data

WR0:

P80, P81:

Port 8

Write strobe high level data

WR1:

P90 to P915:

Port 9

X1, X2:

Crystal for main clock

P120 to P127:

Port 12

XT1, XT2:

Crystal for subclock

PCD0 to PCD3:

Port CD

User’s Manual U17717EJ3V0UD

NEC PD70F3709, PD70F3710, PD70F3711, PD70F3712 User Guide

CHAPTER 1 INTRODUCTION

1.6Function Block Configuration

1.6.1Internal block diagram

			Flash
	NMI	memory			CPU
	NMI	INTC
INTP0 to INTP14		INTC						Instruction
INTP0 to INTP14			Note 1	PC				Instruction
			Note 1	PC				queue
				32-bit barrel	Multiplier				HLDRQ
TIQ00 to TIQ03			RAM	32-bit barrel	Multiplier				HLDAK
TIQ00 to TIQ03				shifter	16 × 16 → 32				ASTB
TIQ10 to TIQ13				shifter	16 × 16 → 32				ASTB
TIQ10 to TIQ13									RD
TIQ20 to TIQ23		16-bit timer/							RD
TIQ20 to TIQ23				System				BCU	WAIT
			Note 2	System				BCU	WAIT
		counter Q:	Note 2	registers					WR0, WR1
		counter Q:
TOQ00 to TOQ03		3 ch			ALU

									AD0 to AD15
TOQ10 to TOQ13				General-purpose					AD0 to AD15
TOQ10 to TOQ13									CS0 to CS3
TOQ20 to TOQ23
TOQ20 to TOQ23		DMAC		registers 32 bits × 32
				registers 32 bits × 32

TIP00 to TIP30,		16-bit timer/
TIP01 to TIP31		16-bit timer/
TIP01 to TIP31		counter P:
TOP00 to TOP30,		counter P:
TOP00 to TOP30,		4 ch
TOP01 to TOP31
		16-bit
		interval							CLKOUT
		timer M:		Ports	Internal	oscillator			CLKOUT
		1 ch					CLM	CG	XT1
									XT1
									XT2
									XT2
SIB0 to SIB2									X1
SIB0 to SIB2								PLL	X1
								PLL	X2
SOB0 to SOB2		CSIB: 3 ch							X2
SOB0 to SOB2		CSIB: 3 ch							RESET
SCKB0 to SCKB2		PCS0PCS7to	PCM0PCM5to PCT0PCT7to PDH0PDH7to PDL0PDL15to PCD0PCD3to P90P915to	P80,P81 P70P715to P60P615to P50P55to P40P42to P30P39to P10,P11	P00P06to				RESET
SCKB0 to SCKB2								LVI
								LVI
TXDA0 to TXDA3Note 3								POC
TXDA0 to TXDA3Note 3				ANI0 to ANI23				POC
RXDA0 to RXDA3Note 3		UARTA:		ANI0 to ANI23					VDD
			A/D	AVSS					VDD
				AVSS
		4 chNote 3		AVREF0				Regulator	VSS
	ASCK0		converter	AVREF0				Regulator	VSS
	ASCK0			ADTRG					REGC
				ADTRG					REGC
		Watchdog	Key return						FLMD0
		Watchdog	Key return	KR0 to KR7					FLMD1
		timer 2	function	KR0 to KR7					FLMD1
									BVDD
		Watch timer		DRST					BVSS
				DRST					EVDD
				DMS					EVDD
				DMS					EVSS
			DCU	DDI					EVSS
			DCU	DDI
				DCK
				DDO
Notes 1.	μPD70F3709: 128 KB
	μPD70F3710: 256 KB
	μPD70F3711: 376 KB
	μPD70F3712: 512 KB
2.	μPD70F3709, 70F3710: 12 KB
	μPD70F3711, 70F3712: 20 KB
3.	μPD70F3709, 70F3710: 3 channels
24		User’s Manual U17717EJ3V0UD

CHAPTER 1 INTRODUCTION

1.6.2Internal units

(1)CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic

logic operations, data transfers, and almost all other instruction processing.

Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing.

(2)Bus control unit (BCU)

The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an instruction queue.

(3)ROM

This is a 512 KB/376 KB/256 KB/128 KB flash memory mapped to addresses 0000000H to 007FFFFH/0000000H to 005DFFFH/0000000H to 003FFFFH/0000000H to 001FFFFH. It can be accessed from the CPU in one clock during instruction fetch.

(4)RAM

This is a 20 KB/12 KB RAM mapped to addresses 3FFA000H to 3FFEFFFH/3FFC000H to 3FFEFFFH. It can be accessed from the CPU in one clock during data access.

(5)Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP0 to INTP14) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple servicing control can be performed.

(6)Clock generator (CG)

A main clock oscillator that generates the main clock oscillation frequency (fX) and a subclock oscillator that generates the subclock oscillation frequency (fXT) are available. As the main clock frequency (fXX), fX is used as is in the clock-through mode and is multiplied by four in the PLL mode.

The CPU clock frequency (fCPU) can be selected from seven types: fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.

(7)Internal oscillator

An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP.). An internal oscillator supplies the clock for watchdog timer 2 and timer M.

(8)Timer/counter

Four-channel 16-bit timer/event counter P (TMP), three-channel 16-bit timer/event counter Q (TMQ), and onechannel 16-bit interval timer M (TMM) are provided on chip.

(9)Watch timer

This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz from the subclock or the 32.768 kHz fBRG from prescaler 3). The watch timer can also be used as an interval timer for the main clock.

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CHAPTER 1 INTRODUCTION

(10)Watchdog timer 2

A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. Either the internal oscillation clock or the main clock can be selected as the source clock.

Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs.

(11)Serial interface

The V850ES/HJ2 includes three kinds of serial interfaces: asynchronous serial interface A (UARTA) and 3- wire variable-length serial interface B (CSIB).

In the case of UARTA, data is transferred via the TXDAn and RXDAn pins. (n = 0 to 3: μPD70F3711, 70F3712, n = 0 to 2: μPD70F3709, 70F3710)

In the case of CSIB, data is transferred via the SOB0 to SOB3 pins, SIB0 to SIB3 pins, and SCKB0 to SCKB3 pins.

(12)A/D converter

This 10-bit A/D converter includes 24 analog input pins. Conversion is performed using the successive approximation method.

(13)DMA controller

A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.

(14)Key interrupt function

A key interrupt request signal (INTKR) can be generated by inputting a falling edge to key input pins (8 channels).

(15)DCU (debug control unit)

An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip debugging function is done with the control pin input level and the on-chip debug mode register (OCDM).

(16)Ports

The general-purpose port functions and control pin functions are provided. For details, see CHAPTER 4 PORT FUNCTIONS.

26	User’s Manual U17717EJ3V0UD

CHAPTER 2 PIN FUNCTIONS

This section explains the names and functions of the pins of the V850ES/HJ2.

2.1Pin Function List

Three I/O buffer power supplies, AVREF0, BVDD, and EVDD, are available. The relationship between the power supplies and the pins is shown below.

	Table 2-1. Pin I/O Buffer Power Supplies

Power Supply	Corresponding Pin

AVREF0	Port 7, port 12

BVDD	Port CD, port CM, port CS, port CT, port DL


EVDD	Port 0, port 1, port 3, port 4, port 5, port 6, port 8, port 9,	RESET

(1) Port pins

			Table 2-2. List of Pins (Port Pins) (1/4)

Pin Name	Pin No.	I/O	Function

P00	6	I/O	Port 0
			7-bit I/O port
P01	7		7-bit I/O port
P01	7		Input/output can be specified in 1-bit units.

P02	17
P02	17

P03	18

P04	19

P05	20

P06	21

P10	3	I/O	Port 1
			2-bit I/O port
P11	4		2-bit I/O port
P11	4		Input/output can be specified in 1-bit units.
			Input/output can be specified in 1-bit units.

P30	25	I/O	Port 3
			10-bit I/O port
P31	26		10-bit I/O port
P31	26		Input/output can be specified in 1-bit units.

P32	27
P32	27

P33	28

P34	29

P35	30

P36	31

P37	32

P38	35

P39	36

P40	22	I/O	Port 4
			3-bit I/O port
P41	23		3-bit I/O port
P41	23		Input/output can be specified in 1-bit units.

P42	24
P42	24

Alternate Function TIP31/TOP31 TIP30/TOP30

NMI

INTP0/ADTRG

INTP1

INTP2/DRST

INTP3

INTP9

INTP10

TXDA0

RXDA0/INTP7

ASCKA0/TIP00/TOP00/TOP01

TIP01/TOP01

TIP10/TOP10

TIP11/TOP11

−

TXDA2

RXDA2/INTP8

SIB0

SOB0

SCKB0

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CHAPTER 2 PIN FUNCTIONS

Table 2-2. List of Pins (Port Pins) (2/4)

Pin Name	Pin No.	I/O	Function	Alternate Function

P50	37	I/O	Port 5	KR0/TIQ01/TOQ01
			6-bit I/O port
P51	38		6-bit I/O port	KR1/TIQ02/TOQ02
P51	38		Input/output can be specified in 1-bit units.	KR1/TIQ02/TOQ02

P52	39			KR2/TIQ03/TOQ03/DDI
P52	39			KR2/TIQ03/TOQ03/DDI

P53	40			KR3/TIQ00/TOQ00/DDO

P54	41			KR4/DCK

P55	42			KR5/DMS

P60	43	I/O	Port 6	INTP11
			16-bit I/O port
P61	44		16-bit I/O port	INTP12
P61	44		Input/output can be specified in 1-bit units.	INTP12

P62	45			INTP13
P62	45			INTP13

P63	46			–

P64	47			–

P65	48			–

P66	49			–

P67	50			–

P68	51			–

P69	52			–

P610	53			TIQ20/TOQ20

P611	54			TIQ21/TOQ21

P612	55			TIQ22/TOQ22

P613	56			TIQ23/TOQ23

P614	57			–

P615	58			–

P70	144	I/O	Port 7	ANI0
			16-bit I/O port
P71	143		16-bit I/O port	ANI1
P71	143		Input/output can be specified in 1-bit units.	ANI1

P72	142			ANI2
P72	142			ANI2

P73	141			ANI3

P74	140			ANI4

P75	139			ANI5

P76	138			ANI6

P77	137			ANI7

P78	136			ANI8

P79	135			ANI9

P710	134			ANI10

P711	133			ANI11

P712	132			ANI12

P713	131			ANI13

P714	130			ANI14

P715	129			ANI15

28	User’s Manual U17717EJ3V0UD

CHAPTER 2 PIN FUNCTIONS

Table 2-2. List of Pins (Port Pins) (3/4)

Pin Name	Pin No.	I/O	Function				Alternate Function
				RXDA3Note/INTP14
P80	59	I/O	Port 8	RXDA3Note/INTP14
			2-bit I/O port	TXDA3		Note
P81	60		2-bit I/O port			Note
P81	60		Input/output can be specified in 1-bit units.
			Input/output can be specified in 1-bit units.

P90	61	I/O	Port 9	KR6/TXDA1
			16-bit I/O port
P91	62		16-bit I/O port	KR7/RXDA1
P91	62		Input/output can be specified in 1-bit units.	KR7/RXDA1

P92	63			TIQ11/TOQ11
P92	63			TIQ11/TOQ11

P93	64			TIQ12/TOQ12

P94	65			TIQ13/TOQ13

P95	66			TIQ10/TOQ10

P96	67			TIP21/TOP21

P97	68			SIB1/TIP20/TOP20

P98	69			SOB1


P99	70			SCKB1

P910	71			SIB2

P911	72			SOB2


P912	73			SCKB2

P913	74			INTP4/PCL

P914	75			INTP5

P915	76			INTP6

P120	128	I/O	Port 12	ANI16
			8-bit I/O port
P121	127		8-bit I/O port	ANI17
P121	127		Input/output can be specified in 1-bit units.	ANI17

P122	126			ANI18
P122	126			ANI18

P123	125			ANI19

P124	124			ANI20

P125	123			ANI21

P126	122			ANI22

P127	121			ANI23

PCD0	77	I/O	Port CD				–
			4-bit I/O port
PCD1	78		4-bit I/O port				–
PCD1	78		Input/output can be specified in 1-bit units.				–

PCD2	79						–
PCD2	79						–

PCD3	80						–

PCM0	85	I/O	Port CM
PCM0	85	I/O	Port CM		WAIT
			6-bit I/O port
PCM1	86		6-bit I/O port	CLKOUT
PCM1	86		Input/output can be specified in 1-bit units.	CLKOUT


PCM2	87			HLDAK
PCM2	87			HLDAK


PCM3	88			HLDRQ

PCM4	89						–

PCM5	90						–

Note μPD70F3711, 70F3712 only

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CHAPTER 2 PIN FUNCTIONS

Table 2-2. List of Pins (Port Pins) (4/4)

Pin Name

Pin No.

I/O

Function

Alternate Function

I/O

Port CS

PCS0

CS0

8-bit I/O port

PCS1

CS1

Input/output can be specified in 1-bit units.

PCS2

CS2

PCS3

CS3

PCS4

–

PCS5

–

PCS6

–

PCS7

–

PCT0

I/O

Port CT

WR0

8-bit I/O port

PCT1

WR1

Input/output can be specified in 1-bit units.

PCT2

–

PCT3

–

PCT4

PCT5

100

–

PCT6

101

ASTB

PCT7

102

–

PDL0

105

I/O

Port DL

AD0

16-bit I/O port

PDL1

106

AD1

Input/output can be specified in 1-bit units.

PDL2

107

AD2

PDL3

108

AD3

PDL4

109

AD4

PDL5

110

AD5/FLMD1

PDL6

111

AD6

PDL7

112

AD7

PDL8

113

AD8

PDL9

114

AD9

PDL10

115

AD10

PDL11

116

AD11

PDL12

117

AD12

PDL13

118

AD13

PDL14

119

AD14

PDL15

120

AD15

30	User’s Manual U17717EJ3V0UD

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