Page 1
I2C Bus-Compatible Video Switch
For the availability of this product, please contact the sales office.
Description
The CXA2040Q is an I2C bus-compatible 5-input,
3-output video switch for TVs.
Features
• Serial data control via I2C bus
• 5 composite video input systems
• 2 Y/C (S terminal) input systems
• 3 composite video output systems
• 1 Y/C (S terminal) output system
• Input can be selected independently for each
output system.
• SYNC_ID function for CV1 system input
• Built-in 6dB amplifier for CVOUT2 system output
• Built-in Y/C MIX circuit
• Slave address can be changed (90H/92H).
• High impedance maintained by I2C bus line (SDA,
SCL) even when power is OFF.
Applications
TVs
Pin Configuration (Top View)
CXA2040Q
32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VCC 12 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 1.0 W
(when mounted on a 50mm × 50mm board)
Operating Conditions
Supply voltage VCC 9.0 ± 0.5 V
Structure
Bipolar silicon monolithic IC
CV2
CC
V
CV3
NC
CV4
GND
CV5
BIAS
25
26
27
28
29
30
31
32
24
NC
23
1
2
Y1
CV1
NC
SYNCTC
22
3
C1
21
4
SDA
S1
20
5
SCL
Y2
19
6
ADR
S2
18
NC
CVOUT1
17
NC
16
CVOUT2
15
NC
14
13
CVOUT3
12
NC
YOUT
11
10
NC
9
COUT
8
7
C2
NC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95Z44-ST
Page 2
Block Diagram
30
GND
26
CXA2040Q
CC
V
SCL
20
SDA
21
2
C BUS DECODER
I
19
ADR
S1
4
S2
6
SYNCTC
CV1
CV2
CV3
CV4
CV5
Y1
C1
22
23
25
27
29
31
SYNC DETECT
CV1
CV2
CV1
CV2
CV3
CV4
CV5
1
3
CV6
CV3
CV4
CV5
CV6
CV7
MUTE
CV1
CV2
CV3
CV4
CV5
CV6
CV7
MUTE
CV1
CV2
CV3
CV4
CV5
CV6
CV7
MUTE
SW1
SW2
SW3
6dB
17
15
13
CVOUT1
CVOUT2
CVOUT3
5
Y2
C2
7
32
BIAS
∗
Numbers inside circles indicate the IC pin numbers.
BIAS
CV7
MUTE
Y1
Y2
MUTE
C1
C2
MUTE
– 2 –
SW4
SW5
11
9
YOUT
COUT
Page 3
Pin Description
Pin
Symbol Pin voltage Equivalent circuit Description
No.
1
Y1
5
Y2
3
C1
7
C2
46S1
S2
4.5V
CXA2040Q
V
CC
Y/C separation signal inputs.
Biased to approximately 4.5V.
1
5
3
7
20k
147
× 2
28k
Input the input signals through
capacitors. Connect protective
resistor of 220Ω between these
pins and the capacitors.
Y1 and Y2 pins: Luminance
signals input.
C1 and C2 pins: Chrominance
signals input.
CC
V
Applying a DC voltage to S1 and
S2 pins allows these voltages to
be applied to the microcomputer
50k
50k
4
6
100k
× 4
as the I2C bus status register data.
S1, S2 = 0 to 2V
OPEN = 0, SEL = 1
S1, S2 = 4.75 to 7.25V
OPEN = 0, SEL = 0
S1, S2 = 9.5 to 12V
OPEN = 1, SEL = 0
119YOUT
COUT
17
CVOUT1
15
CVOUT2
13
CVOUT3
4.5V
4.5V
200 1.2k
× 5
11
× 6
9
200 1.2k
× 5
17
15
× 6
13
× 2
× 2
× 2
× 2
VCC
Y/C signal outputs.
YOUT pin: Luminance signal
output.
COUT pin: Chrominance signal
output.
VCC
Composite video signal outputs.
CVOUT1, CVOUT2:
0dB output with respect to
the input signal.
CVOUT2:
+6dB output with respect
to the input signal.
– 3 –
Page 4
Pin
Symbol Pin voltage Equivalent circuit Description
No.
VCC
CXA2040Q
19 ADR
20 SCL —
20
19
× 4
72k
28k
4k
Selects the slave address for the
I2C bus.
90H at 1.0V or less
92H at 3.5V or more
90H when open
V
CC
I2C bus signal input.
Connect protective resistor of
220Ω between this pin and the
SCL line.
21 SDA —
22 SYNCTC
22
21
× 6
147
147
1.2k
4k
1.2k
CC
V
I2C bus signal input.
Connect protective resistor of
220Ω between this pin and the
SDA line.
CC
V
Sync tip clamp time constant for
Sync Separation.
Connect 68kΩ resistor between
this pin and VCC.
Connect 10µF capacitor between
this pin and GND.
– 4 –
Page 5
Pin
Symbol Pin voltage Equivalent circuit Description
No.
CXA2040Q
23 CV1 4.5V
25
CV2
27
29
31
CV3
CV4
CV5
4.5V
23
25
27
29
31
20k
147
28k
20k
147
28k
V
CC
Composite video signal input.
Biased to approximately 4.5V.
Input the input signal through
capacitor. Connect protective
resistor of 220Ω between this pin
and the capacitor.
The composite video signal input
to CV1 is also taken into the
"SYNC DETECT circuit" of which
SYNC is existed or not.
V
CC
Composite video signal input.
Biased to approximately 4.5V.
Input the input signals through
capacitors. Connect protective
resistor of 220Ω between these
pins and the capacitors.
26 VCC
30 GND
32
BIAS
2
8
10
12
14
NC
16
18
24
28
9.0V
0.0V
4.5V
∗1
∗1
32
1.2k
20k
22.5k
Power supply.
Apply 9.0V.
GND.
CC
V
4.5V bias.
Attach a decoupling capacitor
between this pin and GND.
This pin cannot be used as an
external power supply.
NC (not connected).
Connect to GND.
If these NC pins are not connected
to GND, the cross talk and other
desired values indicated in the
Electrical Characteristics cannot
be obtained.
– 5 –
∗1
Applied externally.
Page 6
CXA2040Q
V
mA
39.0
4.75
27.7
4.50
18.0
4.25
Measurement contents Min. Typ. Max. Unit
Measure the pin inflow
current.
Measure the pin voltage.
VCV11
dB
0.40
0.00
–0.40
VCV11
0.3Vp-p
20Log
VCV21
dB
6.75
6.25
5.75
VCV21
0.3Vp-p
20Log
VCVM11
dB
0.60
0.10
–0.40
VCVM11
0.3Vp-p
Since the sum of 0.15Vp-p
and 0.15Vp-p is input to
each switch, calculations
20Log
∗
are performed with 0.3Vp-p.
26
32
15
13, 17
Measurement pins
C bus
2
C bus
2
Measurement conditions
CC = 9V, no signal
V
VCC = 9V, no signal
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
100kHz, 0.3Vp-p CW
Select each input with I
control and obtain the I/O gain.
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
100kHz, 0.3Vp-p CW
Select each input with I
control and obtain the I/O gain.
Y1 and C1 (CV6) In or
Y2 and C2 (CV7) In
See Electrical Characteristics Measurement Circuit 1 for all other items.
Symbol
CC
VBIAS
I
GCV11
GCV21
13, 17
C bus
2
100kHz, 0.15Vp-p CW
Select each input with I
control and obtain the I/O gain.
GCVM11
Electrical Characteristics See Electrical Characteristics Measurement Circuit 2 for Cross talk and MUTE. (Ta = 25°C, VCC = 9V)
Current
No. Item
consumption
Pin voltage
1
2
CV system
gain 1
3
CV system
gain 2
4
– 6 –
CV system
(Y/C MIX)
gain 1
5
Page 7
CXA2040Q
Typ. Max. Unit
Measurement contents Min.
VCVM21
dB
7.05
6.40
5.75
VCVM21
0.3Vp-p
Since the sum of 0.15Vp-p
and 0.15Vp-p is input to
each switch, calculations
20Log
∗
are performed with 0.3Vp-p.
VY11
dB
0.40
0.00
–0.40
VY11
0.3Vp-p
20Log
VC11
dB
0.40
0.00
–0.40
VC11
0.3Vp-p
20Log
VCV12
dB
0.55
–0.15
–0.85
VCV12
20Log
VCV11
VCV11 and VCV12 should be
∗
the same I/O.
15
Measurement pins
C bus
2
Measurement conditions
Y1 and C1 (CV6) In or
Y2 and C2 (CV7) In
100kHz, 0.15Vp-p CW
Symbol
Select each input with I
CVM21
G
11
C bus
2
control and obtain the I/O gain.
Y1 In or Y2 In
100kHz, 0.3Vp-p CW
Select each input with I
control and obtain the I/O gain.
GY11
9
C bus
2
C1 In or C2 In
100kHz, 0.3Vp-p CW
Select each input with I
control and obtain the I/O gain.
GC11
13, 17
C bus
2
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
10MHz, 0.3Vp-p CW
Select each input with I
control and obtain the I/O gain.
Then obtain the difference from the
I/O gain measured by Test 3.
∆GCV12
Item
No.
CV system
(Y/C MIX)
gain 2
6
Y system
gain
7
– 7 –
C system
gain
8
CV system
frequency
response 1
9
Page 8
CXA2040Q
Typ. Max. Unit
Measurement contents Min.
VCV22
dB
0.55
–0.15
–0.85
VCV22
20Log
VCV21
VCV21 and VCV22 should be
∗
VCVM12
the same I/O.
dB
1.25
–0.25
–1.75
VCVM12
20Log
VCVM11
VCVM11 and VCVM12 should
be the same I/O.
∗
VCVM22
dB
1.25
–0.25
–1.75
VCVM22
20Log
VCVM21
VCVM21 and VCVM22 should
be the same input.
∗
VY12
dB
0.70
0.00
–0.70
VY12
VY11
20Log
VY11 and VY12 should be the
same input.
∗
15
Measurement pins
C bus
2
Measurement conditions
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
10MHz, 0.3Vp-p CW
Select each input with I
control and obtain the I/O gain.
Then obtain the difference from the
Symbol
∆GCV22
13, 17
C bus
2
I/O gain measured by Test 4.
Y1 and C1 (CV6) In or
Y2 and C2 (CV7) In
10MHz, 0.15Vp-p CW
Select each input with I
control and obtain the I/O gain.
Then obtain the difference from the
I/O gain measured by Test 5.
∆GCVM12
15
C bus
2
Y1 and C1 (CV6) In or
Y2 and C2 (CV7) In
10MHz, 0.15Vp-p CW
Select each input with I
control and obtain the I/O gain.
Then obtain the difference from the
I/O gain measured by Test 6.
∆GCVM22
11
C bus
2
Y1 In or Y2 In
10MHz, 0.3Vp-p CW
Select each input with I
control and obtain the I/O gain.
Then obtain the difference from the
∆GY12
I/O gain measured by Test 7.
Item
No.
CV system
frequency
response 2
10
CV system
(Y/C MIX)
frequency
response 1
11
– 8 –
CV system
(Y/C MIX)
frequency
response 2
12
Y system
frequency
response
13
Page 9
CXA2040Q
Typ. Max. Unit
Measurement contents Min.
Vp-p
2.2
VCV13
Vp-p
2.2
The value for the PAL
composite signal should
correspond to an amplitude of
approximately 1Vp-p + 3dB.
VCVMY
The input waveform
amplitude value when Pins
13, 15 or 17 output waveform
distortion factor = 1%.
Y1 or Y2 input waveform
Vp-p
0.95
The value for the PAL Y signal
should correspond to an amplitude
of approximately 1Vp-p + 3dB.
The input waveform amplitude
value when Pins 13, 15 or 17 output
waveform distortion factor = 1%.
C1 or C2 input waveform
The value for the PAL C signal
should correspond to an amplitude
of approximately 0.66Vp-p + 3dB.
VCVMC
The input waveform amplitude
value when Pins 13, 15 or 17 output
waveform distortion factor = 1%.
Vp-p
2.2
The value for the PAL Y signal
should correspond to an
amplitude of approximately
1Vp-p + 3dB.
VY13
The input waveform
amplitude value when Pin 11
output waveform distortion
factor = 1%.
Vp-p
2.2
VC13
The value for the C signal
should correspond to an
amplitude of approximately
2.2Vp-p.
The input waveform
amplitude value when Pin 9
output waveform distortion
factor = 1%.
23, 25, 27,
Measurement pins
29, 31
C bus
2
Measurement conditions
CV1 In, CV2 In, CV3 In,
CV4 In or CV5 In
f = 100kHz CW
Select each input with I
control and then increase the input
waveform amplitude.
Symbol
CV13
V
1, 5
C bus
2
Y1 (CV6) In or Y2 (CV7) In
f = 100kHz CW
Select each input with I
control and then increase the input
waveform amplitude.
C1 (CV6) In or C2 (CV7) In
VCVMY33
3, 7
C bus
2
f = 100kHz CW
Select each input with I
control and then increase the input
waveform amplitude.
VCVMC33
1, 5
C bus
2
Y1 In or Y2 In
f = 100kHz CW
Select each input with I
VY13
3, 7
C bus
2
control and then increase the input
waveform amplitude.
C1 In or C2 In
f = 100 kHz CW
Select each input with I
control and then increase the input
waveform amplitude.
VC13
Item
No.
CV system
input dynamic
range
14
CV system
(Y/C MIX)
input dynamic
range
15
– 9 –
Y system
input dynamic
range
16
C system
input dynamic
range
17
Page 10
CXA2040Q
dB
Max. Unit
–55
Typ.
VX
Measurement contents Min.
Read the output waveform
value.
VX
1Vp-p
20Log
dB
–50
VX
VX
1Vp-p
Read the output waveform
value.
20Log
dB
–45
VX
VX
1Vp-p
Read the output waveform
value.
20Log
9, 11, 13,
15, 17
Measurement pins
C bus control
2
Measurement conditions
Select the input with I
and ground that input pin via a
capacitor. Input a 4.43MHz, 1Vp-p
CW to one input pin system among
the remaining 8 input pins (7 input
pins for Y/C MIX). Then ground the
remaining 7 input pins (6 input pins
Symbol
CRS
G
9, 11,
13, 17
C
2
for Y/C MIX) via capacitors.
Set this pin to MUTE status with I
bus control and input a 4.43MHz,
1Vp-p CW to one input pin system.
Then ground the remaining 8 input
pins via capacitors.
GM1
15
C
2
Set this pin to MUTE status with I
bus control and input a 4.43MHz,
1Vp-p CW to one input pin system.
Then ground the remaining 8 input
pins via capacitors.
GM2
Item
No.
Cross talk
18
CV system 1,
Y system,
MUTE
C system
19
– 10 –
MUTE
(CV system 2)
20
Page 11
CXA2040Q
100 mV
Measurement contents Min. Typ. Max. Unit
The Sig-1 sync level should
C bus status register is "1"
2
Input Sig-1 to CV1 and check
that bit 5 "SYNCSEP" of the
I
21 (SDA)
Measurement pins
30 mV
correspond to approximately
–9dB when the 1Vp-p NTSC
composite signal sync level
(286mV) is set as 0dB.
when the Sig-1 sync level is
100mV or more.
The Sig-2 sync level should
correspond to approximately
C bus status register is "0"
2
Input Sig-2 to CV1 and check
that bit 5 "SYNCSEP" of the
I
when the Sig-2 sync level is
21 (SDA)
–19dB when the 1Vp-p NTSC
composite signal sync level
(286mV) is set as 0dB.
30mV or less.
91 %
Sync is determined to exist
when the sync level is 100mV
or more and a rectangular
wave with a duty of 91% or
C bus status register is "1"
2
Input Sig-3 to CV1 and check
that bit 5 "SYNCSEP" of the
I
when the Sig-3 duty is 91%
or more (the sync width is
5.72µs or less).
21 (SDA)
84 %
more is input to CV1.
Sync is determined not to exist
when a rectangular wave with
C bus status register is "0"
2
Input Sig-4 to CV1 and check
that bit 5 "SYNCSEP" of the
I
when the Sig-4 duty is 84%
21 (SDA)
a duty of 84% or less is input
to CV1 even when the sync
level is 100mV or more.
or less (the sync width is
10.17µs or more).
100mV
63.56µs
Measurement conditions
4.70µs
CV1 In: Sig-1
Symbol
SYNCD11
Item
SYNC
discrimination 11
63.56µs
CV1 In: Sig-2
SYNCD21
SYNC
30mV
4.70µs
CV1 In: Sig-3
discrimination 21
286mV
63.56µs
SYNCD12
SYNC
discrimination 12
Duty = 91%
5.72µs
63.56µs
CV1 In: Sig-4
SYNCD22
SYNC
286mV
Duty = 84%
10.17µs
discrimination 22
No.
21
22
– 11 –
23
24
Page 12
Unit
CXA2040Q
1.0 3.5 V
Measurement contents Min. Typ. Max.
The slave address goes to
92H at high level and 90H at
low level.
Measurement pins
Measurement conditions
Vary the Pin 19 VADR. 21
Symbol
ADRVTH
V
Item
ADR threshold
voltage
25
No.
– 12 –
Page 13
Electrical Characteristics Measurement Circuit 1
CXA2040Q
2.2µ
10k
10µ
17
NC
CVOUT1
CVOUT2
NC
CVOUT3
NC
YOUT
NC
COUT
NC
8
16
15
10µ 10k
14
13
10µ 10k
12
11
10µ 10k
10
9
0.47µ 10k
2
I
68k
CV1
2.2µ
23
2
22
CV1
NC
3
24
NC
25
29
30
32
26
27
28
31
CV2
CC
V
CV3
NC
CV4
GND
CV5
BIAS
Y1
1
2.2µ
2.2µ
CV2
V
CC
9V
2.2µ
CV3
2.2µ
CV4
2.2µ
CV5
33µ
0.01µ
C bus
I/O
0.1µ
21
20
SCL
SDA
SYNCTC
S1
C1
Vs1 Vs2
2.2µ
Y2
5
4
2.2µ
19
6
VADR
ADR
S2
18
NC
C2
7
Y1
∗1
Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, all are
C1
Y2
C2
GND.
∗2
Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, the supply
voltages are as follows.
VCC = 9V, VS1 = 0V, VS2 = 0V
VADR = 0V when operated with a slave address of 90H.
VADR = 9V (VCC) when operated with a slave address of 92H.
– 13 –
Page 14
Electrical Characteristics Measurement Circuit 2 (Cross talk, MUTE)
2
C bus
24
68k
CV1
2.2µ
23
22
0.1µ
21
I
I/O
19
20
VADR
18
CXA2040Q
17
V
CC 9V
CV2
CV3
CV4
CV5
2.2µ
2.2µ
2.2µ
2.2µ
33µ
0.01µ
25
26
27
28
29
30
31
32
CV2
CC
V
CV3
NC
CV4
GND
CV5
BIAS
NC
CV1
SYNCTC
NC
C1
4
3
2.2µ
C1
Y1
1
2
2.2µ
Y1
SDA
S1
5
SCL
Y2
6
2.2µ
Y2
ADR
S2
7
NC
C2
2.2µ
CVOUT2
CVOUT3
C2
NC
CVOUT1
NC
NC
YOUT
NC
COUT
NC
8
16
15
14
13
12
11
10
9
∗1
Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, all are
GND.
∗2
Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, the supply
voltages are as follows.
VCC = 9V
VADR = 0V when operated with a slave address of 90H.
VADR = 9V (VCC) when operated with a slave address of 92H.
– 14 –
Page 15
CXA2040Q
I2C Bus Control Map
1) Control Register
The CXA2040Q control system is comprised of 4 bytes of control registers which control the various outputs.
The inputs which are to be output are selected by writing the respective input data into the control register.
S Slave address A DATA1 A DATA2 A DATA3 A DATA4 A P
S: START CONDITION
A: ACKNOWLEDGE
P: STOP CONDITION
• Slave address
R/W bit
This bit is set to "0" when data is to be written into the control
100100X0
registers.
DATA1 Controls the video output 1.
DATA2 Controls the video output 2.
DATA3 Controls the video output 3.
DATA4 Controls the S terminal output.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
X X video select X X X
Each register is set to "0" upon POWER ON.
• Video switch control map
bit5 bit4 bit3
0
0
0
0
0
1
0
1
1
0
Selected input signal
0
MUTE
1
CV1/YC1
0
CV2/YC2
1
CV3
0
CV4
Value set by the address pin
1
0
1
CV5
1
1
0
CV6
1
1
1
CV7
Other conditions: MUTE
– 15 –
Page 16
2) Status Register
S Slave address A DATA NA P
S: START CONDITION
P: STOP CONDITION
A: ACKNOWLEDGE
• Slave address
R/W bit
This bit is set to "1" when data is to be read into the status
100100X1
registers.
Value set by the address pin
DATA
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CXA2040Q
PON
RES
SYNC
X
SEP
S1
X
OPENS1SELS2OPENS2SEL
(1) PONRES
Returns "1" when the CXA2040Q is POWER ON RESET. Becomes "0" after reading once.
(2) SYNCSEP
"1" returns if sync exists, "0" if sync does not exist.
(3) OPEN/SEL for S1 and S2 is determined by comparing the DC voltages for S1 and S2 pins with two
threshold levels.
DC voltages for S1 and S2 pins S1, S2 OPEN S1, S2 SEL
2V or less
4.75 to 7.25V
9.5 to 12V
0
0
1
1
0
0
3) POWER ON RESET
The CXA2040Q incorporates a POWER ON RESET function which sets each control register to "0" upon
POWER ON. (Which goes to MUTE status.)
The POWER ON RESET VTH has hysteresis. The POWER ON VCC and released VCC are as shown below.
Also, the PONRES bit of the status register is read to determine whether the IC is reset upon POWER ON.
POWER ON RESET RELEASE
POWER ON RESET
4.7V 5.9V
– 16 –
Vcc
Page 17
CXA2040Q
Description of Operation
1) Composite Video System I/Os
There are three systems of composite outputs. Each output switch can select the eight systems of CV1 to CV5
composite video inputs, CV6 and CV7 Y/C MIX (composite video) inputs and MUTE. All composite video
inputs are input from the input pins to each switch by DC coupling. CV6 is the composite video signal obtained
by inputting Y1 and C1 to an adder and adding Y1 and C1. CV7 is the composite video signal obtained by
inputting Y2 and C2 to an adder and adding Y2 and C2. The CV6 and CV7 composite video signals are input
from the input pins to each switch by DC coupling. When MUTE is selected, the internal bias DC output
(approximately VCC/2 [V]) is input to each switch. Only one type of input is selected by the I2C bus control
register. The CVOUT1 and CVOUT3 switches output the signal selected by the I2C bus at a gain of 0 [dB] with
respect to the input signal. The switch output stages are push-pull circuits which output at low impedance. The
CVOUT2 switch outputs the signal selected by the I2C bus amplified to +6 [dB] with respect to the input signal.
The switch output stage is a push-pull circuit which outputs at low impedance. The switches are DC coupled
from input to output.
2) Y System I/Os
The YOUT switch can select the three systems of Y1, Y2 and MUTE. Y1 and Y2 are input from the input pins
to the switch by DC coupling. When MUTE is selected, the internal bias DC output (approximately VCC/2 [V]) is
input to the switch. Only one type of input is selected by the I2C bus control register. The YOUT switch outputs
the signal selected by the I2C bus at a gain of 0 [dB] with respect to the input signal. The switch output stage is
a push-pull circuit which outputs at low impedance. The switch is DC coupled from input to output.
3) C System I/Os
The COUT switch can select the three systems of C1, C2 and MUTE. C1 and C2 are input from the input pins
to the switch by DC coupling. When MUTE is selected, the internal bias DC output (approximately VCC/2 [V]) is
input to the switch. Only one type of input is selected by the I2C bus control register. The COUT switch outputs
the signal selected by the I2C bus at a gain of 0 [dB] with respect to the input signal. The switch output stage is
a push-pull circuit which outputs at low impedance. The switch is DC coupled from input to output.
– 17 –
Page 18
CXA2040Q
4) Sync Discrimination
Vcc
68k
0.1µ
22
SYNCTC
Duty
discrimination
2
I
C
Input signal
2.2µ
23
IC
Sync tip clamp and
comparator
CV1
Fig. 1. Sync discrimination circuit block diagram
Fig. 1 shows the block diagram for the sync discrimination circuit. The signal input from Pin 23 (CV1) is sync tip
clamped by the external element attached to Pin 22. This signal is compared with a threshold voltage which is
larger than the sync tip level. If the signal is smaller than the threshold level, it does not proceed to the
following stage. At this time, the IC determines that sync does not exist. If the signal is larger than the threshold
level, it proceeds to the duty discrimination block. If the duty is greater than 91%, the duty discrimination block
determines that sync exists and sends the data to the I2C. If the duty is less than 84%, sync is determined not
to exist and the data is sent to the I2C. The duty discrimination block also has a time constant. After sync is
determined to exist, the sync status is held for approximately 14H (NTSC signal) even if the IC goes to a status
where sync does not exist such as no signal, etc. If there is no signal or sync does not exist for longer than
14H, the status switches from sync exists to sync does not exist.
– 18 –
Page 19
Application Circuit
CXA2040Q
VCC
I2C BUS
68k
signal inputs
Composite video
75
75
Vcc
9V
75
75
75
220
2.2µ
2.2µ
2.2µ
2.2µ
220
0.01µ 33µ
220
220
2.2µ
220
0.01µ
33µ
29
30
25
26
27
28
31
32
CV2
CC
V
CV3
NC
CV4
GND
CV5
BIAS
24
0.1µ
220 220
23
NC
CV1
Y1
NC
1
2
220
22
SYNCTC
C1
3
220
21
20
SDA
CXA2040Q
S1
4
Vs1
SCL
Y2
5
220
19
ADR
S2
6
VADR
Vs2
18
7
NC
C2
220
17
NC
CVOUT1
CVOUT2
NC
CVOUT3
NC
YOUT
NC
COUT
NC
8
15
13
16
14
12
11
10
Composite
video signal
10µ
10µ
10µ
10µ
9
0.47µ
0dB output 1
Composite
video signal
+6dB output 2
Composite
video signal
0dB output 3
Luminance
signal output
Chrominance
signal output
2.2µ
signal input 1
Luminance
∗1
Input pins of Pins 1, 3, 5, 7, 23, 25, 27, 29 and 31 are biased to approximately 4.2 to 4.7V. Therefore, care
75
2.2µ
75 75 75
signal input 1
Chrominance
2.2µ
signal input 2
Luminance
2.2µ
signal input 2
Chrominance
should be taken for the capacitance polarity.
∗2
Output pins of Pins 9, 11, 13, 15 and 17 are biased to approximately 3.8 to 4.8V. Therefore, care should be
taken for the capacitance polarity.
∗3
Set VADR to 0V (GND) when the IC slave address is 90H, or to 9V (VCC) when the IC slave address is 92H.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 19 –
Page 20
CXA2040Q
Notes on Operation
• Connect the power supply side of the by-pass capacitor between the power supply and GND as close to the
pin as possible.
• Take care not to allow interference signals to enter Pin 32 (BIAS). If interference signals enter Pin 32, the
signal S/N, cross talk and MUTE will deteriorate. Therefore, connect the by-pass capacitor, etc. as close to
the pins as possible.
• For dual surface boards, using one side as a solid earth is best.
• Pins 2, 8, 10, 12, 14, 16, 18, 24 and 28 are NC (not connected) pins. Connect these NC pins to GND. If these
NC pins are not connected to GND, the cross talk and other desired values indicated in the Electrical
Characteristics cannot be obtained.
• Input pins of Pins 1, 3, 5, 7, 23, 25, 27, 29 and 31 are biased to approximately 4.2 to 4.7V. Therefore, care
should be taken for the capacitance polarity.
• Output pins of Pins 9, 11, 13, 15 and 17 are biased to approximately 3.8 to 4.8V. Therefore, care should be
taken for the capacitance polarity.
– 20 –
Page 21
Curve Data
CXA2040Q
CV1 to 5 inputs —
CVOUT1, 3 frequency response
2
0
–2
–4
Video I/O gain [dB]
–6
–8
0.1 1 10
Frequency [MHz]
Y/C MIX input —
CVOUT1, 3 frequency response
2
0
–2
–4
Video I/O gain [dB]
–6
CV1 to 5 inputs —
CVOUT2 frequency response
8
6
4
2
Video I/O gain [dB]
0
–2
0.1 1 10
Frequency [MHz]
Y/C MIX input —
CVOUT2 frequency response
8
6
4
2
Video I/O gain [dB]
0
–8
0.1 1 10
Frequency [MHz]
Y input — YOUT frequency response
2
0
–2
–4
Video I/O gain [dB]
–6
–8
0.1 1 10
Frequency [MHz]
–2
0.1 1 10
Frequency [MHz]
C input — COUT frequency response
2
0
–2
–4
Video I/O gain [dB]
–6
–8
0.1 1 10
Frequency [MHz]
– 21 –
Page 22
Package Outline Unit: mm
CXA2040Q
32PIN QFP (PLASTIC)
25
32
9.0 ± 0.2
+ 0.3
7.0 – 0.1
+ 0.35
1.5 – 0.15
0.1
1724
16
(8.0)
9
+ 0.2
0.1 – 0.1
1
0.8 0.3 – 0.1
+ 0.15
8
± 0.12
+ 0.1
M
0.127 – 0.05
0.50
0° to 10°
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-32P-L01
∗QFP032-P-0707-A
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
– 22 –
EPOXY RESIN
SOLDER PLATING
42 ALLOY
0.2g
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