Datasheet CXA2066S Datasheet (Sony)

Description

The CXA2066S is a bipolar IC developed for high

resolution computer displays.

Features

• Built-in wide band amplifier: 140MHz @ –3dB (Typ.)

• Input dynamic range: 1.0Vp-p (Typ.)

• High gain preamplifier (17dB)

• R, G, and B incorporated in a single package

• I2C bus control

Contrast control Subcontrast control Brightness control OSD contrast control Cutoff control 4-channel DAC output 2 blanking level modes (0.5V fixed and Pedestal –0.6V) ABL control pin

• Built-in sync separator for Sync on Green

• Built-in blanking mixing function

• Built-in OSD mixing function

• Video period detection function

• Built-in sharpness function

• Built-in VBLK synchronous DAC refresh system

Applications

High resolution computer displays

Structure

Bipolar silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C, GND = 0V)

• Supply voltage VCC 14 V VCC27 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation PD 2.05 W

Recommended Operating Conditions

Supply voltage VCC 12 ± 0.5 V

VCC2 5 ± 0.5 V

CXA2066S

Preamplifier for High Resolution Computer Display

– 1 –

E98210-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

30 pin SDIP (Plastic)

– 2 –

CXA2066S

3

4

5

6

7

8

9

10

11

OSD-G

OSD-B

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

V

CC2

GIN

SYNC IN

BIN

CLP

OSD-R

D/A CONVERTER

I

2

C BUS

DECORDER

CUTOFF (R) CUTOFF (G) CUTOFF (B) CUTOFF (RGB)

LPF

OSD GAIN (R) OSD GAIN (G) OSD GAIN (B)

BRIGHTNESS (RGB)

BRIGHTNESS

SUB CONTRAST (R)

SUB CONTRAST (G)

SUB CONTRAST (B)

CONTRAST

OSD SW

GAIN CONTROL AMP

GAIN CONTROL DATA

CONTRAST

Rch

SUB CONTRAST

BLANKING BUFFER AMP

BLANKING PULSE

BLANKING MODE

OSD YS GENERATOR

OSD GAIN (R)

Gch

5V

to OSDSW

Same as R channel

To each MODE switch

Bch

Same as R channel

VDET, SYNC SEP, SHARPNESS

SHARPNESS

GAIN CONT.

T SW

SYNC SEPARATOR

12V

OSD PULSE (13PIN) YS PULSE (17PIN)

VDET COMPARATOR

to OSDSW

1

2

13

14

15

12

16

17

18

19

20

21

22

23

24

25

26

27

28

S/H-R

29

ABL

30

CSYNC

ROUT

GND-R

S/H-G

GOUT

GND-G

V

CC

S/H-B

BOUT

GND-B

BLKING

YS

VDET

Block Diagram

– 3 –

CXA2066S

Pin Description

Pin No.

Symbol

SDA

1

Equivalent circuit

Description

I2C bus standard SDA (serial data) input/output.

VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0.4V

Pin voltage

1

VCC

4k

SCL

2

I2C bus standard SCL (serial clock) input.

VILMAX = 1.5V VIHMIN = 3.5V

2

VCC

4k

10k

COF R COF G COF B COF RGB

3 4 5 6

Cut-off adjustment DAC outputs. The output DC is 1 to 4V.

3 4 5 6

VCCVCC

VCC

100

RIN GIN BIN

VCC2 5V

1.7V (when clamped)

7 9

11

8

RGB signal inputs. Input via the capacitor.

5V power supply.

7 9

11

VCC

1k

VCC

14k

VCC

8k

300

VCC

– 4 –

CXA2066S

No.

Symbol

SYNC IN

10

Equivalent circuit

Description

Sync on Green signal input. Input via the capacitor.

Pin voltage

10

VCC

100

150

VCC

CLP

12

Clamp pulse (positive polarity) input.

VILMAX = 0.8V VIHMIN = 2.8V

12

VCC

10k

10k10k

OSD-R OSD-G OSD-B

13 14 15

OSD control inputs.

VILMAX = 0.8V VIHMIN = 2.8V

13 14 15

VCC

10k

5k

VDET

16

Video detector output.

Typ.; High = 4.3V

Low = 0.2V

16

VCC2

100

VCC2

5k

VCC2

20k

VCC2

2.8V

– 5 –

CXA2066S

Pin No.

Symbol

YS

17

Equivalent circuit

Description

YS (OSD_BLK) input.

VILMAX = 0.8V VIHMIN = 2.8V

Pin voltage

17

VCC

10k

5k

BLKING

18

Blanking pulse input. Set the V blanking pulse width to 300µs or more.

VILMAX = 0.8V VIHMIN = 2.8V

18

VCC

VCCVCC

10k

30k

4k

GND-B GND-G GND-R

19 23 26

GNDs.

BOUT GOUT ROUT

VCC 12V

0V

20 24 27

22

R, G, and B signal outputs.

12V power supply.

20 24 27

620

0.5p

VCC

S/H-B S/H-G S/H-R

21 25 28

Brightness sample-and-hold. Connect a capacitor to GND.

VCC VCC

300

VCC

1k

21 25 28

– 6 –

CXA2066S

Pin No.

Symbol

Equivalent circuit

Description

Pin voltage

CSYNC

30

Sync on Green signal sync separator output (positive polarity).

Typ.; High = 4.3V

Low = 0.2V

15k

VCC2 VCC2VCC2

100

VCC2

30

ABL

29

ABL control input. Ground to GND when not using ABL.

29

VCC

50k

25k

VCC

– 7 –

CXA2066S

I2C BUS Register Definitions

Slave Address

SLAVE RECEIVER; 40 (HEX)

Register Table

SUB ADDRESS BIT7

00H CONTRAST 01H 0

BLK MODE

BRIGHTNESS

02H CUT OFF R 03H CUT OFF G 04H CUT OFF B

OSD GAIN05H VDET LEVEL 06H CUT OFF RGB 07H SUB CONTRAST R 08H SUB CONTRAST G 09H SUB CONTRAST B

0AH

V DET OFF

SHP OFF

SYNC OFF

T SW SHP GAIN

BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

CONTRAST (8) Controls the gain common to the R, G, and B channels. Since control is

performed by multiplying with SUB CONTRAST, the white balance can be adjusted by SUB CONTRAST and the luminance can be adjusted by CONTRAST.

0: Gain minimum (–30dB or less) 255: Gain maximum (+17dB)

BLK MODE (1) Switches the blanking level.

0: Pedestal –0.6V 1: 0.5V fixed

BRIGHTNESS (6) Controls the black level common for the R, G, and B channels.

0: Black level minimum (1V) 63: Black level maximum (3V)

CUT OFF R (8) Controls Pin 3 (COF R) output voltage.

0: Output voltage minimum (1V) 255: Output voltage maximum (4V)

CUT OFF G (8) Controls Pin 4 (COF G) output voltage.

0: Output voltage minimum (1V) 255: Output voltage maximum (4V)

CUT OFF B (8) Controls Pin 5 (COF B) output voltage.

0: Output voltage minimum (1V) 255: Output voltage maximum (4V)

Sub Address

0000

Sub Address

0001

Sub Address

0001

Sub Address

0010

Sub Address

0011

Sub Address

0100

– 8 –

CXA2066S

VDET LEVEL (2) Controls the signal detection (VDET) slice level.

0: Slice level minimum (30mV when RIN = GIN = BIN) 3: Slice level maximum (220mV when RIN = GIN = BIN)

OSD GAIN (6) Controls the OSD gain common to the R, G, and B channels. Since

control is performed by multiplying with SUB CONTRAST (upper 6 bits), white balance and tracking for the video is obtained.

0: Gain minimum (0Vp-p) 63: Gain maximum (5Vp-p)

CUT OFF RGB (8) Controls Pin 6 (COF RGB) output voltage.

0: Output voltage minimum (1V) 255: Output voltage maximum (4V)

SUB CONTRAST R (8)

Controls the R channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance.

0: Gain minimum (–30dB or less) 255: Gain maximum (+17dB)

SUB CONTRAST G (8)

Controls the G channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance.

0: Gain minimum (–30dB or less) 255: Gain maximum (+17dB)

SUB CONTRAST B (8)

Controls the B channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance.

0: Gain minimum (–30dB or less) 255: Gain maximum (+17dB)

VDET OFF (1) Controls the Pin 16 (VDET) output.

0: VDET output on 1: VDET output off

SHP OFF (1) Controls the sharpness function.

0: Sharpness on 1: Sharpness off

SYNC OFF (1) Controls the Pin 30 (CSYNC) output.

0: SYNC output on 1: SYNC output off

T SW (1) Controls the time constant during sharpness.

0: 50ns 1: 100ns

SHP GAIN (4) Controls the sharpness gain.

0: Gain minimum (–30dB or less) 15: Gain maximum (+7dB)

Sub Address

0101

Sub Address

0101

Sub Address

0110

Sub Address

0111

Sub Address

1000

Sub Address

1001

Sub Address

1010

Sub Address

1010

Sub Address

1010

Sub Address

1010

Sub Address

1010

– 9 –

CXA2066S

Electrical Characteristics

No.

Measurement item

Symbol

ICC1 ICC2

F4

F5

Measurement contents

1

2

Current consumption

Frequency response (50MHz)

Frequency response (100MHz)

VCC and VCC2 pins inflow current Input signal: None

Input continuous 1MHz, 50MHz, and 100MHz sine waves at 0.7Vp-p. Measure the output amplitude gain difference at this time.

Gain difference [dB] = 20 log Gain difference [dB] = 20 log

Min. Typ. Max. Unit

65 88 110 mA 30 45

0

–1.85

60 mA

dB

VOUT 50M

V

OUT 1M

)

(

VOUT 100M

V

OUT 1M

)

(

CLP potential (approximately 1.7V)

0.7Vp-p

GND

GCONT1

GCONT2

3

Contrast control 1

Contrast control 2

Measure the level of the output signal amplitude VOUT when a 0.7Vp-p video signal is input. (ABL = 0V)

VCONT1: Contrast = Sub Contrast = FF VCONT2: Contrast = 00/Sub Contrast

= FF

5.0

35

Vp-p

mVp-p

0.7Vp-p

GSUB

4

Sub Contrast control

Measure the level of the output signal amplitude VOUT when a 0.7Vp-p video signal is input. (Contrast = FF/Sub Contrast = 00/ ABL = 0V)

35

mVp-p

0.7Vp-p

RGB input signal (RGB input pins)

Input signal

–1.7

1.7

–5.5 1.8

4.5

5.5

–30 100

– 10 –

CXA2066S

GOSD1

GOSD2

5

OSD gain control

Measure the OSD level of the output signal when an OSD pulse is input.

GOSD1: OSD = 3F/Sub Contrast = FF GOSD2: OSD = 00/Sub Contrast = FF

5.0

–70

Vp-p

mVp-p

OSD period

OSD level

VBRT1

VBRT2

6

Brightness control

Measure the black level of the RGB output signal.

VBRT1: Brightness = 00 VBRT2: Brightness = 3F

1.1

2.9

V

Black level

GND

VBLK1

VBLK2

7

BLK control (BLK MODE = 0)

BLK control (BLK MODE = 1)

Measure the BLK level of the output signal when a BLK pulse is input.

560

310

mV

BLK level (VBLK1)

BLK level (VBLK2)

GND

RGB output signal

No.

Measurement item

Symbol Measurement contents Min. Typ. Max. Unit

80

4.4

5.6

–240

0.8 1.4

2.65

3.15

400 720

200 420

– 11 –

CXA2066S

SHP1

SHP2

SHP3

SHP4

8

Sharpness gain 1

Sharpness gain 2

Sharpness gain 3

Sharpness gain 4

Input a 30MHz sine wave to RGB at an amplitude of 0.1Vp-p, and measure the output level, and then calculate I/O gain.

Gain difference [dB] = 20 log

(Contrast = 7F/Sub Contrast = FF/ ABL = 0V)

SHP1: SHP GAIN = 0/T SW = 0 SHP2: SHP GAIN = F/T SW = 0 SHP3: SHP GAIN = 0/T SW = 1 SHP4: SHP GAIN = F/T SW = 0

10.9

16.6

11.2

18.3

dB

CLP potential (approximately 1.7V)

0.1Vp-p

GND

VIND1

VIND2

9

Input D range (VIN = 0.7V)

Input D range (VIN = 1.2V)

Measure the output level when

0.7Vp-p and 1.2Vp-p input video signals are input. (Contrast = CC, Sub Contrast = FF, Brightness = 00)

4.3

6.3

Vp-p

SYNCHI

SYNCLO

10

SYNCSEP output high level

SYNCSEP output low level

Input a Sync on Green video signal to SYNCIN, and measure the CSYNC high level and low level.

4.4

200

V

mV

Low level

High level

CSYNC

GND

SDLYR

SDLYF

11

SYNCSEP output rise delay

SYNCSEP output fall delay

42

45

ns

Rise delay Fall delay

Vth = 50%

Input signal

Vth = 50%CSYNC

Input signal

No.

Measurement item

Symbol Measurement contents Min. Typ. Max. Unit

Output level

Input level

)

(

8.9 12.9

14.6 18.6

9.2

13.2

16.3

20.3

3.8

4.8

5.8 6.8

4.1

4.7

100 300

50

70

– 12 –

CXA2066S

VCUT1

VCUT2

14

DAC output voltage (COFF = 00)

DAC output voltage (COFF = FF)

Measure the DAC output voltage (Pins 3, 4, 5, and 6) when COFF = 00/FF.

1.1

4

V

VDETHI

VDETLO

12

VDET output high level

VDET output low level

Measure the VDET high level and low level when a 0.7Vp-p video signal is input to RGB.

4.4

280

V

mV

Low level

High level

VDET

GND

VDDLYR

VDDLYF

13

VDET output rise delay

VDET output fall delay

17

26

ns

0.7Vp-p

Input signal

VDET

Rise delay Fall delay

Vth = 50%

No.

Measurement item

Symbol Measurement contents Min. Typ. Max. Unit

4.1

200

4.7

400

40

50

0.9

4.23.8

1.3

– 13 –

CXA2066S

I2C BUS Logic System

No.

Item Symbol Min. Typ. Max. Unit 1 2

3 4

5 6 7 8 9

10 11 12 13 14

High level input voltage Low level input voltage Low level output voltage

SDA, during current inflow of 3mA Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transfer start Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation

VIH VIL

VOL fSCL

tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO

3.0 0

0 0

4.0

4.7

4.0

4.7

440 250

— —

4.7

— —

— — — — — — — — — —

5.0

1.5

0.4

100

— — — — — — —

1

300

—

V V

V

kHz

µs µs µs µs µs

ns ns

µs

ns

µs

– 14 –

CXA2066S

Electrical Characteristics Measurement Circuit

0.1µF

75

0.1µF

75

0.1µF 47µF

0.1µF

75

5V

12V

B channel output

0.1µF

47µF

75

220

3

4

5

6

7

8

9

10

11

OSD-G

OSD-B

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

V

CC2

GIN

SYNC IN

BIN

CLP

OSD-R

1

2

13

14

15

12

16

17

18

19

20

21

22

23

24

25

26

27

28

S/H-R

29

ABL

30

CSYNC

ROUT

GND-R

S/H-G

GOUT

GND-G

V

CC

S/H-B

BOUT

GND-B

BLKING

YS

VDET

G channel output

R channel output

SYNC SEP output

Video detector output

220

I

2

C BUS

DAC output

0.1µF

– 15 –

CXA2066S

Electrical Characteristics Measurement Circuit (Frequency Response)

0.1µF

1k

50

0.1µF 47µF

0.1µF

1k

50

5V

12V

B channel output

0.1µF

47µF

0.1µF

1k

50

220

3

4

5

6

7

8

9

10

11

OSD-G

OSD-B

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

V

CC2

GIN

SYNC IN

BIN

CLP

OSD-R

1

2

13

14

15

12

16

17

18

19

20

21

22

23

24

25

26

27

28

S/H-R

29

ABL

30

CSYNC

ROUT

GND-R

S/H-G

GOUT

GND-G

V

CC

S/H-B

BOUT

GND-B

BLKING

YS

VDET

G channel output

R channel output

SYNC SEP output

Video detector output

220

I

2

C BUS

DAC output

0.1µF

– 16 –

CXA2066S

Description of Operation

1. Sharpness function

The RGB signals input to Pins 7, 9, and 11 are mixed at a ratio of 0.6G + 0.3R + 0.1B to form the Y signal. The high-frequency component is removed from this Y signal by a differentiation circuit, and the amplitude is controlled by a gain control circuit. The signal which undergoes gain control (sharpness component) has its amplitude clipped by a limiter circuit and is then added to the R, G, and B signals.

No sharpness component

Section not sent to RGB output because of the limiter

∗

RGB output when RIN = GIN = BIN = 0.7Vp-p

The output level is set to 100%.

Limiter level = 30% (Typ.)

SHP GAIN = 0 (HEX) or SHP OFF = 1

SHP GAIN = F (HEX)

100%

50ns (T SW = 0)

10%

100ns (T SW = 1)

100%

2. VBLK synchronous DAC refresh system

The VBLK signal is removed from the composite BLK signal which has been input to Pin 18, and the data for each control DAC is overwritten all at once in synchronization with this VBLK signal. The received I2C bus data is held by a latch until the next VBLK signal arrives. As a result, I2C bus data transmission from the microcomputer is timing-free. Set the V blanking pulse width which is input to Pin 18 at 300µs or more.

– 17 –

CXA2066S

VBLK Synchronous DAC Refresh System

The newest transmission data

before Vsync is written to the DAC.

In this case, the data in (1) is written.

Transmission period

disable

Data group (1)

The DAC is not overwritten

while the bus data in the Vsync

period is being transmitted.

The transmitted data is held.

Overwritten by the data in (3).

If (3) is not transmitted, this is

overwritten by the data in (2).

enable

Data group (2)

Data group (3)

Vsync

Bus data transmission

DAC refresh

enable signal

DAC refresh

signal

– 18 –

CXA2066S

0.1µF

75

0.1µF

75

0.1µF 47µF

0.1µF

75

B channel output

YS input

0.1µF

12V

47µF

75

220

3

4

5

6

7

8

9

10

11

OSD-G

OSD-B

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

V

CC2

GIN

SYNC IN

BIN

CLP

OSD-R

1

2

13

14

15

12

16

17

18

19

20

21

22

23

24

25

26

27

28

S/H-R

29

ABL

30

CSYNC

ROUT

GND-R

S/H-G

GOUT

GND-G

V

CC

S/H-B

BOUT

GND-B

BLKING

YS

VDET

G channel output

R channel output

SYNC SEP output

Video detector output

220

I

2

C BUS

DAC output

R channel input

5V

G channel input

Sync on Green input

B channel input

Clamp pulse input

OSD pulse (R channel) input

Blanking pulse input

∗

VBLK ≥ 300µs

ABL input

OSD pulse (G channel) input

OSD pulse (B channel) input

0.1µF

Application Circuit

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 19 –

CXA2066S

5

4

3

2

1

0

0 50 100

CONTRAST Control Characteristics

Output amplitude [Vp-p]

CONTRAST DATA

150 200 250

SUB CONTRAST = 255 SUB CONTRAST = 127

5

4

3

2

1

0

0 50 100

OSD Gain Control Characteristics

OSD output amplitude [Vp-p]

OSD GAIN DATA

150 200 250

SUB CONTRAST = 255 SUB CONTRAST = 127

Video IN = 0.7Vp-p

5

4

3

2

1

0

0 50 100

SUBCONT Control Characteristics

Output amplitude [Vp-p]

SUB CONTRAST DATA

150 200 250

CONTRAST = 255 CONTRAST = 127

Video IN = 0.7Vp-p

5

4

3

2

1

0

0 1 2

ABL Control Characteristics

Output amplitude [Vp-p]

Voltage Applied to Pin 29 [V]

3 4 5

Video IN = 0.7Vp-p SUB CONTRAST = FF (HEX) CONTRAST = FF (HEX)

Example of Representative Characteristics

– 20 –

CXA2066S

Notes on Operation

1. Set the output for ROUT, GOUT, and BOUT for reception at high impedance.

2. Make the wiring from ROUT, GOUT, and BOUT to the power amplifier as short as possible.

3. Connect the VCC and VCC2 decoupling capacitor so that the ceramic capacitor and electrolytic capacitor are connected in parallel and the distance from the IC is as short as possible.

4. Connect the clamp capacitor for RIN, GIN, BIN, S/H-R, S/H-G, S/H-B so that the distance from the IC is as short as possible.

5. Set the output to OFF when the VDET output is not used (Set I2C BUS VDETOFF "1").

– 21 –

CXA2066S

Package Outline Unit: mm

SONY CODE EIAJ CODE JEDEC CODE

30PIN SDIP (PLASTIC)

26.9 – 0.1

+ 0.4

15

16

30

1.778

10.16

8.5 – 0.1

+ 0.3

0.25 – 0.05

+ 0.1

0° to 15°

0.5 ± 0.1

0.9 ± 0.15

3.0 MIN

0.5 MIN

3.7 – 0.1

+ 0.4

SDIP-30P-01 SDIP030-P-0400

1

PACKAGE STRUCTURE

MOLDING COMPOUND

LEAD TREATMENT LEAD MATERIAL PACKAGE MASS

EPOXY RESIN

PLATING

COPPER ALLOY

1.8g

SOLDER/PALLADIUM

1.All mat surface type.

Two kinds of package surface:

2.All mirror surface type.

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).