Page 1
Digital CCD Camera Head Amplifier
Description
The CXA2056Q is a bipolar IC developed as a
head amplifier for digital CCD cameras. This IC
provides the following functions: correlated double
sampling, AGC for the CCD signal, GCA for the lowband chroma signal, AMP for high-band chroma and
line signals, A/D sample and hold, blanking, A/D
reference voltage, and an output driver.
Features
• High sensitivity made possible by a high-gain AGC
amplifier
• Blanking function provided for the purpose of
calibrating the CCD output signal black level
• Regulator output pin provided for A/D converter
reference voltage
• Built-in GCA and AMP for amplifying video signals
(chroma and line signals) from external sources
• Built-in sample-and-hold circuits for camera signals
required by external A/D converters
Absolute Maximum Ratings
• Supply voltage VCC 11 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation
PD 1160 mW
Operating Conditions
Supply voltage VCC1, 2, 3 3 to 3.3 V
Applications
Digital CCD cameras
Structure
Bipolar silicon monolithic IC
– 1 –
E96119A8X-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXA2056Q
32 pin QFP (Plastic)
Page 2
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CXA2056Q
Block Diagram and Pin Configuration
DC
SHIFT
BUF
SH1 SH2
SH3
VIDC
SHIFT
VREF
DMSW1
DMSW2
VSI
CH
SW
CAM
SH
OBSW
VS2
VCENT
VCENT
MODE CONTROL
&
POWER SAVE CONTROL
LOSW
VB
VRT
OFFSET
VRB
CVSW
VCENT VB
VB
BLK SW
26
27
28
29
30
31
32
25
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
1
17
18
19
20
21
22
23
24
PIN
PBRFC
DIN
V
CC2
ICONT
LIN/CH
GND2
RFCONT
AGCCLP
V
CC3
CLPOB
XRS
PBLK
OFFSET
VRT
VRB
MODE1
DRVOUT
MODE2
MODE3
PS
N.C
GND3
LOUTCLP
CLPDM
N.C
GND1
SHD
SHP
V
CC
1
CCDLEVEL
AGCCONT
VISW
LISW
1
2
3
CDS
CLP1
CDS
CLP2
LIN
CLP
LIN
CH AMP
CL
GCA
CAM
DRV
VIDEO
DRV
LOUT
CLP
V
RT
DRV
VRB
DRV
AGC
CLP
AGC
Page 3
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CXA2056Q
Pin Description (VCC1, 2, 3 = 3V)
Pin
No.
Symbol Pin voltage Equivalent circuit Description
1 MODE1
Camera and video
signal selector.
Composite video
signal and high-band
chroma/low-band
chroma signal
selector of the video
signal.
For details on the
selection conditions
for each mode, refer
to the diagram of the
Electrical
Characteristics
Measurement Circuit.
2 MODE2
3 MODE3
4 PS
Power saving mode.
5
17
N.C
No connection;
normally ground.
6
23
30
GND3
GND1
GND2
Ground.
7
LOUTCLP
Capacitor connection
for LOUTCLP which
clamps the output
minimum level in
modes which pass
the composite video
signal.
(Recommended
value: 0.1µF)
VTH = 1.5V
GND
Approx. 1.1V
145
75k
50k
50k
10µA
2
3
4
1
1.5V
7
2µA
100µA 100µA
38k 1k
90k22k
12k
145
1.1V
Page 4
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CXA2056Q
Pin
No.
Symbol Pin voltage Equivalent circuit Description
8
DRVOUT
Driver output for A/D
converter capable of
DC coupling.
Dynamic range
= 1Vp-p
• Camera
mode (CAM)
VRB to VRB +
100mV
• Composite
video mode
(LIN)
VRB + 50mV
= approx.
1.4V
• Chroma
mode
(CH, CL)
Center
voltage =
(VRT – VRB)/2
= approx.
1.85V
10 VRB
1.35V regulator
output.
Be sure to decouple
this pin near the IC
pins to prevent the
oscillation and external
noise when this pin is
not used.
(Recommended
capacitor value: 4.7µF)
9
20
27
VCC3
VCC1
VCC2
Power supply.VCC
1.35V
2.35V11 VRT
2.35V regulator
output.
Be sure to decouple
this pin near the IC
pins to prevent the
oscillation and external
noise when this pin is
not used.
(Recommended
capacitor value: 4.7µF)
100µA
5090
4072
509
30k
10p
1.4
1.85V
30k
SW3
SW1
SW2
2.4mA
CAM signal
VIDEO signal
48
50µA
SW1
145
ICONT
3.2 to 6.4mA
200µA
50µA
25µA25µA
2k
IOFFSET
0 to
50µA
SW1
VRT = 2.35V
V
RB = 1.35V
8
SW1SW2
Mode
1
0
0
0
1
1
SW3
0
1
0
CAM
LIN
CH, CL
0: Open
1: Closed
200
30k
16.5k
13.5k
145
1.35V
110µA
10
30k
6.5k
23.5k
145
2.35V
220µ
11
55µ
55µ
200
Page 5
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CXA2056Q
Pin
No.
Symbol Pin voltage Equivalent circuit Description
12 OFFSET
Controls the output
offset during camera
mode.
When 3V: VRB
When 1.5V:
VRB + 100mV
When 0V
(preset mode):
VRB + 35mV
1.5 to 3V
&
0V
2k
30k
30k
50k 50k
1.5k 3k
25k
VRB
145
50µA
50µA 50µA
12
1.85V
13 PBLK
Camera signal
preblanking pulse
input.
Active when Low only
during camera mode.
Calibrates the black
level of the AGC output
waveform.
When PBLK is Low,
the DRVOUT potential
is forced to VRB.
VTH = 1.85V
13
145
50µA
30k
30k
1.85V
30k
14 XRS
Camera signal
sample-and-hold
pulse input.
VTH = 0.68V
24k
7k
0.68V
770µA
40µA
97µ
145
14
15 CLPOB
Clamp pulse used to
clamp the optical
black portion of the
camera signal after it
passes through the
AGC amplifier.
VTH = 1.5V
145
50µA
30k
30k
1.5V
30k
15
Active: Low
Sampling
Active: Low
Page 6
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CXA2056Q
Pin
No.
Symbol Pin voltage Equivalent circuit Description
16 AGCCLP
AGC clamp capacitor.
(Recommended
value: 0.1µF)
Approx. 1.3V
18
AGCCONT
AGC gain control.
When 1.5V: –1dB
(Minimum gain)
When 3.0V: +31.5dB
(Maximum gain)
1.5 to 3.0V
50k
145
145
5k5k
3k
3k
16
145
18
200µA
3.4k 3.4k
200µA
2.14V
100µA300µA
300µA 100µA
2.29V
ICONT
3.4k
3.4k
3.3k
3.3k
19
CCDLEVEL
Enables monitoring of
the SH3 output
camera signal.
DIN input
CCD signal
black level:
approx. 2.2V
21 SHP
Preset level sampleand-hold pulse input.
22 SHD
Data level sampleand-hold pulse input.
VTH = 0.65V
500
19
340
100µA
36k
10k
0.65V
365µA
20µA
145
21
22
Sampling
Page 7
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CXA2056Q
Pin
No.
Symbol Pin voltage Equivalent circuit Description
24 CLPDM
Clamp pulse used to
clamp the dummy
pixel portion of the
input CCD signal.
VTH = 1.5V
145
50µA
30k
30k
1.5V
24
25
26
28
PIN
DIN
ICONT
CCD signal input.
DRVOUT output
waveform rise time
control.
When 1.5V:
Maximum rise time
When 3V:
Minimum rise time
Black level:
approx. 2.1V
1.5 to 3V
145
145
200µA
50µA
23k
26
25
7k14k
2k
2k
15µA
15µA
145
100µA
15k
45k
28
6k
6k
2.25V
29
LIN/CH
Common input for the
composite video
signal (LIN) and highband chroma signal
(CH).
Clamp
potential
during
LIN mode:
approx. 1.46V
During
CH mode:
approx. 1.85V
145
50µA
25µA
200µA
11.5k
18.5k
1.85V
CH mode
100µA
LIN mode
2µA
10k
30k
VRB + 50mV
29
54k
Active: Low
Page 8
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CXA2056Q
Pin
No.
Symbol Pin voltage Equivalent circuit Description
31 RFCONT
Gain control for the
low-band chroma
signal (CL).
When 0.3V: –4dB
(Minimum gain)
When 2.7V: +12.5dB
(Maximum gain)
0.3 to 2.7V
54k145
42k27k
27k
31
32 PBRFC
Low-band chroma
signal (CL) input.
Approx. 1.9V
32
145
200µA
100µA
7.8k
2k
58k
10k
10k
200µA
38k
1.9V
22k
25µA
2.9V
Page 9
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CXA2056Q
Electrical Characteristics (Ta=25°C, VCC1, 2, 3 = 3V)
Camera
mode
LINE mode
CH mode
CL mode
PS mode
Maximum
gain
Minimum
gain
Range of gain
variance
Dynamic
range
maximum
Dynamic
range
typical
Offset high
Offset low
Offset
preset
VRT DC
level
VRB DC
level
VRT – VRB
Offset
LIN mode
gain
CH mode
gain
CL mode
maximum gain
CL mode
minimum gain
Dynamic
range
IDC
IDL
IDCH
IPCL
IDP
A CONT
max.
A CONT
min.
AGC G
AGCmax.
D
AGCTYP.
D
CAOF
high
CAOF
low
CAOF
pre
VRTO
VRBO
∆VR
BLKOF
LIN G
CH G
RF
CONmax.
RF
CONmin.
SH3 D
AGCCONT = 1.5V, open between VRT and VRB
MODE1 = 3V, MODE2 = 0V
MODE3 = 0V, PS = 3V, ICONT = 3V
Open between VRT and VRB
MODE1 = 0V, MODE2 = 0V,
MODE3 = 0V, PS = 3V
Open between VRT and VRB
MODE1 = 0V, MODE2 = 3V,
MODE3 = 3V, PS = 3V
RFCONT = 0.3V, open between VRT and VRB
MODE1 = 0V, MODE2 = 3V,
MODE3 = 0V, PS = 3V
PS = 0V
DIN = 1µs, 20mVp-p pulse
AGCCONT = 3V, ICONT = 3V
DIN = 1µs, 500mVp-p pulse
AGCCONT = 1.5V, ICONT = 3V
A CON max. – A CON min.
AGCCONT = 3V
DRVOUT output signal at saturation level
AGCCONT = 2V
DRVOUT output signal at saturation level
Camera mode
OFFSET = 1.5V
Camera mode
OFFSET = 3.0V
Camera mode
OFFSET = 0V
With a 400Ω load
With a 400Ω load
With a 400Ω load
BLKOF (PBLK = 3V) – BLKOF (PBLK = 0V)
LIN/CH = 15kHz, 500mVp-p,
Sine wave + offset voltage
LIN/CH = 3MHz, 500mVp-p, sine wave
RFCONT = 2.7V
15kHz 80mVp-p sine wave
RFCONT = 0.3V
15kHz 500mVp-p sine wave
DIN = 1µs, 1Vp-p pulse
Item
Symbol
Conditions Min. Typ.
Max.
Unit
Current
consumption
AGC
DRV
mA
dB
mV
mV
mV
mV
dB
REF
BLK
AMP
GCA
30
10
9
9
2
28.5
—
27.1
800
900
80
—
25
2300
1300
950
—10
2.5
2.5
9.5
—
600
41.0
13.9
12.2
12.2
3.4
31.3
–0.8
32.1
895
955
98
2
34
2342
1359
983
9
3.43
3.18
12.7
–4.0
815
53
19
17
17
6
—
1.4
—
—
—
—
5
40
2400
1400
1050
23
4.5
4.5
—
–2.5
—
mV
SH3
Page 10
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CXA2056Q
Electrical Characteristics Measurement Circuit
MODE1
L
GND
MODE2
L HH
V1
3V
GND
V2
3V
MODE3
L H
V3
3V
GND
PS
L H
V4
3V
GND
SW2SW1
SW4
SW3
GND GND GND
GND3
LOUTCLP
DRVOUT
V5
1.85V
C5
0.1µ
R1
10k
GND
C6
70pF
R2
22
GND
PL5
XRS
GND
PL4
CLPOB
C7
0.1µF
GND
GND
VRT
GND
VRB
C9
4.7µF
R3
400
SW6
ON
OFF
C8
4.7µF
GND
OFFSET
V6
0 to 3V
GND
VCC3
VCC3
3V
VCC2
GND
VCC2
3V
C4
1µF
GND
PIN
C3
1µF
GND
DIN
AC
V8
C2
0.047µF
GND
PBRFC
AC
V13
GND
V12
0.3 to 2.7V
RFCONT
C1
0.1µF
GND
LIN/
CH
AC
V11
SW5
V10
0 to 3V
ON
OFF
GND
CLPDM
PL1
GND
GND1
GND
SHD
PL2
GND
SHP
PL3
GND
V
CC
1
GND
AGCCONT
CCDLEVEL
N.C
V7
1.5 to 3V
VCC1
3V
AGCCLP
ICONT
GND
GND2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
2
3
4
5
6
7
8
1
N.C
GND
V9
1.5 to 3V
GND
PL6
PBLK
SW1
L
H
H
L
H
L
L
SW2
L
L
L
L
H
H
H
SW3
H
L
H
L
L
L
H
SW5 SW4 MODE
OFF
ON
OFF
H
CAM
LIN
CL
CH
L POWER SAVE
Page 11
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CXA2056Q
Measurement Timing Chart
Different for each test
Different for each test
2.5V
GND
2.5V
GND
2.5V
GND
2.5V
GND
1H
2µs
2µs
1H
Equivalent to CCD
signal black level
PL4 (CLPOB)
PL1 (CLPDM)
PL6 (PBLK)
V8 (DIN)
V11 (CH)
V13 (PBRFC)
V10 + V11 (LIN)
PL2 (SHD)
PL3 (SHP)
PL5 (XRS)
1H
Page 12
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CXA2056Q
Application Circuit
MODE1
GND
MODE2
3V
GND
3V
MODE3
3V
GND
PS
3V
GND
GND GND
GND3
LOUTCLP
DRVOUT
0.1µF
22
N.C
GND
PBLK
GND
XRS
GND
CLPOB
0.1µF
GND
GND
VRT
GND
VRB
4.7µF
4.7µF
GND
OFFSET
0 to 3V
VCC3
VCC2
PIN
1µF
DIN
0.047µF
PBRFC
GND
0.3 to 2.7V
RFCONT
0.1µF
LIN/CH
GND
CLPDM
GND
GND1
GND
SHD
GND
SHP
V
CC
1
GND
AGCCONT
CCDLEVEL
N.C
VAGCCONT
1.5 to 3V
AGCCLP
ICONT
GND
GND2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
2
3
4
5
6
7
8
1
1µF
CCD
VCC
LIN/CH
PBRFC
V
CC
VRB VRT
A/D IN
A/D
CLPDM
SHD SHP
V
CC
PBLK XRS
CLPOB
VRFCONT
VICONT
GND
1.5 to 3V
V
OFFSET
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 13
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CXA2056Q
Description of Operation
Refer to the Block Diagram.
1. Camera signal processing system
Process the video signal processing pins as follows only in camera mode.
<7> LOUTCLP ... Connect to GND.
<29> LIN/CH ... Connect to GND.
<31> RFCONT ... Connect to GND via the capacitor (approx. 0.01µF).
<32> PBRFC ... Connect to GND.
Operating conditions
The camera signal processing system operates when PS is High, MODE1 is Low, MODE2 is Low and MODE3
is High, or when PS is High, MODE1 is High, MODE2 is Low and MODE3 is Low.
Camera signal processing system timing chart (when VCC = 3V)
PBLK
(10µ during the idle
transfer interval)
Sig interval OPB interval
Idle transfer
interval
Sig interval
Precharge level
Signal level
2.1V
2.1V
[∗1]
2µs
0.65V
Black level
Basic black
level
2µs
0.65V
10µs
1.35V
Approx. VRB + 35mV when OFFSET = 0V
Approx. VRB + 100mV when OFFSET = 1.5V
Approx. VRB when OFFSET = 3V
CCD output
SHP
SHD
SH1 output
SH2 output
SH3 output
CLPDM
(2µ dummy bit portion during
the idle transfer interval)
XRS
CLPOB
(2µ during the OPB
interval)
CAMSH
output
BLK SW output
CAM DRVOUT output
AGC output
× (– N)
SH3 output
– SH2 output
[∗2]
[∗3]
[∗4]
[∗5]
Page 14
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CXA2056Q
CDS (SH1, SH2, SH3):
The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS)
is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output
by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the
sample-and-hold circuits for the pre-charge level; SH3 is the sample-and-hold circuit for the signal level.
CDSCLP 1, 2:
CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer
interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([∗1], [∗2]) of SH2 and SH3
in line with VREF. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for
the signal level.
AGC:
AGC is the gain control amplifier for the camera signal.
The gain can be varied from –1 to +31dB by adjusting the AGCCONT voltage control VAGCCONT from 1.5 to
3.0V.
CAM SH:
CAM SH is the sample-and-hold circuit for the camera signal processing system; it synchronizes the data readin timing for the external A/D.
Sampling is possible according to the approximately 10ns sampling pulse width input to XRS.
AGCCLP:
The basic black level is set ([*3]) by clamping the AGC output waveform with the CLPOB clock during the OPB
interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current
so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the
OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin.
DC SHIFT:
This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the
AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black
level is maintained at its previous setting.
BLK SW:
The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not
fall below the basic black level and replacing the DC potential with VRB. ([∗4])
The signal is blanked when PBLK is low.
CVSW:
When the MODE1, 2, 3 and PS pin voltages are set so that the camera signal processing system operates,
CVSW conducts the CAMDRV output (camera signal) into the DRVOUT. In addition, when these voltages are
set so that the video signal processing system operates, CVSW conducts the VIDEODRV output (video signal)
into the DRVOUT.
Page 15
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CXA2056Q
OFFSET:
OFFSET controls the CAMDRV output waveform black level offset.
In the camera signal processing system camera mode, the OFFSET pin is enabled, permitting adjustment of
the offset for the [OFFSET] and DRVOUT camera signals. ([∗5]) The voltage controlled by OFFSET is output
as the CAMDRV output DC offset via AGCLP, DCSHIFT, CAMSH, and BLKSW.
When the OFFSET voltage is 1.5 to 3.0V, DRVOUT DC can vary in a linear fashion from VRB + 100mV to VRB.
In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 35mV.
CAMDRV:
CAMDRV operates in the camera signal processing system mode, driving the external A/D. The current that
flows to the last-stage amplifier in CAMDRV is controlled by applying voltage to the ICONT pin, making it
possible to adjust the rise time of the output waveform, which affects the external A/D load capacitance. The
variable range is 1.5 to 3V, with 1.5V yielding the maximum and 3V yielding the minimum. The optimum rise
time for the external A/D input capacitance can be selected.
VRT DRV, VRB DRV:
These are the external A/D reference voltage drivers. These circuits are connected to A/D VRT and VRB,
supplying 2.35V and 1.35V, respectively, when VCC is 3V. The IC's internal primary voltage is also generated
on the basis of the VRT and VRB voltages. (VRB, VB, and VCENT)
MODE CONTROL & POWER SAVE CONTROL:
This block selects the mode governing the operation of the camera signal system and the video signal system
through the selection of High and Low potential for the MODE1, 2, 3, and PS pins. The PS pin is the POWER
SAVE pin; the power saving function operates when this pin is Low.
2. Video signal processing system
Operating conditions
The video signal processing system has three modes: LIN signal mode, CH signal mode and CL signal mode.
The video signal processing system operates in LIN signal mode when PS is High, MODE1 is High, MODE2 is
Low and MODE3 is High, or when PS is High, MODE1 is Low, MODE 2 is Low and MODE3 is Low.
The video signal processing system operates in CH signal mode when PS is High, MODE1 is Low, MODE2 is
High and MODE3 is High.
The video signal processing system operates in CL signal mode when PS is High, MODE1 is Low, MODE2 is
High and MODE3 is Low, or when PS is High, MODE1 is Low, MODE2 is High and MODE3 is High.
Video signal processing system timing chart (when VCC = 3V)
LIN mode
1.46V
1.4V
LIN/CH input
• LIN CHAMP output (3.5dB)
• DRVOUT output
Page 16
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CXA2056Q
LIN signal mode
In LIN signal mode, LINSW and LOSW close, VISW is set to “1” and the video signal passes through CVSW.
In addition, LINCHAMP, LINCLP, LOUTCLP, VIDC SHIFT, and VIDEO DRV all operate.
LINCLP:
LINCLP is an input clamp circuit that clamps the video composite signal sync level.
The video composite signal is input to LIN/CH pin. LINCLP expands the input dynamic range, and sync tip
clamps the input signal at VB (= 1.4V) to allow full input. The input level and frequency are respectively
571mVp-p (Max.) and DC is up to 7MHz.
LINCHAMP:
LINCHAMP amplifies the LIN signal and the CH (high-band chroma) signal; the gain is fixed at 3.5dB.
VISW:
VISW switches the LIN signal, the CH (high-band chroma) signal, and the CL (low-band chroma) signal. The
signals are switched according to the mode selection.
LOUTCLP:
LOUTCLP is an output clamp circuit that clamps the sync level of the video composite signal that is output
from VIDEO DRV.
Because the VIDEO DRV output signal is fully input to the external A/D, the clamp level is set to VB (= 1.4V).
If the sync level of the signal output from VIDEO DRV drops below VB, LOUTCLP operates: the LOUTCLP
current flows so that the sync level equals VB, and the LOUTCLP potential is set. A clamping capacitor is
connected to the LOUTCLP pin.
VIDC SHIFT:
VIDC SHIFT functions when LOUTCLP operates, following the LOUTCLP potential and forcing a DC shift of
the VIDEO output signal sync level to VB.
VIDEO DRV:
VIDEO DRV outputs the video signal (LIN, CH, CL) to the external A/D in video signal processing mode.
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CXA2056Q
CH (high-band chroma) signal mode
In CH mode, CHSW closes, VISW is set to “2” and the video signal passes through CVSW. In addition,
LINCHAMP and VIDEO DRV operate.
VS1:
The video high-band chroma signal is input to the LIN/CH pin. VS1 expands the input dynamic range and sets a
center DC bias so that the center potential of the SIN signal is 1.85V to allow full input. The input level and
frequency of the CH signal are respectively 470mVp-p (Max.) and from 1 to 7MHz.
VCENT:
VCENT is a DC bias circuit that operates when the CH signal is output to VIDEO DRV. The DC bias potential is
generated from VRT and VRB, and is set to 1.85V.
CH mode
1.85VLIN/CH input
• LINCH AMP output
(3.5dB)
• DRVOUT output
1.85V
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CXA2056Q
CL (low-band chroma) signal mode
In CL mode, VISW is set to “3” and the video signal passes through CVSW. In addition, CLGCA and VIDEO
DRV operate.
VS2:
The video low-band chroma signal is input to the PBRFC pin. VS2 expands the input dynamic range and sets a
center DC bias so that the center potential of the SIN signal is 1.9V to allow full input. The input level and
frequency of the CH signal are respectively 1490mVp-p (Max.) and DC is up to 1.5MHz.
CLGCA:
The CLGCA amplifier controls the gain of the CL signal input to the PBRFC pin. The gain can be varied from
–4 to +12.5dB by adjusting the RFCONT voltage from 0.3 to 2.7V. The phase of the CLGCA output waveform
is reversed in DRVOUT.
VCENT:
VCENT is a DC bias circuit that operates when the CL signal is output to VIDEO DRV. The DC bias potential is
generated from VRT and VRB, and is set to 1.85V.
CL mode
1.9VPBRFC input
• CLGCA output
(–4 to +12.5dB)
• DRVOUT output
1.85V
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CXA2056Q
Example of Representative Characteristics
CAM mode AGCCONT control supply voltage characteristics
V
AGCCONT vs. Gain
VAGCCONT [V]
1.5 2.0 2.5 3.0 3.3
0
10
20
30
35
Gain [dB]
Tc = 27°C
VCC = 3V
VCC = 3.15V
V
CC = 3.3V
CAM mode OFFSET control supply voltage characteristics
V
OFFSET vs. OFFSET
VOFFSET [V]
0 1.0 2.0 3.0 3.3
20
40
60
80
100
OFFSET [mV]
Tc = 27°C
VCC = 3.3V
VCC = 3V
115
CL mode RFGCA gain control supply voltage characteristics
V
RFCONT vs. Gain
VRFCONT [V]
0 1.0 2.0 3.0 3.3
–5
0
10
20
25
Gain [dB]
Tc = 27°C
VCC = 3V
VCC = 3.15V
VCC = 3.3V
–4
(V
RB =) 0
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CXA2056Q
CAM mode AGCCONT control temperature characteristics
AGCCONT vs. Gain
AGCCONT [V]
1.5 2.0 2.5 3.0
0
10
20
30
35
Gain [dB]
VCC = 3.0V
CAM mode OFFSET control temperature characteristics
V
OFFSET vs. OFFSET
VOFFSET [V]
0 1.0 2.0 3.0
50
100
OFFSET [mV]
VCC = 3.0V
150
Tc = –20°C
Tc = +27°C
Tc = +75°C
CL mode RFGCA gain control temperature characteristics
V
RFCONT vs. Gain
VRFCONT [V]
0 1.0 2.0 3.02.7
–5
0
10
20
25
Gain [dB]
0.3
VCC = 3V
Tc = –20°C
Tc = +27°C
Tc = +75°C
(VRB =) 0
–4
Tc = –20°C
Tc = +27°C
Tc = +75°C
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CXA2056Q
CAM mode maximum signal amplitude
temperature characteristics (Min. gain)
Tc vs. Vout
Tc [°C]
–20
0.6
Vout [Vp-p]
0.7
0.8
0 50 100
0.53
VCC = 3.0V, AGCCONT = 1.5V
Input amplitude DIN =
Input amplitude DIN =
Input amplitude DIN =
Input amplitude DIN =
Input amplitude DIN =
870mVp-p
800mVp-p
750mVp-p
700mVp-p
600mVp-p
0.9
DIN = 870mVp-p
DIN = 800mVp-p
DIN = 750mVp-p
DIN = 700mVp-p
DIN = 600mVp-p
LIN, CH mode LINCHAMP gain
temperature characteristics
Tc vs. Gain
Tc [°C]
–20
Gain [dB]
3
3.5
4
0 75
VCC = 3.0V
LIN mode
CH mode
VCC [V]
3
Gain [dB]
3
3.15 3.3
3.5
4
LIN, CH mode LINCHAMP gain supply
voltage characteristics
V
CC vs. Gain
Tc = 27°C
CH mode
LIN mode
CAM mode maximum signal amplitude
temperature characteristics (Max. gain)
Tc vs. Vout
Tc [°C]
–20
0.8
Vout [Vp-p]
0.9
1.0
0 50 100
0.75
VCC = 3.0V, AGCCONT = 3.0V
Input amplitude DIN =
Input amplitude DIN =
Input amplitude DIN =
28mVp-p
24mVp-p
21mVp-p
30.99dB
30.99dB
30.76dB
31.41dB
31.41dB
31.03dB
31.45dB
31.45dB
31.12dB
DIN = 28mVp-p
30.99 dB
+0
–0.23
DIN = 24mVp-p
31.41 dB
+0
–0.38
DIN = 21mVp-p
31.45 dB
+0
–0.33
Gain temperature
characteristics from
–20 to +100°C
Page 22
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CXA2056Q
CH, LIN, CL mode DRVOUT output DC voltage
temperature characteristics
VCC = 3.0V
Tc [°C]
–20
DCOUT
1.4
800 20 40 60
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
1.5
1.45
CL mode
CH mode
LIN mode
Tc [°C]
–20
DCIN
1.4
800 20 40 60
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
1.5
1.45
CL mode
CH mode
LIN mode
VCC = 3.0V
Tc vs. DCIN
VRT, VRB, VRT – VRB temperature characteristics
Tc vs. V
RT, VRB, VRT – VRB
VCC = 3.0V
Tc [°C]
–20
V
RT
, V
RB
, V
RT
– V
RB
[V]
0.8
800 20 40 60
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
VRT
VRB
VRT – VRB
CH, LIN, CL mode input pin DC voltage
temperature characteristics
Tc vs. DCOUT
Page 23
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CXA2056Q
CL mode 2nd/3rd harmonic distortion
temperature characteristics (Max. gain)
VCC = 3.0V, RFCONT = 2.7V
f = 700kHz
Tc [°C]
–20
2nd/3rd Harmonic Distortion [dB]
–80
800 20 40 60
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
2nd: out = 0.75Vp-p
3rd: out = 0.75Vp-p
3rd: out = 0.3Vp-p
2nd: out = 0.3Vp-p
LIN mode 2nd/3rd harmonic distortion
temperature characteristics
VCC = 3.0V
f = 5MHz
Tc [°C]
–20
2nd/3rd Harmonic Distortion [dB]
–80
800 20 40 60
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
2nd: out = 0.9Vp-p
3rd: out = 0.9Vp-p
3rd: out = 0.75Vp-p
2nd: out = 0.75Vp-p
CH mode 2nd/3rd harmonic distortion
temperature characteristics
VCC = 3.0V
f = 5MHz
Tc [°C]
–20
2nd/3rd Harmonic Distortion [dB]
–80
800 20 40 60
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
2nd: out = 0.75Vp-p
3rd: out = 0.75Vp-p
3rd: out = 0.9Vp-p
2nd: out = 0.9Vp-p
CL mode 2nd/3rd harmonic distortion
temperature characteristics (Min. gain)
Tc [°C]
–20
2nd/3rd Harmonic Distortion [dB]
–80
800 20 40 60
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
2nd: out = 0.75Vp-p
3rd: out = 0.75Vp-p
2nd: out = 0.3Vp-p
3rd: out = 0.3Vp-p
VCC = 3.0V, RFCONT = 0.3V
f = 700kHz
Tc vs. 2nd/3rd harmonic distortion
Tc vs. 2nd/3rd harmonic distortion
Tc vs. 2nd/3rd harmonic distortionTc vs. 2nd/3rd harmonic distortion
Page 24
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CXA2056Q
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 ALLOY
32PIN QFP (PLASTIC)
9.0 ± 0.2
7.0 – 0.1
1.5 – 0.15
(8.0)
0.1 – 0.1
+ 0.2
+ 0.35
+ 0.3
0.50
0.127 – 0.05
+ 0.1
0° to 10°
0.8
0.3 – 0.1
+ 0.15
1
8
9
32
16
1724
25
M
0.24
0.2g
QFP-32P-L01
QFP032-P-0707
0.1
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