Datasheet CXA2125Q Datasheet (Sony)

Audio/Video Switch with Electronic Volume for 3 Scart

Description

The CXA2125Q is an I2C programmable audio, video
switch designed primarily for set top box applications. It
interfaces from digital encoder sources to TV, VCR and
auxiliary scart connectors.

Features

• 3 scart independent audio/video switching (TV, VCR,

AUX)

• 0 to –63dB volume control with click noise reduction

• 5 stereo audio inputs

• I2C control

• Scart Function Switching input and output

• Scart Fast Blanking for OSD

• Mono switchable to stereo on TV, VCR and AUX outputs

• On-chip +12V to +9V voltage regulator

• Logic output

• Selectable +6dB, +12dB gain on TV output

• RGB input on VCR scart

• Compatible with 2 scart Audio/Video switch CXA2126Q

Applications

Digital Set Top Box

Structure

Bipolar silicon monolithic IC

Absolute Maximum Ratings

• Supply voltage VCC 12 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 850 mW

Operating Conditions

• Supply voltage 10.7 to 12 V

• Operating voltage 9 ± 0.5 V

– 1 –

E99338-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA2125Q

64 pin QFP (Plastic)

– 2 –

CXA2125Q

Block Diagram

× 2

× 2

ROUT2

31

LOUT2

32

MONO SWITCH

× 2

× 2

ROUT1

34

LOUT1

36

8dB 1dB 0/6dB

MONO SWITCH

Selectable Gain Stage

MONO SWITCH

VOUT7

100Ω

× 2

× 2

× 2

× 2

× 2

× 2

FBLK_IN1DIG

Typical Connection

VCR
AUX

DIG BLUE
VCR BLUE
AUX BLUE

DIG GREEN/CVBS

VCR GREEN
AUX GREEN

DIG RED/CHROMA

DIG CHROMA
VCR RED/CHROMA
AUX RED/CHROMA

DIG CVBS/LUMA

DIG CVBS/LUMA
VCR CVBS/LUMA
AUX CVBS/LUMA

TV CVBS

DIG
VCR
AUX
TV
ANALOGUE SAT

DIG
VCR
AUX
TV
ANALOGUE SAT

ANALOGUE SAT CVBS

TV_FBLANK

+5V

0V

FBLK_IN2

FBLK_SW

100Ω

FBLK_IN3

VIN1
VIN2
VIN3

VIDEO_SWITCH1 (TV)

VIN4
VIN5
VIN6

VIN7
VIN8
VIN9

VIN10
VIN11

VIN12
VIN13
VIN14
VIN15
VIN16

VIDEO_SWITCH2 (VCR)

VIDEO_SWITCH3 (AUX)

AUDIO_SWITCH1 (TV)

VOLUME CONTROL

& MUTE

8dB

ZCD

1dB 0/6dB

52
53
51

63
61
13

2
59
15

4

6
57
17

8
10
55
21
23
25

VID_V

CC

VID_BIAS

VID_GND

60
62

7

Bias

Bias

4.5V

Mute

Bias 1

4.05V

AUD_VCC

DIG_VCC

AUD_BIAS
AUD_GND

DIG_GND

20
19
26

Bias 2

4.5V

VCC_12V

VREG_BASE

VREG_9V

58
56

38
43

54

RIN1

3

RIN2

12

RIN3

16

RIN4

22

RIN5

27

9V reg

–6dB
–6dB
–6dB
–6dB

LIN1

5

LIN2

14

LIN3

18

LIN4

24

LIN5

29

–6dB
–6dB

HW_MUTE

45

SDA

11

SCL

9

FNC_VCR

64

FNC_AUX

1

Monitor
Monitor

–6dB
–6dB

TV BLUE

TV GREEN

TV RED/C

TV CVBS/Y

VCR CHROMA

AUX CVBS

VCR CVBS/Y

Typical Connection

50

VOUT1

100Ω

48

× 2

VOUT2

100Ω

47

× 2

VOUT3

100Ω

46

× 2

VOUT4

100Ω

49

× 2

VOUT5

100Ω

41

× 2

VOUT6

100Ω

44

FNC_TV

30

LOGIC

28

× 2

39

MONO

33

PHONO_R

35

RTV

40

LTV

TV

42

PHONO_L

37

AUDIO_SWITCH2 (VCR)

AUDIO_SWITCH3 (AUX)

I

2

C

Interface

LOGIC

P.O.D

VCR

AUX

TV

VCR

AUX

3.3V or 5V

– 3 –

CXA2125Q

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

28

29

30

31

32

36373839404142434445464748495051

52
53
54
55
56
57
58
59
60
61
62
63
64

FBLK_IN1
FBLK_IN2
VREG_9V

VIN13

VREG_BASE

VIN9

V

CC_12V

VIN5

VID_V

CC

VIN2

VID_BIAS

VIN1

FNC_VCR

FNC_AUX

VIN4

RIN1

VIN7

LIN1

VIN8

VID_GND

VIN11

SCL

VIN12

SDA

RIN2

VIN3

LIN2

VIN6

RIN3

17 18 19

VIN10

LIN3

AUD_BIAS

FBLK_IN3

TV_FBLANK

VOUT4

VOUT1

VOUT2

VOUT3

HW_MUTE

VOUT6

DIG_GND

LTV

VOUT5

RTV

VOUT7

DIG_V

CC

PHONO_L

LOUT1

333435

PHONO_R

ROUT1

MONO

LOUT2
ROUT2
FNC_TV
LIN5
LOGIC
RIN5
AUD_GND
VIN16
LIN4
VIN15
RIN4
VIN14
AUD_V

CC

Pin Configuration

– 4 –

CXA2125Q

Pin Description

Pin

No.

Symbol

Pin
voltage

Equivalent circuit Description

63
61
13

2
59
15
55
23

4

6
57
17

8
10
21
25

V

CC = 12V VCC = 9V

14µA

120kΩ

147Ω

60µA

VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
VIN16

4.6V

Video signal inputs.
An input coupling
capacitor is required.
(typ = 0.47µF)

63
61
13

2
59
15

4

6
57
17

8
10
55
21
23
25

12
16
22
27

14
18
24
29

VCC = 12V

33kΩ

33kΩ

7µA

4.5V

RIN2
RIN3
RIN4
RIN5

LIN2
LIN3
LIN4
LIN5

4.5V

Audio signal inputs.
An input coupling
capacitor is required.
(typ = 2.2µF)

12
16
22
27

14
18
24
29

48
47
46
49
41
44
39

V

CC = 12V VCC = 9V

140µA

280µA

200Ω

100Ω

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7

3.9V

Video signal outputs.

48
47
46
49
41
44
39

– 5 –

CXA2125Q

35
37
33
40
34

31
42
36
32

V

CC = 12V VCC = 9V

55Ω

20kΩ

22kΩ

20kΩ

33µA

33µA

RTV
ROUT1
ROUT2
LTV
LOUT1
LOUT2
PHONO_R
PHONO_L
MONO

4.5V

Audio signal outputs.
A coupling capacitor may
be used.
(typ = 10µF)

40
34
31
42
36
32
35
37
33

Pin
No.

Symbol

Pin
voltage

Equivalent circuit Description

62

V

CC = 12V VCC = 9V

14µA

11kΩ

9kΩ

200Ω

BIAS_
VIDEO

3.9V

Reference Bias for video
circuit.
Connected to GND with
capacitor.
(typ = 47µF)

62

7µA

19

V

CC = 12V VCC = 9V

20kΩ

20kΩ

BIAS_
AUDIO

4.5V

Reference Bias for audio
circuit.
Connected to GND with
capacitor.
(typ = 22µF)

19

30

V

CC = 12V

120Ω

3kΩ

15kΩ

FNC_TV

—

I2C controlled output
giving 0V, 6V or 12V.

30

– 6 –

CXA2125Q

Pin

No.

Symbol

Pin
voltage

Equivalent circuit Description

120µA

54

V

CC = 12V

77.7kΩ

13.5kΩ

VREG_9V

9V

Pin connected to emitter
of external regulator
transistor.

54

56

V

CC = 12V VCC = 12V

1mA

120µA

413Ω
15pF

VREG_
BASE

9.7V

Connection to base of
external regulator
transistor.
Max I = 1mA

56

9

VCC = 9V

40µA

4kΩ

10kΩ

40kΩ

SCL

—

I2C clock input.

9

11

VCC = 9V

40µA

4kΩ

4.5kΩ

40kΩ

SDA

—

I2C data input/output.

11

– 7 –

CXA2125Q

Pin

No.

Symbol

Pin
voltage

Equivalent circuit Description

VCC = 12V

45

147Ω

28kΩ

72kΩ

HW_MUTE

—

HW MUTE: This pin is
active high > 2.5V < 9V.
When high, all audio
muted.

45

28

V

CC = 12V VCC = 9V

8µA

7.5kΩ

3V

4.5kΩ

40kΩ

LOGIC

—

Open collector logic pins.

28

50

V

CC = 12V VCC = 9V

100µA

100µA

100Ω

100Ω

FBLK_
OUT

—

Fast Blank output set by
I2C to input FBLK_IN1,
FBLK_IN2, or FBLK_IN3.

High = 5.3V

Low = 1.2V
Connected to external
emitter follower.

50

52
53
51

V

CC = 12V

VCC = 9V

147Ω

90µA

50µA

FBLK_IN1
FBLK_IN2
FBLK_IN3

—

Fast Blank inputs.

Low = < 0.4V
High = > 1.0V, < 3.0V

52
53
51

– 8 –

CXA2125Q

Pin

No.

Symbol

Pin
voltage

Equivalent circuit Description

80µA

64

1

12.5kΩ 12.5kΩ

10kΩ

25kΩ

VCC = 9V

FNC_VCR
FNC_AUX

—

Function switching input.
(Scart pin 8)

64

1

3
5

V

CC = 12V

33kΩ

7µA

4.5V

RIN1
LIN1

4.5V

Audio signal inputs.
A coupling capacitor is
required for these inputs.
(typ = 2.2µF)

3
5

– 9 –

CXA2125Q

Electrical Characteristics

Nominal conditions (Ta = 25°C)

VCC_12V = 12V, No signal, no load

Current consumption ICC 30 50 80 mA

Item Symbol Conditions Min. Typ. Max. Unit

Video system Nominal conditions (Ta = 25°C, Vcc_12V = 12V, VREG_9V = 9V)

Input pin voltage
Output pin voltage – with

output on.
Output pin voltage – with

output off.
Gain

Bandwidth

Input dynamic range
Output dynamic range
Cross talk

S/N ratio

Input impedance

Non-linearity

Differential gain

Differential phase

Sync crush

VVPin
VVPout1

VVPout2
GVv

fV3dB

VDRVI
VDRVO
Vctv

S/NV

ZinV

Lin

DG

DP

SC

4.3

3.6

—

5.5

15

2.5

5.0
—

—

94

–3

–3

–3

–2

4.6

3.9

0

6.0

20

—
—
—

72

120

–0.4

1.5

1

0

4.9

4.2

0.2

6.5

—

—
—

–50

—

175

3

2

2

2

V
V

V

dB

MHz

Vp-p
Vp-p

dB

dB

kΩ

%

%

Deg

%

Item Symbol Conditions Min. Typ. Max. Unit

V2

V1 × 2

No signal, no load (Fig.1)
No signal, no load (Fig.1)

No signal, no load (Fig.1)
f = 200kHz, 0.3Vp-p input (Fig.2)

0.3Vp-p input, frequency where output
level is –3dB with 200kHz serving as
0dB (Fig. 2)

200kHz input (Fig.2)
200kHz, 2.5Vp-p input (Fig.2)
f = 4.43MHz, 1Vp-p input (Fig.2)
Ratio of 0.7Vp-p white video signal to

"black line" noise. Weighted using CCIR

567. HPF @5kHz, LPF @5MHz. (Fig.2)
1Vrms 1kHz input through 56kΩ.

Attenuation measured to calculate ZinV
(Fig.3)

(Fig.4)

V1 = Pin voltage +0.5V,
V2 = Pin voltage +1V

At output, non-linearity = –1 × 100

1.7Vp-p 5-step modulated staircase.
(Chroma and Burst are 150mVp-p

4.43MHz) (Fig.2)
as above. (Fig.2)
Percentage reduction in sync pulse

(0.4Vp-p), with tip at –1.2V input offset.
(Fig.4)

V2

V1

Input Pin V

Plus

– 10 –

CXA2125Q

Audio system

Unless otherwise stated: input coupling capacitor 1µF; output coupling capacitor of 10µF; load of 10kΩ.

Nominal conditions (Ta = 25°C, Vcc_12V = 12V, VREG_9V = 9V)

No signal, no load (Fig. 5)

f = 1kHz, 0.5Vrms input.
TV output amplifier set to 0dB (Fig. 6)

f = 1kHz, 0.5Vrms input.
TV output amplifier set to +6dB (Fig. 6)

f = 1kHz, 1Vrms input. (Fig. 6)
f = 1kHz, 0.5Vrms stereo input.

TV output amplifier set to 0dB (Fig. 6)
f = 1kHz, 0.5Vrms stereo input.

TV output amplifier set to +6dB (Fig. 6)
f = 1kHz, 0.5Vrms stereo input. (Fig. 6)
f = 1kHz, 1Vrms input.

TV output amplifier set to 0dB (Fig. 6)
f = 1kHz, 1Vrms input.

TV output amplifier set to +6dB (Fig. 6)
f = 1kHz, 1Vrms stereo input.

TV output amplifier set to 0dB (Fig. 6)
f = 1kHz, 1Vrms stereo input.

TV output amplifier set to +6dB (Fig. 6)
f = 1kHz, 1Vrms input. (Fig. 6)

f = 1kHz, 1Vrms stereo input. (Fig. 6)

0.3Vp-p input. Output level at 30kHz
with 1kHz serving as 0dB. (Fig. 7)

0.3Vp-p input; frequency where output
level is –3dB with 1kHz serving as 0dB.
No load (Fig. 7)

f = 1kHz, 0.5Vrms, unweighted response;
LPF @400Hz, HPF @80kHz. (Fig. 6)

f = 1kHz (Fig. 6)

f = 1kHz (Fig. 6)
f = 1kHz, 1Vrms input on one input,

measure on any other audio output.
(Fig.6)

Input/output pin voltage

Audio frequency response

Frequency B/W

Distortion
Input dynamic range

RIN2, 3, 4, 5 LIN2, 3, 4, 5
Input dynamic range

RIN1 LIN1
Cross talk

(Channel separation)

VAPIN

GVA1

GVA2
GVA3
GVA4

GVA5

GVA6

GVA7

GVA8

GVA9

GVA10

GVA11

GVA12

FAF

FBWA1

THD

VdA1

VdA2

VctA

4.2

5.5

11
—
—

—

—

–0.5

5.5

–0.7

5

–0.5

–0.7

–0.3

—

—

2

1

—

4.5

6

12

6
6

12

6

0

6

0

6

0

0

0

1

0.003

—

—

—

4.8

6.5

13
—
—

—

—

+0.5

6.5

+0.3

7

+0.5

+0.3

+0.3

—

0.2

—

—

–76

V

dB

dB
dB
dB

dB

dB

dB

dB

dB

dB

dB

dB

dB

MHz

%

Vrms

Vrms

dB

Item Symbol Conditions Min. Typ. Max.

Unit

Output

TV/Phono

TV/Phono
VCR/AUX
TV mono

TV mono
VCR mono

AUX mono
TV/Phono

TV/Phono

TV mono

TV mono

VCR/AUX
VCR mono

AUX mono

Gain Input
RIN1/LIN1

RIN1/LIN1
RIN1/LIN1
RIN1 + LIN1

RIN1 + LIN1

RIN1 + LIN1
RIN2, 3, 4, 5

LIN2, 3, 4, 5
RIN2, 3, 4, 5

LIN2, 3, 4, 5
RIN2, 3, 4, 5

+ LIN2, 3, 4, 5
RIN2, 3, 4, 5

+ LIN2, 3, 4, 5
RIN2, 3, 4, 5

LIN2, 3, 4, 5
RIN2, 3, 4, 5

+ LIN2, 3, 4, 5

– 11 –

CXA2125Q

Offset voltage between input and
output (Fig. 5)

(excluding any external series resistor)

(excluding any external series resistor)
(excluding any external series resistor)

f = 1kHz, 1Vrms input to two channels.
Phase difference of stereo output
measured

f = 1kHz, 1Vrms input (at maximum
volume).
HPF @20Hz, LPF@20kHz. (Fig. 6)

f = 1kHz, 0.5Vrms input. Set by I2C.
(Fig.6)

f = 1kHz, 0.5Vrms input. Set by I2C.
(Fig.6)

f = 1kHz, 1Vrms input. (Fig.6)
Offset voltage between any audio input

and RTV, LTV outputs. (Fig.5)

DC offset
Input impedance

RIN2, 3, 4, 5 LIN2, 3, 4, 5
Input impedance

RIN1/LIN1
Output impedance

Phase difference

S/N ratio

Electronic Volume Control

Fine volume attenuation
step

Coarse volume attenuation
step

Mute
DC Offset -RTV, LTV

Voff

Zin1

Zin2
Zout

Vpda

S/NA

AEVC

AEVF
Amute
VoffTV

–30

—

—
—

—

80

0.6

7.5
—

–30

—

66

33
10

0.05

90

1

8

—

0

+30

—

—
—

—

—

1.4

8.5
–80
+30

mV

kΩ

kΩ

Ω

Deg

dB

dB

dB
dB

mV

Item Symbol Conditions Min. Typ. Max. Unit

– 12 –

CXA2125Q

High level input voltage
Low level input voltage
Low level output voltage
Maximum clock frequency
Minimum waiting time for

data change
Minimum waiting time for

data transfer start
Low level clock pulse width
High level clock pulse width
Minimum waiting time for

start preparation
Minimum data hold time
Minimum data preparation

time
Rise time
Fall time
Minimum waiting time for

stop preparation

I2C Electrical Characteristics

Nominal conditions (Ta = 25°C, Vcc_12V = 12V, VREG_9V = 9V)

With SDA, 3mA current supplied

VIH
VIL
VOL
fSCL

tBUF

tHD;STA
tLOW

tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR

tF
tSU;STO

2.3
0
0
0

4.5

4.0

4.7

4.0

4.7
5

250

—
—

4.7

—
—
—
—

—

—
—

—
—
—
—
—

—
—

5.0

1.5

0.4

100

—

—
—

—
—
—
—

1

300

—

V
V
V

kHz

µs

µs
µs

µs
µs

s
ns
µs

ns
µs

Item Symbol Conditions Min. Typ. Max. Unit

– 13 –

CXA2125Q

47µF

BC547B

+12V +9V

22µF

SDASCL

+9V

+9V

+9V

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

Measurement
point

Measurement
point

V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

28

29

30

31

32

36373839404142434445464748495051

52
53
54
55
56
57
58
59
60
61
62
63
64

17 18 19

333435

CXA2125Q

V

Fig. 1. Video system (d.c. test)

d.c. measured from pins: 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 39, 41, 44, 46, 47, 48, 49, 55, 57, 59, 61, 63

Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.

2. All video outputs are loaded with emitter follower during tests.

– 14 –

CXA2125Q

2.2µF

Input
signal

47µF

75Ω

2.2µF

75Ω

2.2µF

75Ω

2.2µF

BC547B

+12V

+9V

75Ω

2.2µF

75Ω

22µF

2.2µF

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

2.2µF

2.2µF

2.2µF

2.2µF

2.2µF

SDASCL

+9V

+9V

+9V

2.2µF

2.2µF

1kΩ

+12V

BC547B

2.2µF

75Ω

75Ω

75Ω

2.2µF

2.2µF

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

Measurement
point

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

28

29

30

31

32

36373839404142434445464748495051

52
53
54
55
56
57
58
59
60
61
62
63
64

17 18 19

333435

CXA2125Q

V

Signal applied to Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63
Output signal measured from Pins 39, 41, 44, 46, 47, 48, 49

Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.

2. For tests requiring video measuring equipment with 75Ω input impedance, an external video line
driver or buffer is used.

3. All video outputs are loaded with emitter follower during tests.

Fig. 2. Video system (gain, dynamic range, bandwidth, differential gain, differential phase,

crosstalk, signal to noise)

– 15 –

CXA2125Q

2.2µF

47µF

56kΩ

2.2µF

56kΩ

2.2µF

56kΩ

2.2µF

BC547B

+12V +9V

56kΩ

2.2µF

56kΩ

22µF

2.2µF

56kΩ

56kΩ

56kΩ

56kΩ

56kΩ

56kΩ

56kΩ

56kΩ

2.2µF

2.2µF

2.2µF

2.2µF

2.2µF

SDASCL

+9V

+9V

+9V

2.2µF

2.2µF

2.2µF

56kΩ

56kΩ

56kΩ

2.2µF

2.2µF

Input
signal

1kHz

Measurement
point

V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

28

29

30

31

32

36373839404142434445464748495051

52
53
54
55
56
57
58
59
60
61
62
63
64

17 18 19

333435

CXA2125Q

Fig. 3. Video system (input impedance)

Signal applied and measured from Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63

Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.

2. Voltage measurements carried out with a high input impedance DVM. Typically 10GΩ.

– 16 –

CXA2125Q

47µF

BC547B

+12V +9V

22µF

SDASCL

+9V

+9V

+9V

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

1kΩ

+12V

BC547B

Measurement
point

Input
signal

PSU

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

28

29

30

31

32

363738394041

42

434445464748

49

5051

52
53
54
55
56
57
58
59
60
61
62
63
64

17 18 19

333435

CXA2125Q

V

Fig. 4. Video system (linearity)

Signal applied to Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63
Output signal measured from Pins 39, 41, 44, 46, 47, 48, 49

Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.

2. All video outputs are loaded with emitter follower during tests.

– 17 –

CXA2125Q

47µF

BC547B

+12V +9V

22µF

SDASCL

+9V

+9V

+9V

Input
measurement
point

Output
measurement
point

V

V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

28

29

30

31

32

36373839404142434445464748495051

52
53
54
55
56
57
58
59
60
61
62
63
64

17 18 19

333435

CXA2125Q

HW

mute

+5V

1kΩ

SW1

Fig. 5. Audio system (d.c. tests)

d.c. measured from pins: 3, 5, 12, 14, 16, 18, 22, 24, 27, 29, 31, 32, 33, 34, 35, 36, 37, 40, 42

Note) All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.

– 18 –

CXA2125Q

47µF

BC547B

+12V +9V

22µF

2.2µF

600Ω

600Ω

600Ω

600Ω

600Ω

2.2µF

2.2µF

SDASCL

+9V

+9V

2.2µF

2.2µF

600Ω

2.2µF

600Ω

600Ω

2.2µF

2.2µF

600Ω

600Ω

2.2µF

2.2µF

10µF

10µF

Input
signal

Measurement
point

V

CXA2125Q

10kΩ

10µF

10µF

10µF

10µF

10µF

10µF

10µF

+9V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

28

29

30

31

32

36

3738394041424344454647484950

51

52
53
54
55
56
57
58
59
60
61
62
63
64

17 18 19

33

3435

HW

mute

+5V

1kΩ

SW1

Signal applied to Pins, 3, 5, 12, 14, 16, 18, 22, 24, 27, 29
Output signal measured from Pins 31, 32, 33, 34, 35, 36, 37, 40, 42

Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.

2. When muting audio using hardware mute, SW1 is closed.

Fig. 6. Audio system (gain, dynamic range, signal to noise, crosstalk, distortion, volume control)

– 19 –

CXA2125Q

47µF

BC547B

+12V +9V

22µF

2.2µF

600Ω

600Ω

600Ω

600Ω

600Ω

2.2µF

2.2µF

SDASCL

+9V

+9V

2.2µF

2.2µF

600Ω

2.2µF

600Ω

600Ω

2.2µF

2.2µF

600Ω

600Ω

2.2µF

2.2µF

10µF

10µF

Input
signal

Measurement
point

V

CXA2125Q

10µF

10µF

10µF

10µF

10µF

10µF

10µF

+9V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

28

29

30

31

32

36373839404142434445464748495051

52
53
54
55
56
57
58
59
60
61
62
63
64

17 18 19

333435

HW

mute

+5V

1kΩ

SW1

Signal applied to Pins, 3, 5, 12, 14, 16, 18, 22, 24, 27, 29
Output signal measured from Pins 31, 32, 33, 34, 35, 36, 37, 40, 42

Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.

2. When muting audio using hardware mute, SW1 is closed.

Fig. 7. Audio system (bandwidth)

– 20 –

CXA2125Q

GREEN

Digital Encoder

2.2µF

2.2µF

1µF

1µF

10µF

10µF

560Ω

10µF

560Ω

1µF

1µF

47µF

10nF10µF

75Ω

75Ω

1kΩ

2.2µF

+12V

+12V

+12V

2.2µF

2.2µF

2.2µF

BC547B

CXA2125Q

BC547B

BC547B

BC547B

2.2µF

2.2µF

2.2µF 2.2µF

22µF

10µF

2.2µF

1µF

1µF

10kΩ

10nF

10µF 10nF

RED CHROMAAUDIO R AUDIO LFAST BLANK BLUE CVBS LUMA

I

2

C

1µF

TV SCART

VCR SCART

AUX SCART

1kΩ

10kΩ

75Ω

560Ω

10kΩ

75Ω

191721

151311

9

753

1

2018161412

10

864

2

191721

151311

9

753

1

2018161412

10

864

2

191721

151311

9

753

1

2018161412

10

864

2

75Ω

1kΩ

75Ω

75Ω

75Ω

10µF

560Ω

10µF

560Ω

10µF

560Ω

10µF

BC547B

+12V

75Ω

BC547B

75Ω

1kΩ

RF

Modulator

Phono

Outputs

L R

BC547B

75Ω

1kΩ

BC547B

75Ω

1kΩ

BC547B

+12V

75Ω

1kΩ

1µF

CVBS

Audio R

Audio L

Analogue

Satellite

75Ω

75Ω 75Ω 75Ω

75Ω

2.2µF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

20

21

22

23

24

25

26

27

282930

31

32

363738394041

42
434445464748

49
5051

52535455565758596061626364

FBLK_IN1

FBLK_IN2

VREG_9V

VIN13

VREG_BASE

VIN9

V

CC_12V

VIN5

VID_V

CC

VIN2

VID_BIAS

VIN1

FNC_VCR

FNC_AUX

VIN4

RIN1

VIN7

LIN1

VIN8

VID_GND

VIN11

SCL

VIN12

SDA

RIN2

VIN3

LIN2

VIN6

RIN3

17 18 19

VIN10

LIN3

AUD_BIAS

FBLK_IN3

TV_FBLANK

VOUT4

VOUT1

VOUT2

VOUT3

HW_MUTE

VOUT6

DIG_GND

LTV

VOUT5

RTV

VOUT7

DIG_V

CC

PHONO_L

LOUT1

333435

PHONO_R

ROUT1

MONO

LOUT2

ROUT2

FNC_TV

LIN5

LOGIC

RIN5

AUD_GND

VIN16

LIN4

VIN15

RIN4

VIN14

AUD_V

CC

Application Circuit

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 21 –

CXA2125Q

Description of Operation

1. Explanation of Video Section

The video section comprises of 16 high impedance inputs switched through to 7 video outputs. A +6dB internal
amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation which
occurs at the external emitter follower stage used for driving video loads. All video outputs have an integrated
100Ω series protection resistor. The typical external configuration is shown in Fig. 1-1.

Amp

Switch

1kΩ

120kΩ75Ω

75Ω 0.47µF

Vbias

Vbias

Video Element

75Ω

75Ω

Load

+12V

Scart Out

Scart In

BC547B100Ω

VID_V

CC = 9V

Fig. 1-1. Video Circuit Element: 6dB gain amplifier with external emitter follower

Switching the Video Outputs Off

Each video output can be individually turned off using the I2C. When turned off, the output dc voltage is
approximately 0V and hence the current consumption of the external emitter followers is reduced.

– 22 –

CXA2125Q

2. Explanation of Audio System

Inputs and Outputs

The audio system consists of 5 stereo inputs, 3 stereo outputs and separate mono and phono outputs. The
stereo outputs can be connected to any one of the 5 stereo inputs. All audio inputs have a –6dB attenuator
except RIN1 and LIN1. Thus, the net gain of the audio system is 0dB, as the internal switch is followed by an
audio amplifier having +6dB of gain. The stereo input RIN1/LIN1 does not have an input attenuator and
therefore the net gain from input to output is +6dB. The output impedance of each audio amplifier is near zero,
and can be capacitively coupled directly to the external scart circuit. The output circuitry is typically a 10µF
capacitor, and an optional 560Ω series compliance resistor. Depending on the length and type of cable used in
the scart cable connector, the load seen at the scart terminal will consist of a parallel capacitor, (100pF to
400pF) and mandatory 10kΩ resistor connected to ground. The customer may chose to place an alternative
audio filter at the AV switch output.

TV Audio Output

The TV audio section is composed of an audio switch followed by two variable gain stages, corresponding to
the coarse and fine electronic volume control. The coarse volume control gives a 0 to –56dB range in 8dB
steps. Similarly the fine control gives a 0 to –7dB range in 1dB steps. The volume control section is followed by
a switchable 0/+6dB amplifier which allows compensation for low level signals from a DAC. Finally, a mono
switch allows the mixed R + L signal to be switched to the R and L output channels. (Fig. 2-1)

Fig. 2-1. TV Audio Output

TV Mute

The I2C mute function acts only on the TV, phono and mono audio circuit. Audio mute can be implemented
after a audio zero cross detection to reduce click noise, or immediately depending on the I2C setting of ZCD. It
can be seen from the I2C write format that the same mute bit occurs in DATA 1 and DATA 7. This allows the
software to action an immediate mute, make any suitable changes to the audio source or electronic volume
control and after a minimum period of 6 × 90µs (540µ s) un-mute the output buffer. Such a period provides
ample time to allow any transient ac voltages to settle during an audio source change.

10µF

560Ω

C

Scart Pin

Optional
Low Pass Filter

TV Audio Output

Volume Control

8dB 1dB 0/6dB

MONO

SWITCH

× 2

× 2

× 2

× 2

8dB

ZCD

1dB 0/6dB

RIN1

1µF

Audio
Source

3

RIN2

12

RIN3

16

RIN4

22

RIN5

27

–6dB
–6dB
–6dB
–6dB

LIN1

5

LIN2

14

LIN3

18

LIN4

24

LIN5

29

–6dB
–6dB
–6dB
–6dB

Mute

PHONO_R

35

RTV

40

LTV

42

PHONO_L

37

– 23 –

CXA2125Q

Zero Cross Detector (ZCD)

The zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio
mute. The change volume or mute instruction sent by I2C will only be implemented when a minimal (ie zero
cross) signal amplitude is detected.
The zero cross detection circuit can be turned off by setting the "ZCD" bit low in the I2C write mode.

Hardware Mute

A hardware mute pin is provided which will mute all audio outputs when the pin voltage exceeds 2.5V. This
muting is instantaneous.

VCR and AUX Output

The outputs ROUT1, 2 and LOUT1, 2 have a fixed gain of 0dB from the input. If any attenuation is required
then it is possible to insert a series resistance on the input. (Fig. 2-2)

10µF

560Ω

C

Scart Pin

Optional
Low Pass Filter

VCR and AUX Audio Circuit

MONO

SWITCH

× 2

× 2

RIN1

1µF

Audio
Source

3

RIN2

12

RIN3

16

RIN4

22

RIN5

27

–6dB
–6dB
–6dB
–6dB

LIN1

5

LIN2

14

LIN3

18

LIN4

24

LIN5

29

–6dB
–6dB
–6dB
–6dB

Mute

ROUT1/2

34

•

31

36

•

32

LOUT1/2

Fig. 2-2. VCR and AUX Audio Output

Phono Outputs

There is a stereo phono output which carries the same signal as the TV output. This is typically used for
connection to a hi-fi. The user may connect an external attenuator which is a.c. coupled to the outputs.

– 24 –

CXA2125Q

I2C Data Interface Table

IC Control Data Format

Slave address

A DATA1 A DATA2 A DATA3 A DATA4 A DATAn A P

S

S: Start condition A: Acknowledge P: Stop condition

Address = 90H

I2C Data Structure (write mode)

Address
Data1

Data2

Data3

Data4
Data5
Data6

Data7

b7

1

EVC

Vid_Switch 1

TV

Vid_Switch 2

VCR

Vid_Switch 3

AUX

mono

VCR

mono

TV

mono

AUX

FBLK

FNC

LOGIC

TV Aud

Gain

Vout5

Mute

Not used Not used

Not used

Not usedNot used
Not used
Not used

Not used Not used Not used

Not used

TV Aud

Mute

b6

0

b5

0

b4

1

EVF

b3

0

b2

0

b1

0

b0

0 = Write

TV Aud

Mute

Z.C.D

Aud_Switch 1

TV

Aud_Switch 2

VCR

Aud_Switch 3

AUX

Vout2

on/off

Vout3

on/off

Vout4

on/off

Vout1
on/off

Vout6

on/off

Vout7

on/off

Vout5

on/off

Key

EVC: Electronic Volume Course (8dB steps)
EVF: Electronic Volume Fine (1dB steps)
TV Aud Mute: TV Audio mute. Controls the TV audio output buffer. (Same bit appears in data 1 & 7)
Z.C.D: Zero cross detector active. When ZCD = 1 volume and mute change at zero cross.
Vid_Switch 1: Selects the input video sources for Vout1, Vout2, Vout3, Vout4
Vid_Switch 2: Selects the input video sources for Vout5, Vout6
Vid_Switch 3: Selects the input video sources for Vout7
Aud_Switch 1: Selects one of 5 stereo inputs for RTV, LTV, PHONO_L, PHONO_R, MONO
Aud_Switch 2: Selects one of 5 stereo inputs for Rout1, Lout1
Aud_Switch 3: Selects one of 5 stereo inputs for Rout2, Lout2
FNC: Video function switch control
FBLK: Video Fast Blanking control
LOGIC: Logic outputs (open collector). 0 = high impedance. 1 = current sink mode.

– 25 –

CXA2125Q

I2C Data Format (read mode)

Slave address A DATA8 PNAS

NA: No Acknowledge

I2C Data Structure (read mode)

Address
Data

b7

1
x

b6

0
x

b5

0

ZC Status

b4

1

P.O.D. FNC_AUX

b3

0

b2

0

b1

0

b0

1 = Read

FNC_VCR

Key

FNC_VCR: At Pin 64, AV switch monitors the voltage of pin 8 from VCR scart, and records status.
FNC_AUX: At Pin 1, AV switch monitors the voltage of pin 8 from AUX scart, and records status.
ZC Status: ZC Status = 1 indicates that zero cross condition has been achieved after the ZCD is turned on.
P.O.D.: Power On Detect. P.O.D. = 1 when DIG_VCC voltage rises above a threshold level of

approximately 5V.

– 26 –

CXA2125Q

3. Video Input I2C Control

Switch 1 (TV Output) Data 2 Bits 3, 4, 5

Vout1

(B)

Switch setting

Vout2

(Green)

Vout3

(R/C)

Vout4

(CVBS/Y)

Comment

VIN1

Bias
VIN2
VIN3

Bias

Bias

Bias

Bias

0 x x 0 0 0 x x x
1 x x 0 0 1 x x x
2 x x 0 1 0 x x x
3 x x 0 1 1 x x x
4 x x 1 0 0 x x x
5 x x 1 0 1 x x x
6 x x 1 1 0 x x x
7 x x 1 1 1 x x x

VIN4

Bias
VIN5
VIN6

Bias

Bias

Bias

Bias

VIN7
VIN8
VIN9

VIN10

VIN7

Bias
Bias
Bias

VIN11
VIN12
VIN13
VIN14

VIN4
VIN15
VIN16

Bias

Digital encoder
Digital encoder
VCR
AUX
Digital encoder
TV
Analogue satellite
Video mute

Vout5

(Chroma (C))

Switch setting

Vout6

(CVBS/Y)

Comment

VIN7
VIN8
VIN9

VIN10

VIN7

Bias
Bias
Bias

0 x x 0 0 0 x x x
1 x x 0 0 1 x x x
2 x x 0 1 0 x x x
3 x x 0 1 1 x x x
4 x x 1 0 0 x x x
5 x x 1 0 1 x x x
6 x x 1 1 0 x x x
7 x x 1 1 1 x x x

VIN11
VIN12
VIN13
VIN14

VIN4
VIN15
VIN16

Bias

Digital encoder
Digital encoder
VCR
AUX
Digital encoder
TV
Analogue satellite
Video mute

Note) After power on all TV outputs are off and muted.

Switch 2 (VCR Output) Data 3 Bits 3, 4, 5

Note) After power on VCR outputs are off and muted.

VCR Chroma Mute Data 3 Bit 7

0 x x x x x x x = Vout5 active. Connected to input specified in above table.
1 x x x x x x x = Vout5 muted (the output dc bias still remains).

– 27 –

CXA2125Q

Switch 3 (AUX Output) Data 4 Bits 3, 4, 5

Vout7

(CVBS)

Switch setting Comment

VIN11

Bias
VIN13
VIN14

VIN4
VIN15
VIN16

Bias

0 x x 0 0 0 x x x
1 x x 0 0 1 x x x
2 x x 0 1 0 x x x
3 x x 0 1 1 x x x
4 x x 1 0 0 x x x
5 x x 1 0 1 x x x
6 x x 1 1 0 x x x
7 x x 1 1 1 x x x

Digital encoder
Video mute
VCR
AUX
Digital encoder
TV
Analogue satellite
Video mute

Note) After power up the AUX video outputs are off and muted.

Standby Mode Control Data 6 Bits 0, 1, 2, 3, 4, 5, 6

Each video output can be individually turned off using data byte 6.

0 = Video output off
1 = Video output on

Note) When switched off, the video outputs are high impedance to prevent d.c. driving of the external emitter

follower stage.
The reduction of overall current consumption will depend on how many video outputs are turned off.
After power on all video outputs are in the off state.

– 28 –

CXA2125Q

4. Fast Blanking Operation (Pin 16 on SCART), FBLK

The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB
information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a
CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and
is defined as follows,

Fast blanking output at scart,

1. CVBS mode Scart pin voltage = 0 to 0.4V

2. RGB mode Scart pin voltage = 1 to 3.0V

Threshold voltage is approximately 0.75V at the scart input.

Fast Blanking I2C Control

In the CXA2125Q, there are three fast blanking inputs, one associated with the Digital Encoder input
(FBLANK_IN1), one with the VCR RGB/CVBS input (FBLANK_IN2), and another associated with the AUX
RGB/CVBS input (FBLANK_IN3). These can be selected by I2C. In addition to the two blanking inputs, the fast
blank pin output can be set to a constant 0V or 5V by means of the I2C control. Hence there are four possible
states. These are controlled according to the following table.

FBLK Control Data 5 Bits 3, 4, 5

Note) After power on the output is 0V.

Fast Blank output circuit

The output requires an external buffer stage to drive the required 75Ω scart termination.
The levels at the IC output are 0V and +5V.

Fast Blank OutputI2C Setting

0V
+5V
Same level as Fast Blank in 1 (0/+5V)
Same level as Fast Blank in 2 (0/+5V)
Same level as Fast Blank in 3 (0/+5V)
+5V
+5V
+5V

0 x x 0 0 0 x x x
1 x x 0 0 1 x x x
2 x x 0 1 0 x x x
3 x x 0 1 1 x x x
4 x x 1 0 0 x x x
5 x x 1 0 1 x x x
6 x x 1 1 0 x x x
7 x x 1 1 1 x x x

1kΩ

75Ω

75Ω

Scart line 16

V

CC

TV

Fast Blank

0V/5V

CXA2125Q

Fig. 4-1. Fast Blanking Interface to TV SCART

– 29 –

CXA2125Q

5. Function Switch, FNC.

The function switch facility is designed to read the status of the SCART function pin 8 from the VCR input. The
read register holds the status of the input function lines.
The function output is controlled by I2C and is used to change the voltage on the function line to the TV. The
output can be connected directly to the scart pin. (Fig. 5-1)

Read Mode

Reads the status of the inputs FNC_VCR and FNC_AUX.

0
0
1

b1/b3

0
1
1

b0/b2

0 to +2V (default)

+4.5 to +7V

+9.5 to +12V

FNC_VCR/FNC_AUX

(Internal TV)

(16:9 External)

(4:3 External)

Level (SCART Defn.)

Read Data8

Input Pin Voltage

Write Mode

Controls the voltage at the TV function line (pin 8)

Mode/(Typical pin Voltage)I2C Control (Data 5)

Internal TV/(1V)
External scart input 16:9 mode/(6V)
External scart input 4:3 mode/(11V)
External scart input 4:3 mode/(11V)

0 x x x x x 0 0 x
1 x x x x x 0 1 x
2 x x x x x 1 0 x
3 x x x x x 1 1 x

Note) After power on output is internal TV mode ie. 0V at the pin.

10kΩ

Scart Pin 8

< 2V

> 4.5V < 7V

> 10V

FNC_TV

CXA2125Q

Fig. 5-1. TV Function Switch Output

– 30 –

CXA2125Q

6. Logic Output

A single logical output pin is provided. This is controlled via the I2C and is an open collector output.

Specification

I2C bit 0 = open collector/high output impedance
I2C bit 1 = Vsat (to 0.2V)
Vmax at logic pin = 12V
Imax during current sink = 1mA

Logic

cct.

I2C

LOGIC

Open collector logic
outputs

Fig. 6-1. Logic Output Interface

– 31 –

CXA2125Q

7. I2C Audio Signal Control

Outputs TV, VCR, AUX Data 2, 3, 4 Bits 0, 1, 2

Rin1
Rin2
Rin3
Rin4

Rin5
Audio mute
Audio mute
Audio mute

Lin1
Lin2
Lin3
Lin4

Lin5
Audio mute
Audio mute
Audio mute

RTV, ROUT1, ROUT2

LTV, LOUT1, LOUT2

0dB
–1dB
–1dB
–3dB
–4dB
–5dB
–6dB
–7dB

Volume Control Fine Data 1 Bits 2, 3, 4

Volume Control Coarse Data 1 Bits 5, 6, 7

Switch Setting

0 x x x x x 0 0 0
1 x x x x x 0 0 1
2 x x x x x 0 1 0
3 x x x x x 0 1 1
4 x x x x x 1 0 0
5 x x x x x 1 0 1
6 x x x x x 1 1 0
7 x x x x x 1 1 1

Note) After power on the audio outputs are muted.

Setting

Volume Fine Control Gain

0 x x x 0 0 0 x x
1 x x x 0 0 1 x x
2 x x x 0 1 0 x x
3 x x x 0 1 1 x x
4 x x x 1 0 0 x x
5 x x x 1 0 1 x x
6 x x x 1 1 0 x x
7 x x x 1 1 1 x x

0dB
–8dB

–16dB
–24dB
–32dB
–40dB
–48dB
–56dB

Setting

Gain

0 0 0 0 x x x x x
1 0 0 1 x x x x x
2 0 1 0 x x x x x
3 0 1 1 x x x x x
4 1 0 0 x x x x x
5 1 0 1 x x x x x
6 1 1 0 x x x x x
7 1 1 1 x x x x x

– 32 –

CXA2125Q

TV output amplifier Data 7 Bit 6

x 0 x x x x x x = 0dB
x 1 x x x x x x = +6dB

Note) After power on the gain is set to 0dB.

TV Mono Switch Data 7 Bit 3

x x x x 0 x x x = Normal stereo output
x x x x 1 x x x = Mono signal switched onto R + L line.

VCR Mono Switch Data 7 Bit 4

x x x 0 x x x x = Normal stereo output
x x x 1 x x x x = Mono signal switched onto R + L line.

AUX Mono Switch Data 7 Bit 5

x x x 0 x x x x = Normal stereo output
x x x 1 x x x x = Mono signal switched onto R + L line.

Mute and Zero Cross Operation

For TV, Phono and mono outputs.

There are two mute control bits in the bus map to allow the TV outputs to be muted before the channel change
instruction occurs. The normal structure for a click free audio channel change is as follows:

Data 1 Mute the TV audio output with the ZCD switched on.
Data 2 Change the TV audio source.
Data 7 Un-mute the TV audio output again with the ZCD switched on.

Note) After power on TV Mute and ZCD are set to 0.

TV Aud Mute Data 1 Bit 1

Data 7 Bit 7

ZCD Data 1 Bit 0 RTV, LTV, Phono_R, Phono_L, Mono outputs

0
0
1
1

0
1
0
1

Un-mute immediately
Un-mute on next zero cross
Mute immediately
Mute on next zero cross

– 33 –

CXA2125Q

Notes on operation

1) Supply de-coupling capacitors, 10nF and 4.7µF in parallel should be inserted as close to the supply pins,
20, 38, 60 as possible.

2) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB
track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the
video.

3) Attention should be given to the electrolytic capacitors on the input and output signal pins. As the pin's
voltage is between 3.7V and 4.7V dc the positive terminal on the capacitor should be orientated towards the
pin.

4) The audio outputs may be muted at any time after power up by connecting the HW_MUTE pin (45) to a
voltage > 2.5V and < 9V.

5) When driving video loads with impedance = 75Ω an emitter follower or video line driver is required to be
connected at the video outputs as shown in the application schematic.
Stray capacitance on pins Vout1-8 must be kept to a minimum by placing loads as close to the pins as
possible.

6) The supply voltage on pin 58 "VCC_12V" should not exceed +12V. If the supply has poor regulation then a
series diode or zener diode may be used to limit the voltage at this pin.

– 34 –

CXA2125Q

Inputs RIN1, LIN1 selected

Input [Vrms]

0

1

0.1

0.01

0.001

0.5 1 1.5

THD [%]

Audio frequency characteristics

Frequency [Hz]

Input = 0.3Vp-p

100

4

0

2

–4

–2

–6

1k 10k 100k 1M 10M

Audio Output/Input gain [dB]

Inputs RIN2, 3, 4, 5/LIN2, 3, 4, 5 selected

Input [Vrms]

0

0.1

0.01

0.001

0.0001
1 2 3 3.3

THD [%]

Video frequency characteristics

Frequency [Hz]

100k

4

6

8

0

2

1M

10M

50M

Video Output/Input gain [dB]

Typical audio output distortion

– 35 –

CXA2125Q

Package Outline Unit: mm

SONY CODE
EIAJ CODE
JEDEC CODE

23.9 ±0.4

20.0 –0.1

0.4 – 0.1

+ 0.15

14.0 – 0.1

1

19

20

32

33

51

52

64

0.15 – 0.05

+ 0.1

2.75 – 0.15

16.3

0.1 – 0.05

+ 0.2

0.8 ± 0.2

M

0.2

0.15

+ 0.4

17.9 ±0.4

+ 0.4

+ 0.35

64PIN QFP(PLASTIC)

QFP-64P-L01

QFP064-P-1420

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN
SOLDER/PALLADIUM

42/COPPER ALLOY

PACKAGE STRUCTURE

PLATING

1.5g

1.0

0° to10°