Datasheet CXA2095S Datasheet (Sony)

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Page 1

– 1 –

CXA2095S

E96X20-PS

Y/C/RGB/Sync/Deflection for Color TV

Description

The CXA2095S is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for NTSC system color TVs onto a single chip.

The following functions have been added to the same function IC, CXA2025S.

1) Vertical sync pull-in speed switching function

2) YUV SW Y signal switching function

3) fsc output pin

Features

• I2C bus compatible

• Sync signal processing uses a countdown system

with non-adjusting H/V oscillator frequencies

• Built-in deflection compensation circuit capable of

supporting various wide modes

• Non-adjusting Y/C block filter

• Built-in AKB

• Video signal I/Os: Y/C separation input, Y/color

difference input, analog RGB input and RGB

output

• YUV SW Y signal switching function allows picture

quality adjustment for the Y signal in the same

manner as for the normal Y signal even when

Y/color difference input is selected

Applications

Color TVs (4:3, 16:9)

Structure

Bipolar silicon monolithic IC

Pin Configuration

Absolute Maximum Ratings

(Ta = 25°C, SGND, JGND = 0V)

• Supply voltage SVCC, JVCC –0.3 to +12 V

• Operating temperature

Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation PD 1.5 W

• Voltages at each pin –0.3 to SVCC, JVCC + 0.3 V

Operating Conditions

Supply voltage SVCC 9.0 ± 0.5 V

JVCC 9.0 ± 0.5 V

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

48 pin SDIP (Plastic)

2728

BLHOLD

YIN

XTAL

APCFIL

CIN

YUV SW

EYIN

ERYIN

EBYIN

SGND

RIN

GIN

BIN

RSH

ROUT

GSH

GOUT

BSH

BOUT

SCL

SDA

IKIN

ABLIN/VCOMP

ABLFIL

FSCOUT

HSIN

VSIN

VSFIL

IREF

JGND

BGP

CERA

AFCFIL

L2FIL

AFCPIN/HOFF

HDRIVE

SAWOSC

VAGCSH

EWDRIVE

VDRIVE+/VPROT

VDRIVE–/VPROT

VTIM (SCP)

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CXA2095S

C BUS

DECODER

D/A

IREF

VSYNC

SEP.

HSYNC

SEP.

PHASE

DETECTOR

32f

H VCO

H PHASE

DETECTOR

H DRIVE

H PHASE

SHIFTER

V SAW

OSC/AGC

V PARA

GEN.

V SAW

GEN.

WIDE

MODE

V ZOOMING

ABL

AXIS

Y/C MIX PICTURE

D-COL

GAMMA

CLAMP BRIGHT

DRIVE

AKB/CUTOFF/IK

BLANKING BUFFER

RGB CLAMP

YS SW

REF-P SW

YM ATT.

YUV SW

YUV

CLAMP

AMP

CHROMA

VCO

CHROMA

DEMOD.

KILLER

DETECTOR

COLOR

HUE

CHROMA

APC

TOT

ACC AMP

VM AMP

SUBCONT

C-TRAP

Y DELAY SHARPNESS

CLAMP

DC-TRAN

D-PIC

TIMING PULSE GEN.

V COUNT DOWN

1/32

DIVIDER

26 27

29 30

41 42

SDA

SCL

BGP

IREF

VSIN

VSFIL

HSIN

AFCFIL

JGND

CERA

L2FIL

AFCPIN

/HOFF

HDRIVE

SAWOSC

VAGCSH

EWDRIVE

VDRIVE+

VDRIVE–

/VPROT

VTIM

ABLIN

/VCOMP

ABLFIL

IKIN

YIN

BLHOLD

CIN

APCFIL

XTAL

YUVSW

EYIN

ERYIN

EBYIN

SGND

RIN

GIN

BIN

RSH

GSH

BSH

BOUT

GOUT

ROUT

FSCOUT

Block Diagram

Page 3

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CXA2095S

Pin Description

Pin No.

Symbol Equivalent circuit Description

XTAL

Connect a 3.579545MHz crystal oscillator.

APCFIL

CR connection for the chroma APC lag-lead filter.

BLHOLD

Capacitor connection for black peak hold of the dynamic picture (black expansion).

YIN

Y signal input. Input a 2Vp-p (including sync, 100% white) Y signal via a capacitor. The pedestal level of the input signal is clamped to 4.2V.

7 SCL

I2C bus protocol SCL (Serial Clock) input.

VILMAX = 1.5V VIHMIN = 3.5V

350

200µ

1.2k

50µ

1.2k

SVCC

20k

9µ

25µ

SVCC

1.2k

100µ

SVCC

30k

10p

35µ

JVCC

10k

50µ

CIN

Chroma signal input. Provide a bias of about VCC/2 and input a C signal (including sync, 100% white, 2Vp-p CV signal) with a 570mVp-p burst level.

Power supply for the video block.

SVCC

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CXA2095S

8 SDA

I2C bus protocol SDA (Serial Data) I/O.

VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0.4V

YUV SW

Switch control for the external YUV signal input. When YUV SW is high, the external YUV signal is selected; when YUV SW is low, the Y/C block signal is selected. However, when the EY-SW register is 1, the YIN (Pin 4) input is selected for the Y signal even if YUV SW is high.

VILMAX = 0.4V VIHMIN = 1.0V VIHMAX = 3.0V

EYIN

External Y signal input. Input a 0.7Vp-p (100 IRE) Y signal via a capacitor. The signal is clamped to 6.5V at the burst timing of the signal input to the sync input (Pin 44).

ERYIN

External R-Y signal input. Input a 0.78Vp-p (color difference signal obtained by detecting a 100 IRE, 0.7Vp-p, 100% color bar chroma signal at the orthogonal axis) + (R-Y) signal via a capacitor. The signal is clamped to 6.2V at the burst timing of the signal input to the sync input (Pin 44).

YM switch control input. When YM is high, the Y/C block signal is attenuated by 6dB.

VILMAX = 0.4V VIHMIN = 1.0V VIHMAX = 3.0V

JVCC

50µ

SVCC

147

40k

100µ

11 12

SVCC

40k

SVCC

147

40k

100µ

EBYIN

External B-Y signal input. Input a 1.0Vp-p (color difference signal obtained by detecting a 100 IRE, 0.7Vp-p, 100% color bar chroma signal at the orthogonal axis) + (BY) signal via a capacitor. The signal is clamped to 6.2V at the burst timing of the signal input to the sync input (Pin 44).

GND for the video block.

SGND

Pin No.

Symbol Equivalent circuit Description

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CXA2095S

YS switch control input. When YS is high, the RGB block signal is selected; when YS is low, the Y/C block is selected.

VILMAX = 0.4V VIHMIN = 1.0V VIHMAX = 3.0V

16 17 18

RIN GIN BIN

Analog R, G and B signal input. Input a 0.7Vp-p (no sync, 100 IRE) signal via a capacitor. The signal is clamped to 5.1V at the burst timing of the signal input to the sync input (Pin 44).

19 21 23

RSH GSH BSH

Sample-and-hold for R, G and B AKB. Connect to GND via a capacitor. When not using AKB (manual cut-off mode), R, G and B cut-off voltage can be controlled by applying a control voltage to each pin. The control voltage is 4.2 ± 2V.

20 22 24

ROUT GOUT BOUT

R, G and B signal output.

2.4Vp-p is output during 100% white input.

ABLIN /VCOMP

ABL control signal input and VSAW high voltage fluctuation compensation signal input. High voltage compensation has linear control characteristics for the pin voltage range of about 8V to 1V. ABL operates when the pin voltage becomes lower than about 1.2V.

SVCC

147

40k

100µ

SVCC

30k

200

21 23

SVCC

50µ

12k

200

SVCC

1100µ

SVCC

50µ

SVCC

147

IKIN

Input the signal converted from the CRT beam current (cathode current IK) to a voltage via a capacitor. The V blanking part is clamped to 2.7V at the V retrace timing. The input for this pin is the reference pulse return, and the loop operates so that the Rch, the Gch and Bch are all 1Vp-p. (∗For the CXA2025S, the loop

operates so that the Rch is 1Vp-p and the Gch and Bch are 0.83Vp-p.) The Gch and Bch can be varied by ±0.5V by the bus CUTOFF control. When not using AKB, this pin should not be connected.

Pin No.

Symbol Equivalent circuit Description

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CXA2095S

ABLFIL

Connect a capacitor to form the LPF of the ABL control signal.

VTIM (SCP)

V timing pulse output. Outputs the timing pulse from V sync identification to the end of V blanking. Pulses are positive polarity from 0 to 6 [V]. During zoom mode, the V blanking pulse which has been expanded before and after the V sync is superimposed and output as the 0 to 3 [V] pulse.

VDRIVE– /VPROT

V sawtooth wave output and Vprotect signal input. When a large current (3mA) is led from this pin, the RGB outputs are all blanked and the status is returned to the I2C bus.

VDRIVE+ /VPROT

Outputs a V sawtooth wave of the opposite polarity as VDRIVE–. The Vprotect function can also be operated by this pin.

VAGCSH

Sample-and-hold for AGC which maintains the V sawtooth wave at a constant amplitude. Connect to GND via a capacitor.

SVCC

10k

1.2k

JVCC

10k

JVCC

30k

24k

720

400µ

JVCC

30k

24k

720

400µ

JVCC

15k

78k

1.4k

25µ

800µ

JVCC

1.2k

EWDRIVE

V parabola wave output.

Pin No.

Symbol Equivalent circuit Description

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CXA2095S

SAWOSC

Connect a capacitor to generate the V sawtooth wave.

HDRIVE

H drive signal output. This signal is output with the open collector. This pin goes high (OFF) during hold-down.

∗

For the CXA2025S, this pin is low (ON) during hold-down.

AFCPIN /HOFF

H deflection pulse input for H AFC. Input an about 5Vp-p pulse via a capacitor. Set the pulse width to 10 to 12µs. This pin is also used as the hold-down signal input for the HD output, and if this pin is 1 [V] or less for a 7V cycle or longer, the hold-down function operates and the HD output goes to high (OFF). In addition, the RGB outputs are all blanked and the status is returned to the I2C bus.

L2FIL

Filter for H AFC. Connect to GND via a capacitor. The H phase can also be controlled from this pin by leading current in and out of this capacitor. As the pin voltage rises, the picture shifts to the left; as the pin voltage drops, the picture shifts to the right.

CERA

Connect the ×32fH VCO ceramic oscillator.

JVCC

100

100µ

JVCC

147

20k

JVCC

147

10k

60k

50µ 50µ

4.2V

JVCC

100

25µ

JVCC

1.2k

46k

50µ

10k

JVCC

400µ

50µ

AFCFIL

CR connection for the AFC lag-lead filter.

JGND

GND for the deflection block.

JVCC

Power supply for the deflection block.

Pin No.

Symbol Equivalent circuit Description

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CXA2095S

IREF

Internal reference current setting. Connect to GND via a 15kΩ resistor.

VSFIL

Filter for V sync separation. Connect to GND via a capacitor.

VSIN

Sync signal input for V sync separation. Input a 2Vp-p Y signal.

HSIN

Sync signal input for H sync separation. Input a 2Vp-p Y signal.

BGP

Burst gate pulse output. This pulse is a 0 to 3V positive polarity pulse. While this pulse is gated near V-Sync for the CXA2025S, it is constantly output for the CXA2095S.

20k

JVCC

147

JVCC

147

20µ

JVCC

147

10µ

SVCC

400µ

15k

Y signal differential waveform output for VM (Velocity Modulation). (7.1VDC, 2.0Vp-p) The signal delayed for 250ns from YIN is output. The delay time from YIN and the differential coefficient of the output signal vary according to sharpness f0 control.

Pin No.

Symbol Equivalent circuit Description

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CXA2095S

FSCOUT

Sub carrier output.

Output level: 5.9VDC, 0.5Vp-p

This pin is not connected. Connect to GND normally to prevent interference to others.

SVCC

300µ

147

Pin No.

Symbol Equivalent circuit Description

Page 10

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CXA2095S

Electrical Characteristics

Setting conditions

• Ta = 25°C, SVCC = JVCC = 9V, SGND = JGND = 0V

• Measures the following after setting the I

C bus register as shown in “I

C bus register initial settings”.

No.

Item Symbol Measurement conditions

Measure-

ment pin

Measurement contents

Min. Typ. Max. Unit

No.

Item Symbol Measurement conditions

Measure-

ment pin

Measurement contents

Min. Typ. Max. Unit

Signal block current

consumption

SVCC = 9.0V,

Bus data = center

Measure the pin inflow current.

65 90

Sync block current

consumption

JVCC = 9.0V,

Bus data = center

Measure the pin inflow current.

Horizontal free-running

frequency

fHFR

AFC MODE = 0H

HDRIVE output frequency

Confirm that I

C status register HLOCK is 1

(the pull-in range when f

H is shifted from 15.734kHz).

Measure the pulse width for the section where the

HDRIVE output is high.

Measure the pulse width for the section where the BGP

output is high.

Measure the VDRIVE output Vp-p.

15.55

15.734

15.9

kHz

Horizontal sync pull-in

range

∆

SYNC IN: composite sync

—

–400

—

400

5 HD output pulse width

HDw

SYNC IN: composite sync

24.5

25.5

26.5

µs

6 BGP output pulse width

VBGPh

3.1 4.0

4.9

µs

VDRIVE output

amplitude

VSpp

SYNC IN: composite sync

29,

0.8

0.95 1.1

VDRIVE output center

potential

VSdc

29,

2.9

3.0

3.15

Sync deflection block items

VSpp

43: VSIN in

VSdc

8.97ms

VDRIVE+

Page 11

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CXA2095S

EWDRIVE output

amplitude

VEWpp

SYNC IN: composite sync

Measure the EWDRIVE output Vp-p.

0.5

0.65

0.8

EWDRIVE output center

potential

VEWdc

3.7

4.0

4.2

VEWpp

43: VSIN in

8.97ms

R, G and B output

amplitude

VRout1

20,

22,

Output amplitude when a video signal with an amplitude

of 1.4Vp-p/100 IRE is input

2.1

2.4

2.7

Signal block items

R, G and B output

linearity

Lin

20,

22,

100

105

13 C-TRAP attenuation

C-Trap

C-TRAP = 0/1

CTRAP-ADJ = 7H

—

–37.5

—

1.4Vp-p/100 IRE

YIN:

100 IRE

50 IRE

YIN:

fsc, 50 IRE

Lin = × 100

V2 × 2

f = 3.58MHz

No.

Item Symbol Measurement conditions

Measure-

ment pin

Measurement contents Min. Typ. Max. Unit

No.

Item Symbol Measurement conditions

Measure-

ment pin

Measurement contents

Min. Typ. Max. Unit

Input fsc to YIN.

Ratio of the fsc component of the Rout amplitude when

CTRAP=1 against the Rout amplitude when CTRAP=0.

Page 12

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CXA2095S

VM output

Color gain

Hue center offset

Killer point

APC pull-in range

Dynamic color operation

R output

Dynamic color operation

B output

YM gain

Vvm

Vcol

φoffset

∆f

APC

∆GdcolR

∆GdcolB

∆GYM

—

20,

22,

Confirm that status register KILLER is 1 when the burst

level is –31dB assuming burst 570mVp-p to be 0dB.

Confirm that the burst frequency is pulled in at 3.58MHz

±400Hz.

∆GdcolR = × 100

∆GdcolB = × 100

Output amplitude ratio of the R, G and BOUT when YM

is high and low

Vpp (DCOL = 1)

Vpp (DCOL = 0)

ROUT, BOUT

1.5

2.2

2.4

0.75

0.98

1.2

–8.5 0 8.5 deg

— –31 — dB

–400 — 400 Hz

YIN: 100 IRE

D-COL = 0/1

SUBCONT = F

50 IRE

f = 3MHz

Vvm

YIN

CIN

180° 0°

500mVpp

Vpp

BOUT

Vpp

YIN: 3MHz, 50 IRE

VM = 1

YIN: GND

CIN: burst

+180°, 500mVp-p

COLOR = 1F

HUE = 1F, SUB-HUE = 7

YIN = GND

CIN: burst only

104

106

108

–7.1

–6.1

–5.1

Vpp (DCOL = 1)

Vpp (DCOL = 0)

No.

Item Symbol Measurement conditions

Measure-

ment pin

Measurement contents Min. Typ. Max. Unit

Page 13

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CXA2095S

R output amplitude during

external Y input

VRout2

2.05

2.4

2.75

YUVSW: 2V

EYIN: 0.7V

VRout2 = Vout

R output amplitude during

external R-Y input

VRout3

1.25

1.7

2.15

YUVSW: 2V

ERYIN: 0.4V

VRout3 = Vout

B output amplitude during

external B-Y input

VBout1

1.34

1.64

1.94

YUVSW: 2V

EBYIN: 0.4V

VBout1 = Vout

R output amplitude during

linear R input

VLRout

1.9

2.23

2.55

YS: 1V

RGBIN: 0.7V

VRout = Vout

G output amplitude during

linear G input

VLGout

1.9

2.23

2.55

YS: 1V

RGBIN: 0.7V

VGout = Vout

B output amplitude during

linear B input

VLBout

1.9

2.23

2.55

YS: 1V

RGBIN: 0.7V

28 IK level R

VIKR

0.8

0.98

1.16

SYNC IN: composite sync

GCUTOFF = 0

BCUTOFF = 0

29 IK level G

VIKG

0.42

0.60

0.78

30 IK level B

VIKB

0.42

0.60

0.78

VBout = Vout

EYIN

ERYIN

EBYIN

RGBIN

R, G, B out

Vin

Vout

VIKR VIKGVIKG

IKIN

No.

Item Symbol Measurement conditions

Measure-

ment pin

Measurement contents Min. Typ. Max. Unit

Page 14

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CXA2095S

Electrical Characteristics Measurement Conditions “I2C bus register initial settings”

PICTURE = 3F Hex C-TRAP = 0 VM = 0 HUE = 1F Hex DC-TRAN = 0 D-PIC = 0 COLOR = 1F Hex TOT = 0 AXIS = 0 BRIGHT = 1F Hex D-COL = 0 ABL = 0 SHARPNESS = 7 Hex PRE-OVER = 3 SHP-F0 = 2 SUB-CONT = 7 Hex CTRAP-ADJ = 7 Hex SUB-COLOR = 7 Hex SUB-HUE = 7 Hex SUB-BRIGHT = 1F Hex GAMMA = 0 G-DRIVE = 2A Hex AGING1 = 0 AGING2 = 0 B-DRIVE = 2A Hex G-CUTOFF = 0 Hex B-CUTOFF = 0 Hex EY-SW = 0 CD-MODE2 = 0 RON = 1 GON = 1 BON = 1 PICON = 1 VOFF = 0 FHHI = 0 CD-MODE = 0 AKBOFF = 0 V-SIZE = 1F Hex V-COMP = 0 V-POSITION = 1F Hex AFC-MODE = 1 S-CORR = 0 Hex V-LIN = 7 Hex H-SIZE = 1F Hex REF-POSI = 3 PIN-COMP = 1F Hex VBLKW = 0 H-POSITION = 7 Hex PIN-PHASE = 7 Hex UP-CPIN = 0 Hex LO-CPIN = 0 Hex AFC-BOW = 7 Hex AFC-ANGLE = 7 Hex V-ASPECT = 0 Hex ZOOMSW = 0 HBLKSW = 0 V-SCROLL = 1F Hex JMPSW = 0 UP-VLIN = 0 Hex LO-VLIN = 0 Hex LEFT-BLK = 7 Hex RIGHT-BLK = 7 Hex

Page 15

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CXA2095S

Application Circuit

C bus

input/output

2728

BLHOLD

YIN

XTAL

APCFIL

CIN

YUV SW

EYIN

ERYIN

EBYIN

SGND

RIN

GIN

BIN

RSH

ROUT

GSH

GOUT

BSH

BOUT

SCL

SDA

IKIN

ABLIN/VCOMP

ABLFIL

FSCOUT

HSIN

VSIN

VSFIL

IREF

JGND

BGP

CERA

AFCFIL

L2FIL

AFCPIN/HOFF

HDRIVE

SAWOSC

VAGCSH

EWDRIVE

VDRIVE–

/VPROT

VTIM

10k

10µ

100

100100100

0.1µ

0.1µ 47µ

0.01µ

2.7k

0.1µ

10k

0.0027µ

0.01µ

1µ

8.2k

390

503k

15k

330k

0.47µ

100

1µ

220

0.0047µ

3.5k

100p

100

0.1µ

100

0.1µ

100

0.1µ

0.01µ

220

0.01µ

220

0.1µ0.1µ0.1µ220220220

47µ

0.01µ

0.47µ

4.7µ

0.47µ

15k

470p

15p

3.579545

MHz

1.5k

0.47µ

PINP Y/color difference

signal input

YM/YS

signal input

Analog

RGB input

RGB output

C signal input

Y signal input

V sawtooth

wave output

+9V

BGP

output

Signal output

for VM

Hold-down input

HP input

HD output

V parabola

wave output

V protect signal input

V timing pulse output

ABL/High voltage fluctuation

compensation signal input

IK input

VDRIVE+

/VPROT

fsc

output

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

Page 16

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CXA2095S

Electrical Characteristics Measurement Circuit

Signal sources are all GND unless otherwise specified in the Measurement conditions column of Electrical Characteristics. ABL is 9V unless otherwise specified.

2728

BLHOLD

YIN

XTAL

APCFIL

CIN

YUV SW

EYIN

ERYIN

EBYIN

SGND

RIN

GIN

BIN

RSH

ROUT

GSH

GOUT

BSH

BOUT

SCL

SDA

IKIN

ABLIN/VCOMP

ABLFIL

FSCOUT

HSIN

VSIN

VSFIL

IREF

JGND

BGP

CERA

AFCFIL

L2FIL

AFCPIN/HOFF

HDRIVE

SAWOSC

VAGCSH

EWDRIVE

VTIM

4538

2T1

2T2

2CD

1CD

1T1

1T2

47µ

2000p

10k

5.1k

10k

2000p

HDRIVE

AFCPIN

width 10µs

delay 12µs

HOFF

HDRIVE

E/W

VDRIVE+

VDRIVE– VTIM

VPROT

10k

ABL

10µ

0.001µ

100

100100100

0.1µ

0.1µ 47µ

0.01µ

2.7k

0.1µ

10k

0.1µ

0.01µ

1µ

8.2k

390

503kHz

15k

330k

0.47µ

100

1µ

220

0.0047µ

VMBGP

10k

330p

1µ

100

51k

20k

10k

D1 D2 D3

100

0.1µ

100

0.1µ

100

0.1µ

0.01µ RGBIN

220

0.01µ

220

YSYM

EBYIN

0.1µ0.1µ0.1µ220220220

CBUS

47µ

0.01µ

0.47µ

4.7µ

0.47µ

15k

470p

15p

3.579545

MHz

1.5k

ERYIN

EYIN

CINYINSYNCIN

ROUT GOUT BOUT IKIN

YUVSW

CXA2095S

VDRIVE–

/VPROT

VDRIVE+

/VPROT

FSCOUT

Page 17

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CXA2095S

CTRAP-ADJ

SUB-HUE

B-CUTOFF

V-LIN

PIN-PHASE

LO-CPIN

AFC-ANGLE

LO-VLIN

RIGHT-BLK

PICTURE

HUE

COLOR

BRIGHT

SUB-BRIGHT

G-DRIVE B-DRIVE

V-SIZE

V-POSITION

H-SIZE

PIN-COMP

V-ASPECT V-SCROLL

SHARPNESS

SUB-CONT

SUB-COLOR

G-CUTOFF

S-CORR

H-POSITION

UP-CPIN

AFC-BOW

UP-VLIN

LEFT-BLK

Definition of I2C Bus Registers

Slave Addresses

88H: Slave receiver 89H: Slave transmitter

Control Register

BIT0BIT1BIT2BIT3BIT4BIT5BIT6BIT7

Sub Address

∗ ∗ ∗ 0 0 0 0 0 00 H ∗ ∗ ∗0 0 0 0 1 01 H ∗ ∗ ∗0 0 0 1 0 02 H ∗ ∗ ∗0 0 0 1 1 03 H ∗ ∗ ∗0 0 1 0 0 04 H ∗ ∗ ∗0 0 1 0 1 05 H ∗ ∗ ∗0 0 1 1 0 06 H ∗ ∗ ∗0 0 1 1 1 07 H ∗ ∗ ∗0 1 0 0 0 08 H ∗ ∗ ∗0 1 0 0 1 09 H ∗ ∗ ∗0 1 0 1 0 0A H ∗ ∗ ∗0 1 0 1 1 0B H ∗ ∗ ∗0 1 1 0 0 0C H ∗ ∗ ∗0 1 1 0 1 0D H ∗ ∗ ∗0 1 1 1 0 0E H ∗ ∗ ∗0 1 1 1 1 0F H ∗ ∗ ∗1 0 0 0 0 10 H ∗ ∗ ∗1 0 0 0 1 11 H ∗ ∗ ∗1 0 0 1 0 12 H ∗ ∗ ∗1 0 0 1 1 13 H ∗ ∗ ∗1 0 1 0 0 14 H ∗ ∗ ∗1 0 1 0 1 15 H ∗ ∗ ∗1 0 1 1 0 16 H ∗ ∗ ∗1 0 1 1 1 17 H

C-TRAP

DC-TRAN

TOT

D-COL

D-PIC

AXIS

ABL

PRE-OVER

SHP-F0

GAMMA

AGING1

EY-SW

AGING2

CD-MODE2

AKBOFF

CD-MODE

FHHIVOFFPICONBONGONRON

V-COMP

AFC-MODE

REF-POSI

VBLKW

ZOOMSW

JMPSW

HBLKSW

Status Register

BIT0

BIT1

BIT2

BIT3

KILLER

BIT4

HNG

BIT5 VNG

BIT6

IKR

BIT7

HLOCK

Note) EY-SW and CD-MODE2 have been added to the CXA2025S.

∗: Don't care

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CXA2095S

Description of Registers

PICTURE (6) : Picture gain control (RGB gain control)

0H = –15dB 3FH = 0dB RGB output: 2.4Vp-p (I/O gain: +4.7dB, 1.4Vp-p input)

C-TRAP (1) : Y block chroma trap ON/OFF switch

0 = Trap OFF 1 = Trap ON (Y signal delay time adjusted when C-TRAP turned ON or OFF.)

VM (1) : Y signal differential output ON/OFF switch for VM

0: Output OFF 1: Output ON (2.0Vp-p)

HUE (6) : Hue control (Chroma demodulation axis control when SUB-HUE is 8H)

0H = +35° Flesh color appears red. 1FH = 0° 3FH = –35° Flesh color appears green.

DC-TRAN (1) : Y DC transmission ratio selector switch

0 = 100% 1 = 82%

DPIC (1) : Y black expansion ON/OFF switch

0 = OFF 1 = ON Point of inflection: 30 IRE

COLOR (6) : Color gain control

0H = Color OFF (–40dB or less) 1FH = 0dB B output: 1.1Vp-p (I/O gain: +5.7dB, 0.57Vp-p input) 3FH = +5.4dB

TOT (1) : Chroma TOT filter band selector switch

0 = TOT-TRAP OFF 1 = TOT-TRAP ON (TRAP f0 2.0MHz)

AXIS (1) : R-Y, G-Y axis selector switch

0 = Japan axis R-Y: 95° × 0.60, G-Y: 236° × 0.33 1 = US axis R-Y: 105° × 0.78, G-Y: 236° × 0.33

(B-Y: 0° × 1)

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CXA2095S

BRIGHT (6) : Bright level control (RGB DC bias control)

0H = –300mV 1FH = 0mV –300mV from REF-P level 3FH = +300mV

D-COL (1) : Dynamic color ON/OFF switch

0 = Dynamic color OFF 1 = Dynamic color ON (R, Bch level control)

ABL (1) : ABL mode selector switch

0 = Picture ABL mode 1 = Picture/bright ABL mode

SHARPNESS (4) : Sharpness gain control (Y aperture correction gain control)

0H = –8dB 7H = 1dB FH = +5.1dB

PRE-OVER (2) : Sharpness preshoot/overshoot ratio control

0H = 1:1 (PRE:OVER) 3H = 5:1

SHP-F0 (2) : Sharpness f0 control (Delay line current control for aperture correction)

0H = 2.5MHz 3H = 4.0MHz

SUB-CONT (4) : Contrast gain control (Y gain control)

0H = –3.0dB 7H = 0dB FH = +2.5dB

CTRAP-ADJ (4) : Chroma trap f0 adjustment (Y block chroma trap current control)

0H = +300kHz 7H = 0kHz FH = –300kHz fsc adjustable to –30dB or less (SHP-F0 min.); adjustment value: 3 to 4

SUB-COLOR (4) : Color gain control (ACC reference level control)

0H = –4.0dB 7H = 0dB FH = +2.1dB

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CXA2095S

SUB-HUE (4) : Hue control (Phase control for chroma demodulation axis when HUE = 1FH)

0H = +10° 7H = 0 FH = –10°

B-Y axis adjustable to 0°

SUB-BRIGHT (6) : Bright level control (RGB DC bias control)

0H = –300mV 1FH = 0mV –300mV from REF-P level 3FH = +300mV

GAMMA (2) : Gamma control (RGB gamma correction amount control)

0H = Gamma OFF 3H = Gamma peak (40 IRE) +400mV

G-DRIVE (6) : Gch drive gain adjustment (Gch gain control)

0H = G/R –3.8dB 2AH = G/R 0dB 3FH = G/R +2.5dB

AGING1 (1) : White output aging mode ON/OFF switch

(Has priority over RGBON and PICON control, set to OFF mode at poweron.) 0 = Aging mode OFF 1 = Aging mode ON 60 IRE flat signal output from Y block when input is

no signal

AGING2 (1) : Black output aging mode ON/OFF switch

(Has priority over AGING1, set to OFF mode at power-on.) 0 = Aging mode OFF 1 = Aging mode ON Black level output

B-DRIVE (6) : Bch drive gain adjustment (Bch gain control)

0H = B/R –3.8dB 2AH = B/R 0dB 3FH = B/R +2.5dB

EY-SW (1) : Internal Y signal fixed mode ON/OFF switch

0 = YUV SW (Pin 9) standard operation (EYIN, ERYIN and EBYIN input are

selected when Pin 9 is high.)

1 = EYIN (Pin 10) input only invalid (Internal Y, ERYIN and EBYIN input are

selected when Pin 9 is high.)

CD-MODE2 (1) : Vertical sync pull-in speed switch

0 = Standard (equivalent to CXA2025S) 1 = High speed

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CXA2095S

G-CUTOFF (4) : Gch cut-off adjustment (Gch reference pulse value control of IKIN pin input)

0H = 62% 7H = 100% (G/R: Gch reference pulse amplitude when Rch reference FH = 150% pulse amplitude of IKIN pin input is assumed 100%)

B-CUTOFF (4) : Bch cut-off adjustment (Bch reference pulse value control of IKIN pin input)

0H = 62% 7H = 100% (B/R: Bch reference pulse amplitude when Rch reference FH = 150% pulse amplitude of IKIN pin input is assumed 100%)

RON (1) : ON/OFF switch for Rch video output without a reference pulse

(Operates when PICON = 1, set to OFF mode at power-on.) 0 = Rch video output OFF (Blanked status, reference pulse only output) 1 = Rch video output ON

GON (1) : ON/OFF switch for Gch video output without a reference pulse

(Operates when PICON = 1, set to OFF mode at power-on.) 0 = Gch video output OFF (Blanked status, reference pulse only output) 1 = Gch video output ON

BON (1) : ON/OFF switch for Bch video output without a reference pulse

(Operates when PICON = 1, set to OFF mode at power-on.) 0 = Bch video output OFF (Blanked status, reference pulse only output) 1 = Bch video output ON

PICON (1) : ON/OFF switch for RGB output with a reference pulse (Set to OFF mode at

power-on.) 0 = RGB output OFF (All blanked status) 1 = RGB output ON

VOFF (1) : V sawtooth wave oscillation stop ON/OFF switch (Set to OFF mode at

power-on.) 0 = Oscillation stop OFF (VDRIVE– and VDRIVE+: normal output) 1 = Oscillation stop ON (VDRIVE– and VDRIVE+: DC output and DC value

vary according to V-POSITION.)

FHHI (1) : H oscillator frequency fixation ON/OFF switch (Set to ON mode at power-on.)

0 = H oscillator frequency fixation OFF AFC normal mode 1 = H oscillator frequency fixation ON Oscillator frequency fixed to

maximum value (16.252kHz).

CD-MODE (1) : V countdown system mode selector switch

(Set to automatic selection mode during power-on.) 0 = Non-standard signal mode, standard signal mode and no signal mode

automatically selected

1 = Fixed to non-standard signal mode

(V oscillator frequency is 55Hz during no signal mode (free run).)

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CXA2095S

AKBOFF (1) : AKB ON/OFF switch (Set to ON mode at power-on.)

0 = AKB ON 1 = AKB OFF IK clamp, IK S/H and reference pulse fixed to OFF.

R, G and B cut-off adjustment at AKB OFF performed by voltage applied to Pins 19 (RSH), 21 (GSH) and 23 (BSH), respectively.

V-SIZE (6) : Vertical amplitude adjustment (V sawtooth wave gain control)

0H = –14% Vertical picture size decreases. 1FH = 0% Amplitude: 1.15Vp-p, center DC : 3V (when V-ASPECT = 1FH) 3FH = +14% Vertical picture size increases.

V-COMP (2) : Compensation amount setting for vertical high voltage fluctuation (V sawtooth

wave gain control) 0H = 0% V sawtooth wave amplitude compensation amount when 1V is

applied with respect to when 9V is applied of VCOMP (Pin 26)

3H = –5% V sawtooth wave amplitude compensation amount when 1V is

applied with respect to when 9V is applied of VCOMP (Pin 26)

V-POSITION (6) : Vertical position adjustment (V sawtooth wave DC bias control)

0H = –0.09V Picture position drops, VDRIVE+ output DC Down 1FH = 0V Center DC: 3V 2FH = +0.09V Picture position rises, VDRIVE+ output DC Up

AFC MODE (2) : AFC loop gain control (PLL between Hsync and Hvco)

0H = H free run mode 1H = Small gain 2H = Medium gain 3H = Large gain

S-CORR (4) : Vertical S correction amount adjustment (V sawtooth wave secondary component

gain control) 0H = Secondary component amplitude by adding sawtooth wave is 0 FH = Secondary component amplitude by adding sawtooth wave is Maximum

V-LIN (4) : Vertical linearity adjustment (Gain control for V sawtooth wave secondary

component) 0H = 85% (Bottom/top of picture) Top of picture expanded; bottom of picture

compressed. 7H = 100% (Bottom/top of picture) FH = 115% (Bottom/top of picture) Top of picture compressed; bottom of

picture expanded.

H-SIZE (6) : Horizontal amplitude adjustment (V parabola wave DC bias control)

0H = –0.5V Horizontal picture size decreases, EWDRIVE output DC Down. 1FH = 0V Amplitude: 0.58Vp-p, center DC: 4V (when V-ASPECT = 2FH) 3FH = +0.5V Horizontal picture size increases, EWDRIVE output DC Up

REF-POSI (2) : Reference pulse timing setting

0H = (From VTIM rise) Rch: 22H, Gch: 23H, Bch: 24H 1H = (From VTIM rise) Rch: 20H, Gch: 21H, Bch: 22H 2H = (From VTIM rise) Rch: 18H, Gch: 19H, Bch: 20H 3H = (From VTIM rise) Rch: 16H, Gch: 17H, Bch: 18H

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CXA2095S

PIN-COMP (6) : Horizontal pin distortion compensation amount adjustment (V parabola wave

gain control) 0H = 0.11Vp-p Compensation amount minimum 1FH = 0.47Vp-p Center DC: 4V (when V-ASPECT = 2FH) 3FH = 0.84Vp-p Compensation amount maximum

VBLKW (2) : VBLK width control (Blanked width after reference pulse. Operates when

JMPSW = 1, blanked width after reference pulse is fixed to 1H when JMPSW = 0.) 0H = 12H from Bch REF-P 1H = 11H from Bch REF-P 2H = 10H from Bch REF-P 3H = 9H from Bch REF-P

H-POSITION (4) : Horizontal position adjustment (HAFC phase control)

0H = 1µs delay Picture position shifts to right. Video delayed with

respect to HD. 7H = 0µs FH = 1µs advance Picture position shifts to left. Video advanced with

respect to HD.

PIN-PHASE (4) : Horizontal trapezoidal distortion compensation amount adjustment (V parabola

wave center timing control) 0H = 1.5ms advance Horizontal size for top of picture increases.

Horizontal size for bottom of picture decreases. 7H = 0ms Center timing is 8.9ms from VTIM. FH = 1.5ms delay Horizontal size for top of picture decreases.

Horizontal size for bottom of picture increases.

UP-CPIN (4) : Horizontal pin distortion compensation amount adjustment for top of picture (V

parabola wave gain control) 0H = +0.2V Horizontal size for top of picture decreases. 7H = 0V (0.7Vp-p, 4:3 mode) FH = –0.2V Horizontal size for top of picture increases.

LO-CPIN (4) : Horizontal pin distortion compensation amount adjustment for bottom of picture

(V parabola wave gain control) 0H = +0.2V Horizontal size for bottom of picture decreases. 7H = 0V (0.7Vp-p, 4:3 mode) FH = –0.2V Horizontal size for bottom of picture increases.

AFC-BOW (4) : Vertical line bow compensation amount adjustment (HAFC phase control

according to parabola wave) 0H = Top and bottom of picture delayed 500ns with respect to picture center 7H = 0ns FH = Top and bottom of picture advanced 500ns with respect to picture center

AFC-ANGLE (4) : Vertical line slope compensation amount adjustment (HAFC phase control

according to sawtooth wave) 0H = Top of picture delayed 500ns, bottom of picture advanced 500ns with

respect to picture center 7H = 0ns FH = Top of picture advanced 500ns, bottom of picture delayed 500ns with

respect to picture center

V-ASPECT (6) : Aspect ratio control

(V sawtooth wave gain control) 0H = 75% 16:9 CRT full 2FH = 100% 4:3 CRT full (amplitude: 1.23Vp-p) 3FH = 112%

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CXA2095S

ZOOMSW (1) : Zoom mode ON/OFF switch for 16:9 CRT

(Top and bottom of V sawtooth wave squeezed and 25% of picture cut) 0 = Zoom OFF Sawtooth wave amplitude: 1.23Vp-p 1 = Zoom ON Sawtooth wave amplitude: 70%

HBLKSW (1) : HBLK width control ON/OFF switch during 4:3 software full display mode on a

16:9 CRT 0 = Control OFF HBLK pulse generated from HPIN. 1 = Control ON HBLK pulse generated as pulse generated from HPIN or as

pulse generated from HVCO and width adjusted. Width adjustment is performed by the LEFT-BLK and RIGHTBLK registers.

V-SCROLL (6) : Vertical picture scroll control during zoom mode on a 16:9 CRT

(DC component added to sawtooth wave AGC output to control ZOOMSW cut timing) 0H = –0.25V Scrolled toward top of screen by 32H and top of picture

zoomed. 1FH = 0V 3FH = +0.25V Scrolled toward bottom of screen by 32H and bottom of picture

zoomed.

JUMPSW (1) : Reference pulse jump mode ON/OFF switch

(In addition to V-ASPECT control, sawtooth wave gain control performed for 100% of VBLK interval and 67% of picture interval) 0 = Jump mode OFF 1 = Jump mode ON

On a 4:3 CRT, jump mode expands the sawtooth wave amplitude to 112% with V-ASPECT; on a 16:9 CRT, jump mode compresses the sawtooth wave amplitude to 75% with V-ASPECT. The V blanking width is expanded at both the top and bottom of the picture. Blanking for the bottom of the picture starts 251H after VTIM, and blanking for the top of the picture can be varied as the blanking width after the reference pulse by the VBLKW register.

UP-VLIN (4) : Vertical linearity adjustment for top of picture

(Secondary component gain control for sawtooth wave added to sawtooth wave AGC output) 0H = 100% (Bottom/top of picture) FH = 115% (Bottom/top of picture) Top of picture compressed.

LO-VLIN (4) : Vertical linearity adjustment for bottom of picture

(Tertiary component gain control for sawtooth wave added to sawtooth wave AGC output) 0H = 100% (Bottom/top of picture) FH = 85% (Bottom/top of picture) Bottom of picture compressed.

LEFT-BLK (4) : HBLK width control for left side of picture when HBLKSW = 1

(Phase control for timing pulse generated from HVCO) 0H = +1.3µs HBLK width maximum 7H = 0µs Center HBLK: 13µs FH = –1.3µs HBLK width minimum

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CXA2095S

RIGHT-BLK (4) : HBLK width control for the right side of picture when HBLKSW = 1

(Phase control for timing pulse generated from HVCO) 0H = +1.3µs HBLK width maximum 7H = 0µs Center HBLK: 13µs FH = –1.3µs HBLK width minimum

HLOCK (1) : Lock status between Hsync and HVCO

0 = HVCO free run status 1 = Locked to Hsync

IKR (1) : AKB operation status

0 = REF-P return small and AKB loop unstable. 1 = REF-P return sufficient and AKB loop stable.

VNG (1) : Signal input status to VPROT pin

0 = No VPROT input 1 = VPROT input (In this case, RGB outputs are blanked.)

HNG (1) : Signal input status to HOFF pin

0 = No HOFF input 1 = HOFF input (In this case, RGB outputs are blanked.)

KILLER (1) : Color killer status

0 = Killer OFF status 1 = Killer ON status

Note) The following have been added to the CXA2025S.

EY-SW: Sub Add 09H, Bit 1 CD-MODE2: Sub Add 09H, Bit 0

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CXA2095S

Description of Operation

1. Power-on sequence

The CXA2095S does not have an internal power-on sequence. Therefore, all IC operations are controlled by the set microcomputer (I2C bus controller).

1) Power-on The IC is reset and the RGB outputs are all blanked. Hdrive starts to oscillate, but oscillation is at the maximum frequency (16kHz or more) and is not synchronized to the input signal. Output of vertical signal VTIM starts, VDRIVE outputs V sawtooth wave. Bus registers which are set by power-on reset are as follows.

AGING1 = 0: All white output aging mode OFF AGING2 = 0: All black output aging mode OFF RON = 0: Rch video blanking ON GON = 0: Gch video blanking ON BON = 0: Bch video blanking ON PICON = 0: RGB all blanking ON VOFF = 0: V sawtooth wave oscillation mode ∗VOFF = 1 for the CXA2025S. FHHI = 1: H oscillator maximum frequency mode CD-MODE = 0: Automatic selector mode of the countdown mode AKBOFF = 0: AKB mode

2) Bus register data transfer The register setting sequence differs according to the set sequence. Register settings for the following sequence are shown as an example.

Set sequence CXA2095S register settings Power-on Reset status in 1) above.

↓ ↓

Degauss Reset status in 1) above.

The CRT is degaussed in the completely darkened condition.

↓ ↓

IC initial setting The IC is set to the power-on initial settings. (See the following page.)

The HDRIVE oscillator frequency goes to the standard frequency (around

15.734kHz).

↓ ↓

AKB operation start PICON is set to 1 and a reference pulse is output from Rout, Gout and

Bout. Then, the IC waits for the cathode to warm up and the beam current to start flowing.

↓ ↓

AKB loop stable Status register IKR is monitored.

IKR = 0: No cathode current IKR = 1: Cathode current Note that the time until IKR returns to 1 differs according to the initial status of the cathode.

↓ ↓

Video output RON, GON and BON are set to 1 and the video signal is output from

Rout, Gout and Bout.

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CXA2095S

3) Power-on initial settings The initial settings listed here are reference values, and initial settings may be determined freely according to the set usage conditions.

PICTURE = 3F Hex Max (User Cont.) C-TRAP = 0 Chroma Trap OFF VM = 1 VM out ON HUE = 1F Hex Center (User Cont.) DC-TRAN = 0 Y DC transmission ratio 100% D-PIC = 1 Y black expansion ON COLOR = 1F Hex Center (User Cont.) TOT = 0 Chroma low frequency increased AXIS = 0 R-Y, G-Y Japan axis BRIGHT = 1F Hex Center (User Cont.) D-COL = 1 Dynamic Color ON ABL = 1 Picture/bright ABL mode SHARPNESS = 7 Hex Center (User Cont.) PRE-OVER = 0 Sharpness pre/over ratio 2:1 SHP-F0 = 1 Sharpness f0 3MHz SUB-CONT = 7 Hex Center (Adjust) CTRAP-ADJ = 7 Hex Center (Adjust) SUB-COLOR = 7 Hex Center (Adjust) SUB-HUE = 7 Hex Center (Adjust) SUB-BRIGHT = 1F Hex Center (Adjust) GAMMA = 0 Gamma OFF G-DRIVE = 1F Hex Center (Adjust) AGING1 = 0 Aging Mode OFF AGING2 = 0 Aging Mode OFF B-DRIVE = 1F Hex Center (Adjust) G-CUTOFF = 7 Hex Center (Adjust) B-CUTOFF = 7 Hex Center (Adjust) EY-SW = 0 Standard CD-MODE2 = 0 Standard RON = 0 Rch video output OFF GON = 0 Gch video output OFF BON = 0 Bch video output OFF PICON = 0 RGB all blanked VOFF = 0 Vdrive oscillation stopped FHHI = 0 Horizontal oscillator frequency standard CD-MODE = 0 V countdown auto mode AKBOFF = 0 AKB ON V-SIZE = 1F Hex Center (Adjust) V-COMP = 3 Vdrive high voltage fluctuation compensation amount max V-POSITION = 1F Hex Center (Adjust) AFC-MODE = 2 Center S-CORR = 7 Hex Center (Adjust) V-LIN = 7 Hex Center (Adjust) H-SIZE = 1F Hex Center (Adjust) REF-POSI = 0 PIN-COMP = 1F Hex Center (Adjust) VBLKW = 0

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CXA2095S

(Power-on initial settings cont.)

H-POSITION = 7 Hex Center (Adjust) PIN-PHASE = 7 Hex Center (Adjust) UP-CPIN = 7 Hex Center (Adjust) LO-CPIN = 7 Hex Center (Adjust) AFC-BOW = 7 Hex Center (Adjust) AFC-ANGLE = 7 Hex Center (Adjust) V-ASPECT = 0 Hex 16:9 CRT Full Mode ZOOMSW = 1 16:9 CRT HBLKSW = 1 Hblk width adjust ON V-SCROLL = 1F Hex Center (User) JMPSW = 0 16:9 CRT Full Mode UP-VLIN = 7 Hex 16:9 CRT Full Mode LO-VLIN = 7 Hex 16:9 CRT Full Mode LEFT-BLK = F Hex Hblk width min. RIGHT-BLK = F Hex Hblk width min.

2. Various mode settings

The CXA2095S contains bus registers for deflection compensation which can be set for various wide modes. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once distortion adjustment has been performed in full mode, wide mode settings can be made simply by changing the corresponding register data.

• VDRIVE signal picture distortion adjustment registers V-SIZE, V-POSITION, S-CORR, V-LIN

• E/WDRIVE signal picture distortion adjustment registers H-SIZE, PIN-COMP, PIN-PHASE, UP-CPIN, LO-CPIN

• Wide mode setting registers V-ASPECT, ZOOMSW, HBLKSW, V-SCROLL, JMPSW, UP-VLIN, LO-VLIN, LEFT-BLK, RIGHT-BLK

Examples of various modes are listed below. These modes are described using 480 lines as the essential number of display scanning lines. Wide mode setting register data is also listed, but settings may differ slightly due to IC variation. The standard setting data differs for 16:9 CRTs and 4:3 CRTs.

V-ASPECT 0 H 2F H V-SCROLL 1F H 1F H ZOOMSW 1 0 UP-VLIN 0 H 0 H LO-VLIN 0 H 0 H JMPSW 0 0 HBLKSW 0 0 LEFT-BLK 7 H 7 H RIGHT-BLK 7 H 7 H

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CXA2095S

1) 16:9 CRT full mode This mode reproduces the full 480 lines on a 16:9 CRT. 4:3 images are reproduced by stretching the picture to the left and right. Normal images are compressed vertically, but 16:9 images can be reproduced in their original 16:9 aspect ratio with a video source which compresses (squeezes) 16:9 images to 4:3 images. The register settings are the 16:9 CRT standard values.

2) 16:9 CRT normal mode In this mode, 4:3 images are reproduced without modification. A black border appears at the left and right of the picture. In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2095S also has a register (H-SIZE) which controls the H size, but the control width is not sufficient for 25% compression. Therefore, external measures must be taken such as switching the H deflection coil. Full mode should be used when performing memory processing and attaching a black border to the video signal. H blanking of the image normally uses the flyback pulse input to AFCPIN (Pin 36). However, the blanking width can be varied according to the control register setting when blanking is insufficient for the right and left black borders. The following three settings are added to the 16:9 CRT standard values for the register settings.

HBLKSW = 1 LEFT-BLK = Adjustment value

RIGHT-BLK = Adjustment value The H angle of deflection also decreases, causing it to differ from the PIN compensation amount during H size full status. Therefore, in addition to the wide mode registers, PIN-COMP must also be readjusted only for this mode.

3) 16:9 CRT zoom mode In this mode, 4:3 images are reproduced by enlarging the picture without other modification. The top and bottom of normal 4:3 images are lost, but almost the entire picture can be reproduced for vista size video software, etc. which already has black borders at the top and bottom. The enlargement ratio can be controlled by the V-ASPECT register, and enlarging the picture by 33% compared to full mode allows zooming to be performed for 4:3 images without distortion. In this case, the number of scanning lines is reduced to 360 lines compared to 480 lines for full mode. The zooming position can be shifted vertically by the V-SCROLL register. V blanking of the image normally begins from V sync and continues for 2H after the AKB reference pulse, and the top and bottom parts are also blanked during this mode. Adjust the following two registers with respect to the 16:9 CRT standard values for the register settings.

V-ASPECT = 2FH

V-SCROLL = 1FH or user control

4) 16:9 CRT subtitle-in mode When Cinema Scope size images which have black borders at the top and bottom of the picture are merely enlarged with the zoom mode in 3) above, subtitles present in the black borders may be lost. Therefore, this mode is used to super-compress only the subtitle part and reproduce it on the display. Add the LO-VLIN adjustment to the zoom mode settings for the register settings.

V-ASPECT = 2FH

V-SCROLL = 1FH or user control

LO-VLIN = Adjustment value The LO-VLIN register causes only the linearity at the bottom of the picture to deteriorate. Therefore, UP-VLIN should also be adjusted if the top and bottom of the picture are to be made symmetrical. Since the picture is compressed vertically, the number of scanning lines exceeds 360 lines.

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5) 16:9 CRT V compression mode This mode is used to reproduce two 4:3 video displays such as for PandP. The V size must be compressed to 67% in order to reproduce two displays on a 16:9 CRT without distortion using 480 scanning lines, and this can be set by JMPSW. Compression is performed after the AKB reference pulse, so the reference pulse remains in the overscan position. The V blanking width after the reference pulse becomes larger than normal and can be varied by the VBLKW register. During this mode, the bottom V blanking width is also expanded to 10H wider than normal so that the bottom of the picture is not overscanned. 16:9 CRT standard values are used with only the JMPSW setting changed for the register settings.

JMPSW = 1

6) 16:9 CRT Sony type wide zoom mode This mode reproduces 4:3 video software naturally on wide displays by enlarging 4:3 images without other modification and compressing the parts of the image which protrude from the picture into the top and bottom parts of the picture. The display enlargement ratio is controlled by V-ASPECT, and the compression ratios at the top and bottom of the picture are controlled by UP-VLIN and LO-VLIN. Adjust the following three registers with respect to the 16:9 CRT standard values for the register settings.

V-ASPECT = Adjustment value UP-VLIN = Adjustment value LO-VLIN = Adjustment value

7) 4:3 CRT normal mode This is the standard mode for 4:3 CRTs. The register settings are the 4:3 CRT standard values.

8) 4:3 CRT V compression mode This mode is used to reproduce M-N converter output consisting of 16:9 images expanded to a 4:3 aspect ratio and other squeezed signals without distortion on a 4:3 CRT. The V size must be compressed to 75% in order to reproduce 4:3 images in a 16:9 aspect ratio. Compressing the V size with the JMPSW register used in mode 5) above, compresses the V size to 67%. Therefore, V-ASPECT is set to enlarge the V size by 8%. AKB reference pulse handling and V blanking are the same as for mode 5) above. 4:3 CRT standard values are used with the V-ASPECT and JMPSW settings changed for the register settings.

V-ASPECT = 3FH JMPSW = 1

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Mode Settings

1)-1

1)-2

16:9 16:9

16:9

4:3

16:9 4:3

4:3

4:3 (16:9 + subtitle area)

4:3

16:9

16:9 CRT full Wide full

16:9 CRT normal

16:9 CRT zoom

16:9 CRT with subtitle area on

16:9 CRT

V compression

16:9 CRT wide zoom

4:3 CRT normal

4:3 CRT

V compression

V-ASPECT = 0h: V size 75% V-ASPECT = 0h: V size 75% V-ASPECT = 0h: V size 75%

HBLKSW = 1h: HBLK width adjustment ON LEFT-BLK = Adjustable RIGHT-BLK = Adjustable PIN-COMP = Adjustable (External support: H-DY H amplitude 75%)

V-ASPECT = 2Fh: V size 100% ZOOMSW = 1h: Zoom ON

V size limited at 75%

V-SCROLL = 0h: Zoom bottom of video image

1Fh: Zoom center of video image 3Fh: Zoom top of video image Adjustable: Open to user

V-ASPECT = 2Fh: V size 100% UP-VLIN = Adjustable: Slightly compresses top of

video image

LO-VLIN = Adjustable: Significantly compresses

bottom of video image ZOOMSW 1h: V size limited at 75% (V-SCROLL = Adjustable)

V-ASPECT = 0h: V size 75% JMPSW = 1h: Reference pulse skipping ON

V size compressed 67% after the reference pulse

(compressed to 50% total) VBLKW = Adjustable: VBLK width expanded at

top and bottom of video image V-ASPECT = Adjustable: V size 90%

UP-VLIN = Adjustable: LO-VLIN = Adjustable: (S-CORR = Adjustable):

V-ASPECT = 2Fh: V size 100% V-ASPECT = 3Fh: V size 112%

JMPSW = 1h: Reference pulse skipping ON

(compressed to 75% total) VBLKW = Adjustable: VBLK width expanded at

top and bottom of video image

Setting CRT SIZE

SOFT SIZE

MODE NAME I2C BUS REGISTER

∗

The amount of picture distortion compensation in a vertical direction position of the CRT does not change in response to the above modes; as a result, the initial values of each picture distortion register can be used as it is.

Compression of top and bottom of video image

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CXA2095S

3. Signal processing

The CXA2095S is comprised of sync signal processing, H deflection signal processing, V deflection signal processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I2C bus.

1) Sync signal processing The Y signals input to Pins 43 and 44 are sync separated by the horizontal and vertical sync separation circuits. The resulting horizontal sync signal and the signal obtained by frequency dividing the 32 FH-VCO output using the ceramic oscillator (frequency 503.5kHz) by 32 are phase-compared, the AFC loop is constructed, and an H pulse synchronized with the H sync is generated inside the IC. Adjustment of the H oscillator frequency is unnecessary. When the AFC is locked to the H sync, 1 is output to the status register (HLOCK) and that can be used to detect the presence of the video signal. The vertical sync signal is sent to the V countdown block where the most appropriate window processing is performed to obtain V sync timing information which resets the counter. AKB and other V cycle timing are then generated from this reset timing.

2) H deflection signal processing The H pulse obtained through sync processing is phase-compared with the H deflection pulse input from Pin 36 to control the phase of the HDRIVE output, and so the horizontal position of the image projected on the CRT is controled. In addition, the compensation signal generated from the V sawtooth wave is superimposed. As a result, the vertical picture distortion is compensated. The H deflection pulse is used to H blank the video signal. When the pulse input from Pin 36 has a narrow width, the pulse generated by the IC can be added to the H deflection pulse and used as the H blanking pulse. (HBLKSW) Pin 36 is normally pulse input, but if the pin voltage drops to the GND level, HDRIVE output goes to high level (DC) and 1 is output to the status register (HNG). To release this status, turn the power off and then on again.

3) V deflection signal processing The V sawtooth wave is generated at the cycle of the reset pulse output from the countdown system. After performing wide deflection processing for this sawtooth wave, picture distortion adjustment is performed by the VDRIVE and E/WDRIVE function circuits and the signal is output as the VDRIVE and E/WDRIVE signals.

4) Y signal processing The Y signal input to Pin 4 (specified input level: level at which a 100% white (including sync, 140 IRE) signal with a gain of 6dB with respect to the video signal standard becomes a 2Vp-p signal) passes through the subcontrast control, trap for eliminating the chroma signal, sharpness control, clamp and black expansion circuits, and is then input to the switching circuit (YUV SW) for the external Y/color difference signal. The differential waveform of the Y signal delayed for approximately 200ns from the Y input is output from Pin 45 as the signal for VM. The VM signal is not output in the following cases.

When EY-SW = 0 and YUV SW (Pin 9) or YS (Pin 15) is high

When EY-SW = 1 and YS (Pin 15) is high The f0 of the built-in filter is automatically adjusted inside the IC, but the trap f0 may require fine adjustment by the I2C bus (CTRAP-ADJ) if it is affected by variation. When inputting a signal which has been Y/C separated by a comb filter, etc., the trap should be turned OFF.

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CXA2095S

5) C signal processing The chroma signal input to Pin 5 (specified input level: level at which a 40 IRE burst level signal with a gain of 6dB with respect to the video signal standard becomes a 570mVp-p signal) passes through the ACC, TOT (secondary HPF), color control and demodulation circuits. The signal then becomes the R-Y and B-Y color difference signal and is input to the YUV SW circuit. When the burst level goes to –31dB or less with respect to the specified input level, the color killer operates and the color difference signal is not output. The external Y, color difference signals input to Pins 10, 11 and 12 pass through the clamp and amplifier circuits and are input to the YUV SW circuit. The YUV SW circuit is controlled by the YUV SW (Pin 9). However, its operation differs depending on the data in the I2C bus register (EY-SW). In other words, the YUV SW circuit output is as follows.

When EY-SW = 0: Internal Y/color difference signal when YUV SW is low,

external Y/color difference signal (Pins 9, 10 and 11) when YUV SW is high

When EY-SW = 1: Internal Y/color difference signal when YUV SW is low,

internal Y/external color difference signal when YUV SW is high When external Y/color difference signal is selected , the picture quality can be adjusted in the same manner as with the normal internal Y signal by setting EY-SW to 1 and then inputting the external Y signal to YIN (Pin 4). However, in this case the delay time between the Y signal and color difference signals must be realigned. The specified input level for the external Y signal is the level at which a normal video signal standard, 100 IRE, 100% white signal becomes a 0.7Vp-p signal. The specified input level for the external color difference signal is the level at which a normal video signal standard, 40 IRE burst level demodulates a 258mVp-p chroma signal at orthogonal coordinates to become a 0.8 times signal (R-Y is demodulated by the 90° axis to become a 1.14 times signal, B-Y is demodulated by the 0° axis to become a 2.03 times signal).

The G-Y signal is generated as the base of Y, color difference signals at the axis adjustment circuit. The Y signal is added to R-Y, G-Y, and B-Y respectively and these signals become R, G, and B signals. And they are input to the RGB block.

6) RGB signal processing The RGB signals obtained from the Y/C block pass through the half-tone switch circuit (YM SW), the switch circuit for the external RGB signal (YS SW), the picture control, dynamic color, gamma compensation, clamp, brightness control, drive adjustment, cut-off adjustment and auto cut-off circuits, and are output to Pins 20, 22 and 24. The RGB signals input to Pins 16, 17 and 18 are the level at which a normal video signal standard, 100 IRE, 100% white signal becomes a 0.7Vp-p signal. The voltage applied to Pin 26 (ABLIN) is compared with the internal reference voltage, integrated by the capacitor which is connected to Pin 27, and performs picture control and brightness control. In order to adjust the white balance (black balance), this IC has a drive control function which adjusts the gain between the RGB outputs and a cut-off control function which adjusts the DC level between the RGB outputs. Both drive control and cut-off control are adjusted by the I2C bus, with the Rch fixed and the G and Bch variable. An auto cut-off function (AKB) which forms a loop between the IC and CRT and performs adjustment automatically has also been added. This function can compensate for changes in the CRT with time. Auto cut-off operation is as follows.

• R, G and B reference pulses for auto cut-off, shifted 1H each in the order mentioned, appear at the top of the picture (actually, in the overscan portion). The reference pulse uses 1H in the V blanking interval, and is output from each R, G and B output pin.

• The cathode current (IK) of each R, G and B output is converted to a voltage and input to Pin 25.

• The voltage input to Pin 25 is compared with the reference voltage in the IC, and the current generated by

the resulting error voltage charges the capacitors connected to Pins 19, 21 and 23 for the reference pulse interval and is held during all other interval.

• The loop functions to change the DC level of the R, G and B outputs in accordance with the capacitor pin voltage so that the Pin 25 voltage matches the reference voltage in the IC.

The Rch for the reference voltage in the IC is fixed and the G and Bch are cut-off controlled by the I2C bus. During G/B-CUTOFF center status, the loop functions so that the Rch, Gch and Bch for the reference pulse input to Pin 25 is all 1Vp-p. The reference pulse timing can be varied by the I2C bus. When AKB is not used, the IC can be set to manual cut-off adjustment mode with I2C bus settings. In this case, the DC level of the R, G and B outputs can be varied by applying voltages independently to Pins 19, 21 and 23.

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CXA2095S

4. Notes on operation

When designing the board pattern for TV set, interference from around the power supply and GND should be considered as the RGB and deflection signals output from the CXA2095S are DC direct connected. Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the bypass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also, locate the XTAL oscillator, ceramic oscillator and IREF resistor as near to the pin as possible, and do not wire signal lines near this pin. Drive the Y, external Y/color difference and external RGB signals at a sufficiently low impedance, as these signals are clamped when they are input using the capacitor connected to the input pin. The built-in capacitor receives the chroma signal, so apply a DC bias of about VCC/2 externally and input the chroma signal at a sufficiently low impedance.

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CXA2095S

V-SIZE

Time [ms]

0 5 10 15 20

2.4

V [V]

3.6

3.4

3.2

3.0

2.8

2.6

VSIZE = 0 VSIZE = 1F VSIZE = 3F

V-POSITION

Time [ms]

0 5 10 15 20

2.4

V [V]

3.6

3.4

3.2

3.0

2.8

2.6

V-POSITION = 0 V-POSITION = 1F V-POSITION = 3F

S-CORR

Time [ms]

0 5 10 15 20

2.4

V [V]

3.6

3.4

3.2

3.0

2.8

2.6

SCORR = 0 SCORR = 7 SCORR = F

V-LIN

Time [ms]

0 5 10 15 20

2.4

V [V]

3.6

3.4

3.2

3.0

2.8

2.6

VLIN = 0 VLIN = 7 VLIN = F

V-ASPECT

Time [ms]

0 5 10 15 20

2.2

V [V]

3.8

3.4

3.2

3.0

2.8

2.6 VASPECT = 0

VASPECT = 1F VASPECT = 3F

3.6

2.4

V-SCROLL

Time [ms]

0 5 10 15 20

2.4

V [V]

3.8

3.4

3.2

3.0

2.8

2.6

VSCROLL = 0 VSCROLL = 1F VSCROLL = 3F

3.6

Curve Data

I2C bus data conforms to the “I2C bus register initial settings” of the Electrical Characteristics Measurement Conditions (P. 14).

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CXA2095S

UP-VLIN

Time [ms]

0 5 10 15 20

2.4

V [V]

3.6

3.4

3.2

3.0

2.8

2.6

DATA-0 DATA-7 DATA-F

LO-VLIN

Time [ms]

0 5 10 15 20

2.4

V [V]

3.6

3.4

3.2

3.0

2.8

2.6

LO-VLIN = 0 LO-VLIN = 7 LO-VLIN = F

PIN-COMP

Time [ms]

0 5 10 15 20

3.0

V [V]

4.2

4.0

3.8

3.6

3.4

3.2

PIN-COMP = 0 PIN-COMP = 1F PIN-COMP = 3F

PIN-PHASE

Time [ms]

0 5 10 15 20

3.3

V [V]

4.1

3.9

3.8

3.7

3.6

3.5 PIN PHASE = 0

PIN PHASE = 7 PIN PHASE = F

4.0

3.4

LO-CPIN

Time [ms]

0 5 10 15 20

3.4

V [V]

4.1

3.9

3.8

3.7

3.6

3.5

LO-CPIN = 0 LO-CPIN = 7 LO-CPIN = F

4.0

UP-CPIN

Time [ms]

0 5 10 15 20

3.3

V [V]

4.1

3.9

3.8

3.7

3.6

3.5

UP-CPIN = 0 UP-CPIN = 7 UP-CPIN = F

4.0

3.4

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CXA2095S

H POSITION

DATA

0 4 8 12 16

Time [µs]

3.0

2.5

2.0

1.5

1.0

0.5

2 6 10 14

PICTURE

DATA

0 20 40 60 70

–15

Gain [dB]

–5

–10

10 30 50

COLOR

DATA

0 20 40 60 70

–20

Gain [dB]

–5

–10

–15

10 30 50

CTRAP

Frequency [MHz]

0 2 4 6 7

–35

Gain [dB]

–5

–10

–15

–20

–25

CTRAP = 0 CTRAP = 1

–30

1 3 5

H-SIZE

Time [ms]

0 5 10 15 20

3.0

V [V]

4.6

4.2

4.0

3.8

3.6

3.4 HSIZE = 0

HSIZE = 1F HSIZE = 3F

4.4

3.2

SHARPNESS

Frequency [MHz]

0 4 8 12 16

–20

Gain [dB]

–5

–10

–15

SHARPNESS = 0 SHARPNESS = 7 SHARPNESS = F

2 6 10 14

SYNC center

t [µs]

µs

HSIN

AFCPIN

COLOR OFF when DATA = 0 (–40dB or less)

∗

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CXA2095S

DATA

–4

Gain [dB]

–1

–2

–3

SUB COLOR

0 4 8 12 162 6 10 14

SUB CONT

DATA

0 4 8 12

–4

Gain [dB]

–1

–2

–3

2 6 10 14

–4

Gain [dB]

–1

–2

–3

B-DRIVE, G-DRIVE

DATA

0 20 40 60 7010 30 50

BRIGHT

DATA (Hex)

0 0F 1F 2F 3F

–1.0

Potential difference between Rch reference pulse level and black level [Vp-p]

0.25

–0.5

SUB-BRIGHT = 3F SUB-BRIGHT = 1F SUB-BRIGHT = 0

07 17 27 37

SUB-BRIGHT

DATA (Hex)

0 0F 1F 2F 3F

–0.6

Potential difference between Rch reference pulse level and black level [Vp-p]

–0.4

–0.1

07 17 27 37

–0.5

–0.3

–0.2

GAMMA

YIN input amplitude [IRE]

0 20 40 80 120

1.5

Rch output [V]

5.0

3.0

4.0

10 30 60 100

3.5

4.5

2.0

2.5

70 11050 90

GAMMA 0 GAMMA 1 GAMMA 2 GAMMA 3

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CXA2095S

G, B – CUTOFF

DATA (Hex)

0 3 F

2.5

IKIN reference pulse voltage [V]

4.0

3.0

5 B

3.5

7 D9

Rch Gch, Bch IK clamp level

AKB open loop characteristics

Voltage applied to Rch, Gch and Bch sample-and-hold capacitance pins [V]

0 8

R, G and B output reference pulse potential [V]

1 2 415 73 6

0.5

2.5

1.5

3.5

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CXA2095S

Package Outline Unit: mm

48PIN SDIP (PLASTIC)

13.0

+ 0.3

– 0.1

4.6

+ 0.4

– 0.1

0.25

+ 0.1

– 0.05

48 25

1 24

1.778

15.24

0° to 15°

0.5 ± 0.1

0.9 ± 0.15

3.0 MIN 0.5 MIN

SONY CODE EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

PLATING

COPPER / 42 ALLOY

5.1g

SDIP-48P-02 SDIP048-P-0600

43.2

+ 0.4 – 0.1

SOLDER/PALLADIUM

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).