Datasheet CXA2094Q Datasheet (Sony)

– 1 –

CXA2094Q

48 pin QFP (Plastic)

E97725A86

US Audio Multiplexing Decoder

Description

The CXA2094Q is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction. Various kinds of filters are built in while adjustment and mode control are all executed through I2C BUS.

Features

• Adjustment free of VCO and filter.

• Audio multiplexing decoder and dbx noise

reduction decoder are all included in a single chip.

Almost any sort of signal processing is possible

through this IC.

• All adjustments are possible through I2C BUS to

allow for automatic adjustment.

• Various built-in filter circuits greatly reduce external

parts.

• There are two systems for external inputs.

• There is an additional SAP output.

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VCC 11 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 0.6 W

Range of Operating Supply Voltage

9 ± 0.5 V

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

∗ A license of the dbx-TV noise reduction system is required for the use of this device.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

2627

28

29

30

40

39

38

37

36

35

34

31

32

33

41 42

43 44 45 46 47 48

1

SDA

SCL

DGND

MANIN

NC

COMPIN

NC

PCINT2

PCINT1

VCATC

VCAIN

VEOUT

VETC

VEWGT

NC

VE

SAPIN

NC

SAPOUT

TVOUT-L

TVOUT-R

AUX2-L

TVOUT-S

AUX2-R

AUX1-L

AUX1-R

ESAPIN

SOUT

VCAWGT

NC

VGR

NC

GND

SAPTC

V

CC

SUBOUT

STIN

MAINOUT

PLINT

IREF

NC

NOISETC

NC

Standard I/O Level

• Input level

COMPIN (Pin 12) 100mVrms

245mVrms (Selected by INSW) AUX1-L/R (Pins 42 and 41) 490mVrms AUX2-L/R (Pins 45 and 44) 490mVrms

• Output level TVOUT-L/R (Pins 47 and 46) 490mVrms

Pin Configuration (Top View)

– 2 –

CXA2094Q

Block Diagram

VGR

IREF

DGND

SCL

SDA

SAPOUT

SAPIN

STIN

VE

VEWGT

VETC

VEOUT

VCAIN

VCAWGT

VCATC

MAININ

MAINOUT

SUBOUT

PLINT

PCINT1

COMPIN

V

CC

GND

NOISETC

SAPTC

AUX2-L

IREF

SW

LPF LPF

HPF

RMSDET

VCAVEDeEm

LOGIC

VCA

LPF

1/2

1/4VCOLFLT

STLPF

VCA LPF

BPF

SAPVCO

LPF

NOISE

DET

SAPIND

"PONRES"

STIND

"SAP"

"NOISE"

NRSW/FOMO/SAPC

WIDEBAND

SPECTRAL

"STEREO"

DeEm

FLT

AMP

(+4dB)

I

2

C BUS I/F

(+6dB)

AUX1-R AUX1-L

AUX2-R

PCINT2

TVSW

TVOUT-L

TVOUT-R

FEXT2

FEXT1

TVSW/EXT/M1

33 32

28

24

ATT/INSW

8

9

11

12

23

18

17

14

25

15

20

2

1

48

27

34

36

35

37

46

47

44

45

41 42

3

4

22

40

MATRIX

39

LPF

38

TVOUT-S

ESAPIN

SOUT

– 3 –

CXA2094Q

Pin Description (Ta = 25°C, VCC = 9V)

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

SCL

DGND

MAININ

—

4.0V

Serial clock input pin. VIH > 3.0V VIL < 1.5V

Digital block GND.

Input the (L + R) signal from MAINOUT (Pin 4).

1

2

3

MAINOUT

NC

4.0V

—

(L + R) signal output pin.

—

VCC

147

1k

15k

↓

200µ

V

CC

× 4

4

5

NC

—

6

NC

—

7

10.5k

VCC

7.5k

↓ 35µ

2.1V

× 4

4k

3k

1

2

VCC

10k

VCC

147

3

53k

4V

– 4 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit

Description

PCINT1

PCINT2

PLINT

4.0V

5.1V

Stereo block PLL loop filter integrating pin.

Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.)

VCC

147

20k

↓

26µ

20k

10k

20k

↓

50µ

20k

11

22k

VCC

30k

147

8

4k

VCC

× 2

10k

2k

147

9

8

9

11

COMPIN 4.0V

Audio multiplexing signal input pin.

12

VCC

12

24k

4V

34k

14k 147

24k 24k

NC

—

10

NC

—

13

– 5 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

VGR

IREF

GND

1.3V

—

Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.)

Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62kΩ (±1%) resistor between this pin and GND.)

Analog block GND.

Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.)

14

15

17

SAPTC

4.5V

18

8k

4k

3k

10k

VCC

↓ 50µ

1k

VCC

18

17

40k 40k 30k

30p

1.8k

16k

6.3k

147

30k 15k 30k

VCC

× 2

V

CC

15

× 4

11k

9.7k

19.4k

2.06k

3k

147

VCC

11k

14

NC

—

16

NC

—

19

VCC

—

Supply voltage pin.

20

NC

—

21

– 6 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

SUBOUT

STIN

NOISETC

4.0V

3.0V

(L-R) signal output pin.

Input the (L-R) signal from SUBOUT (Pin 22).

Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.)

22

23

SAPIN

4.0V

Input the (SAP) signal from SAPOUT (Pin 25).

27

24

2k

4k

1k

147

580

14.4k

580

4k

10P

2k2k

Vcc

22

23k

147

18k

20k

11.7k

23k

4V

147

18k

4V

VCC

23

27

3k

3.3k

4k

4V

Vcc

8k

× 2

10k

1k

2k

Vcc

200k

24

SAPOUT 4.0V

SAP FM detector output pin.

25

24k ↓ 10µ

580

Vcc

5P

580

4k ↓ 50µ

10k

147

25

– 7 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

VE

VETC

4.0V

1.7V

Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3kΩ resistor in series between this pin and GND.)

Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3µF capacitor between this pin and GND.)

28

VEWGT

4.0V

Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047µF capacitor and a 3kΩ resistor in series between this pin and GND.)

32

33

Vcc

4V

36k

2.9V

580

147

580

8k

30k ↓ 8µ

4k ↓ 50µ

32

20k ↓ 7.5µ

4k ↓ 50µ

Vcc

× 4

33

7.5k

147

VCC

28

NC

—

26

NC

—

29

NC

—

30

NC

—

31

– 8 –

CXA2094Q

No.

Symbol

Pin voltage

Equivalent circuit

Description

VEOUT

VCAIN

VCAWGT

4.0V

Variable de-emphasis output pin. (Connect a 4.7µF non-polar capacitor between Pins 34 and 35.)

VCA input pin. Input the variable de-emphasis output signal from Pin 34 via a coupling capacitor.

Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.)

34

35

VCATC

1.7V

Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.)

36

37

Vcc

10k

580

5P

34

4k

VCC

30k

8k

36k

2.9V

3p

580

147

40k 40k

↓

50µ

↓

8µ

37

↓

50µ

VCC

4k

20k

× 4

↓

7.5µ

36

VCC

20k

VCC

47k

35

– 9 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

ESAPIN

4.0V

Additional SAP output pin.

Input the signal from SOUT (Pin 38).

SOUT

4.0V

38

39

VCC

15k

VCC

× 4

1k

38

↓

200µ

VCC

4V

147

47k

10k

39

AUX1-R

4.0V

Right channel external input 1 pin.

41

AUX1-L

4.0V

Left channel external input 1 pin.

42

AUX2-R

4.0V

Right channel external input 2 pin.

44

AUX2-L

4.0V

Left channel external input 2 pin.

45

VCC

4V

27.5k

47k

10k

41 42 44 45

TVOUT-S

4.0V

Optional output pin. From this pin monaural or additional SAP is output.

40

TVOUT-R

4.0V

TVOUT right channel output pin.

46

TVOUT-L

4.0V

TVOUT left channel output pin.

47

3k

580

VCC

46 47

40

43

NC

—

43

– 10 –

CXA2094Q

No.

Symbol

Pin voltage

Equivalent circuit Description

7.5k

4.5k

× 5

4k

3k

7.5k

V

CC

↓ 35µ

2.1V

× 2

48

SDA

—

Serial data I/O pin. VIH > 3.0V VIL < 1.5V

48

– 11 –

CXA2094Q

Electrical Characteristics

COMPIN input level

(100% modulation level)

(Ta = 25°C, V

CC = 9V)

Item

Current consumption

Main output level

Main de-emphasis

frequency characteristic

Main LPF frequency

characteristic

Main distortion

Main overload distortion

Main S/N

Sub output level

Sub LPF frequency

characteristic

Sub distortion

Sub overload distortion

Sub S/N

ST → SAP

Crosstalk

No.

1

2

3

4

5

6

7

8

9

10

11

12

13

Signal

Icc

Vmain

FCdeem

FCmain

THDm

THDmmax

SNmain

Vsub

FCsub

THDsub

THDsmax

SNsub

CTst

Mode

MONO

ST

SAP

Input pin

—

12

Min.

22

440

–1.2

–3.0

–

61

150

–3.0

–

56

60

Typ.

32

490

0

–1.0

0.1

0.15

69

190

–0.5

0.1

0.2

64

70

Max.

42

540

1.0

0.5

–

230

1.0

2.0

–

Unit

mA

mVrms

dB

%

dB

mVrms

dB

%

dB

Input signal

No signal

Mono 1kHz 100% mod.

Pre-em. ON

Mono 5kHz 30% mod.

Pre-em. ON

Mono 12kHz 30% mod.

Pre-em. ON

Mono 1kHz 100% mod.

Pre-em. ON

Mono 1kHz 200% mod.

Pre-em. OFF

Mono 1kHz,

Pre-em. ON

SUB (L-R) 1kHz,

100% mod., NR OFF

SUB (L-R) 12kHz,

30% mod., NR OFF

SUB (L-R) 1kHz,

100% mod., NR OFF

SUB (L-R) 1kHz,

200% mod., NR OFF

SUB (L-R) 1kHz,

NR OFF

SUB (L-R) 1kHz,

100% mod., NR ON,

SAP Carrier (5fH)

Measurement

conditions

20 log

('5k'/ '1k')

20 log

('12k'/ '1k')

20 log

('100%'/ '0%')

20 log

('12k'/ '1k')

20 log

('100%'/ '0%')

20 log

('NRSW = 0'/

'NRSW = 1')

Filter

15kLPF

1kBPF

Output

46/47

22

47

fH = 15.734kHz

Main (L + R)

(Pre-Emphasis : OFF)

SUB (L – R) (dbx-TV : OFF)

Pilot

SAP Carrier

INSW = 0

= 245mVrms

= 490mVrms

= 49mVrms

= 147mVrms

INSW = 1

= 100mVrms

= 200mVrms

= 20mVrms

= 60mVrms

– 12 –

CXA2094Q

No.

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Item

Sub pilot leak

Stereo ON level

Stereo ON/OFF

hysteresis

SAP output level

SAP LPF frequency

characteristic

SAP distortion

SAP S/N

SAP → ST

Cross talk

SAP ON level

SAP ON/OFF hysteresis

ST separation 1 L → R

ST separation 1 R → L

ST separation 2 L → R

ST separation 2 R → L

TVOUT output level

TVOUT cross talk

TVOUT

muted amount

Symbol

PCsub

THst

HYst

Vsap

FCsap

THDsap

SNsap

CTsap

THsap

HYsap

STLsep1

STRsep1

STLsep2

STRsep2

Vtv

CTtv1

CTtv2

MUtv1

MUtv2

Mode

ST

SAP

ST

SAP

ST

EXT

INT

EXT

INT

EXT

Input pin

12

41/42

44/45

41/42

44/45

12

41/42

44/45

Min.

–

–9.0

2.0

150

–3.0

–

46

60

–12.0

2.0

23

–0.5

–

Typ.

–42

–6.0

6.0

190

0

2.5

55

70

–9.0

4.0

35

0

–75

–90

–85

–90

Max.

–30

–3.0

10.0

230

2.5

6.0

–

–6.5

6.0

–

0.5

–60

–80

–70

–75

Unit

dB

mVrms

dB

%

dB

Input signal

PILOT (f

H) 0dB

Change

PILOT (f

H) Level

SAP 1kHz 100% mod.

NR OFF

SAP 10kHz 30% mod

.

NR OFF

SAP 1kHz 100% mod

.

NR OFF

SAP 1kHz, NR OFF

SAP 1kHz 100% mod.

NR ON, Pilot (fH)

Change

SAP Carrier (5f

H)

Level

ST-L 300Hz 30% mod

.

NR ON

ST-R 300Hz 30% mod

.

NR ON

ST-L 3kHz 30% mod

.

NR ON

ST-R 3kHz 30% mod

.

NR ON

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

MONO 1kHz 100% mod.

Pre-em. ON

MONO 1kHz 100% mod.

Pre-em. ON

Sine wave 1kHz,

490mVrms

Measurement

conditions

0dB = 49mVrms

20 log (‘on

level'/ 'off level')

20 log

('10k'/ '1k')

20 log

('100%'/ '0%')

20 log ('NRSW

= 1'/ 'NRSW = 0')

0dB = 147mVrms

20 log (‘on

level’/’off level’)

0dB = 490mVrms

EXT → INT

0dB = 490mVrms

INT → EXT

20 log

(M1 =

"0"/M1 = "1")

20 log

(M1 =

"0"/M1 = "1")

Filter

f

H BPF

15kLPF

1kBPF

15kLPF

1kBPF

Output

22

BUS

RETURN

25

47

BUS

RETURN

46/47

– 13 –

CXA2094Q

No.

33

34

35

36

Item

TVOUT DC offset

TVOUT distortion

TVOUT S/N

TVOUT overload distortion

Symbol

OStv

THDtv

SNtv

THDtvmax

Mode

INT

EXT

Input pin

—

41/42

44/45

41/42

44/45

41/42

44/45

Min.

–25

–

75

–

Typ.

0

0.01

88

0.1

Max.

25

0.5

–

1.0

Unit

mV

%

dB

%

Input signal

No signal

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

2Vrms

Measurement

conditions

Mute (M1 = 0)/

DC difference

when there is

no signal

20 log

('490mVrms'/

'No signal')

Filter

15kLPF

Output

46/47

– 14 –

CXA2094Q

Electrical Characteristics Measurement Circuit

C21

4.7µ

C23

4.7µ

C9

10µ

25

2627

28

29

30

36

31

VCATC

VCAIN

VEOUT

VETC

VEWGT

NC

VE

SAPIN

NC

SAPOUT

3

4

5

6

7

8

10

11

SCL

DGND

MAININ

NC

COMPIN

NC

PCINT2

PCINT1

MAINOUT

PLINT

13

14

15

16

17

18

19

20

21

22

23

24

NC

VGR

NC

GND

SAPTC

V

CC

SUBOUT

STIN

IREF

NC

NOISETC

NC

40

45

46

48

SDA

TVOUT-L

TVOUT-R

AUX2-L

TVOUT-S

AUX2-R

AUX1-L

AUX1-R

ESAPIN

SOUT

VCAWGT

NC

C18

4.7µ

C16

2700p

R7

3.3k

C12

3.3µ

TANTALUM

C13

0.047µ

R4

3k

S1

S2

S3

S4

BUFF

FILTERS

15kHz LPF

f

H BPF

1kHz BPF

MEASURES

SIGNAL

GENERATOR

C2

1µ

C24

4.7µ

C17

4.7µ

C22

100µ

VCC

V6

9V

GND

R8

62k

METAL

± 1%

SIGNAL

GENERATOR

C20

10µ

C14

5600p

R6

1MEG

R5

100k

C15

0.012µ

C11

4.7µ

DGND

I

2

C BUS DATA

R3

220

R2

220

2

1

12

C18

1µ

C19

4.7µ

V5

AC

S5

35

34

32

33

TANTALUM

R1

3.9k

37

C1

4.7µ

39

38

C5

4.7µ

C6

4.7µ

C7

4.7µ

V1

AC

43

47

C8

4.7µ

V2

AC

C3

4.7µ

V3

AC

C4

4.7µ

V4

AC

41

42

44

SIGNAL

GENERATOR

SIGNAL

GENERATOR

SIGNAL

GENERATOR

GND

9

– 15 –

CXA2094Q

Adjustment Method (Input signal level is the case when standard input signal is 245mVrms)

1. ATT adjustment

1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.

2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then, adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value (490mVrms).

3) Adjustment range: ±30% Adjustment bits: 4 bits

2. Separation adjustment

1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.

2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUT-R output to the minimum.

3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to reduce TVOUT-R output to the minimum.

4) The adjustments in 2 and 3 above are performed to optimize the separation.

5) “WIDEBAND” “SPECTRAL” Adjustment range: ±30% Adjustment range: ±15% Adjustment bits: 6 bits Adjustment bits: 6 bits

∗ Adjust this through Tuner and IF when this IC is mounted on the set.

– 16 –

CXA2094Q

Description of Operation

The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.

Fig. 1. Base band spectrum

Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)

Fig 3. dbx-TV block

PEAK DEV

kHz

50

25

L + R

50 – 15kHz

L-R

dbx-TV

NR

50

AM-DSB-SC

SAP

dbx-TV NR

FM 10kHz

50 – 10kHz

TELEMETRY

FM 3kHz

15

f

H = 15.734kHz

f

H 2fH 3fH 4fH 5fH 6fH 6.5fH

f

5

PILOT

3

(COMPIN)

STEREO LPF

PLL

(VCO 8f

H)

2f

HL0°

f

HL90°

f

HL0°

MODE CONTROL

PILOT

DET

MVCA

PILOT

CANCEL

MAIN LPF DE.EM

(MAIN OUT)

L + R

4.7µ

(MAIN IN)

L-R (DSB)

DET

INJ.

LOCK

SUBVCA

SUB LPF

WIDEBAND

(SUBOUT)

(ST IN)

4.7µ NR SW

dbx-TV

BLOCK

MATRIX

(Lch)

(Rch)

MODE

CONTROL

(SAP IN)

4.7µ

SAP(FM)

DET

SAP LPF

I C BUS DECODER MODE CONTROL

SAP BPF

(SAP OUT)

L – R

to TVSW

2

NOISE

DET

I C BUS DECODER

2

SAP DET

I

2

C BUS

DECODER

A B

25

22

12

4

3

23

27

40

(TVOUT-S)

LPF

38

39

4.7µ

(SOUT) (ESAPIN)

NR SW

FIXED

DEEMPHASIS

VARIABLE

DEEMPHASIS

(VE OUT) (VCA IN)

to MATRIX

4.7µ

HPF

LPF

RMS

DET

RMS

DET

VCA

A B

(ST IN)

(SAP IN)

35

34

23

27

– 17 –

CXA2094Q

Fig. 4. Switch block

(1) L + R (MAIN)

After the audio multiplexing signal input from COMPIN (Pin 12) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix.

(2) L – R (SUB)

The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA.

(3) SAP

SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 25 output is soft muted.

(4) Mode discrimination

Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal.

(5) dbx-TV block

Either the L – R signal or SAP signal input respectively from ST IN (Pin 23) or SAP IN (Pin 27) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix.

(Lch) (Rch)

(AUX1-L)

(AUX1-R)

from MATRIX

(TVOUT-L)

(TVOUT-R)

TVSW

(AUX2-L) (AUX2-R)

41

42

45

44

46

47

– 18 –

CXA2094Q

The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal.

(6) Matrix, TVSW

The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the mode control and whether there is ST / SAP discrimination. “TVSW” switches the “MATRIX” output signal, external input signal (input to AUX1-L, R (Pins 42 and

41)), external input signal (input to AUX2-L, R (Pins 45 and 44)) and external forced MONO.

(7) Others

“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 15) with GND become the reference current.

– 19 –

CXA2094Q

SPECTRAL (6)

WIDEBAND (6)

∗∗∗∗0000 ∗∗∗∗0001 ∗∗∗∗0010 ∗∗∗∗0011 ∗∗∗∗0100

∗ ∗ ∗ ∗ ∗

SLAVE RECEIVER

84H (1000 0100)

SLAVE TRANSMITTER

85H (1000 0101)

Register Specifications

Slave address

Register table

Status Registers

DATA

SUB ADDRESS MSB LSB

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

TEST-DA

TVSW

INSW

TEST1

EXT

SMD

NRSW

ATTSW

FOMO

FST

SAPC

FEXT1M1FEXT2

STA1

BIT7

POWER ON RESET

STA2

BIT6

STEREO

STA3

BIT5 SAP

STA4

BIT4

NOISE

STA5

BIT3

—

STA6

BIT2

—

STA7

BIT1

—

STA8

BIT0

—

ATT (4)

∗ : Don't Care

– 20 –

CXA2094Q

Description of Registers

Control registers

ATT SPECTRAL WIDEBAND

TEST-DA

TEST1 FST

NRSW FOMO

TVSW FEXT1

FEXT2 EXT

M1 SMD

ATTSW INSW

SAPC

Input level adjustment Adjustment of stereo separation (3kHz) Adjustment of stereo separation (300Hz) Turn to DAC test mode and VCO adjustment mode by means

of TEST-DA = 1. Turn to test mode by means of TEST = 1.

(Adjustment of FILTER) Turn to forced stereo by means of FST = 1. Selection of the output signal (Stereo mode, SAP mode) Turn to forced MONO by means of FOMO = 1.

(Left channel only is MONO during SAP output.) Selection of TV mode or external input mode for TVOUT

output External input 1 forced MONO (1: forced MONO ON) External input 2 forced MONO (1: forced MONO ON) Selection of external input 1 mode or external input 2 mode

for TVOUT output. (TVSW = 1) Selection of TVOUT mute ON/OFF

(0: mute ON, 1: mute OFF) Selection of L + R or additional SAP Turn the input stage MVCA off when ATTSW = 1. Selection of standard input level Selection of SAP mode or L + R mode according to the

presence of SAP broadcasting

Register

Contents

4 6 6

1

1 1

1

A A A

T

T T

U U

S S

S

9 1F 1F

0

— —

0

1

0

— —

—

Number of bits

Classification∗

1

Standard setting

∗1

Classification U: User control

A: Adjustment S: Proper to set T: Test

Status registers

PONRES STEREO SAP NOISE

1 1 1 1

POWER ON RESET detection; 1: RESET Stereo discrimination of the COMPIN input signal; 1: Stereo SAP discrimination of the COMPIN input signal; 1: SAP Noise level discrimination of the SAP signal; 1: Noise

Register Number of bits Contents

– 21 –

CXA2094Q

Description of Control Registers

ATT (4): Adjust the signal level input to COMPIN (Pin 12) to the standard input level.

Variable range of the input signal: standard input level –5.0dB to +3.0dB 0 = Level min. F = Level max.

SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.

0 = Level max. 3F = Level min.

WIDEBAND (6):Perform low frequency (fs = 300Hz) separation adjustment.

0 = Level min. 3F = Level max.

TEST-DA (1):Set DAC output test mode.

0 = Normal mode 1 = DAC output test mode In addition, the following output are present at Pin 47. TVOUT-L (Pin 47): DA control DC level

TEST1 (1): Monitor SAP BPF and NR BPF output.

0 = Normal mode 1 = SAP BPF and NR BPF output In addition, the following outputs are present at Pins 47 and 46. TVOUT-L (Pin 47): SAP BPF OUT TVOUT-R (Pin 46): NR BPF OUT

FST (1): Select forced STEREO mode

0 = Normal mode 1 = Forced stereo mode

NRSW (1): Select stereo mode or SAP mode

0 = Stereo mode 1 = SAP mode

– 22 –

CXA2094Q

FOMO (1): Select forced MONO mode

0 = Normal mode 1 = Forced MONO mode

FEXT1 (1): Turn external input [1] to forced MONO.

0 = Normal mode 1 = External input [1] is forced MONO.

Input the same signal to both AUX1-L and AUX1-R.

FEXT2 (1): Turn external input [2] to forced MONO

0 = Normal mode 1 = External input [2] is forced MONO Input the same signal to both AUX2-L and AUX2-R.

TVSW (1): Select TV mode or external input mode for TVOUT output.

0 = TV mode 1 = External input mode

EXT (1): Select external input [1] mode or external input [2] mode for TVOUT output. (TVSW = 1)

0 = External input [1] mode 1 = External input [2] mode

M1 (1): Mute the TVOUT-L and TVOUT-R output.

0 = Mute ON 1 = Mute OFF

SMD (1): Select L + R or additional SAP signal

0 = L + R output is selected 1 = additional SAP output is selected

ATTSW (1): Select BYPASS SW of MVCA

0 = Normal mode 1 = MVCA is passed

INSW (1): Select standard input level of COMPIN (Pin 12)

0 = 245mVrms 1 = 100mVrms

SAPC (1): Select the SAP signal output mode

When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected

– 23 –

CXA2094Q

Description of Mode Control

Priority ranking: M1 > TVSW/EXT > (NRSW & FOMO & SAPC)

NRSW

FOMO

SAPC

M1

TVSW/EXT

“Select dbx input and TV decoder output” Conditions: FOMO = 0

NRSW = 0 (MONO or ST output)

• During ST input: left channel: L, right channel: R

• During other input: left channel: L + R, right channel: L + R

NRSW = 1 (SAP output)

• When there is “SAP” during SAP

discrimination – left channel: SAP, right channel: SAP

• When there is “No SAP”, output is the

same as when NRSW = 0.

“Select dbx input and TV decoder output” Conditions: FOMO = 0

NRSW = 0 (MONO or ST output) As on the left

NRSW = 1 (SAP output)

• Regardless of the presence of SAP discrimination, dbx input: “SAP” left channel: SAP, right channel: SAP

However, when there is no SAP, SAPOUT output is soft muted (–7dB)

Mode control SAPC = 0 SAPC = 1

“Forced MONO”

FOMO = 1

• During SAP output: left channel: L + R, right channel: SAP

• During ST or MONO output: left channel: L + R, right channel: L + R Change the selection conditions for “MONO or ST output” and “SAP output”.

SAPC = 0: Switch to SAP output when there is SAP discrimination.

Do not switch to SAP output when there is no SAP discrimination.

SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.

“MUTE”

M1 = 0: TVOUT-L, R, S output is muted.

“TV mode/external input mode selection”

TVSW = 0: Set TVOUT-L, R output to TV mode. TVSW = 1: Set TVOUT-L, R output to external input mode. EXT = 0: Set TVOUT-L, R output to external input [1] mode. (TVSW = 1) EXT = 1: Set TVOUT-L, R output to external input [2] mode. (TVSW = 1)

– 24 –

CXA2094Q

Decoder Output and Mode Control Table 1 (SAPC = 1)

Note

(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).

The signal is soft muted when NOISE = 1.

∗ : Don’t care. ∗1

SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

0 0 0 0 ∗ 1 MUTE L + R L + R 0 0 0 1 0 1 SAP SAP SAP

MONO

0 0 0 1 1 1 SAP L + R SAP 0 ∗ 1 0 ∗ 1 MUTE L + R L + R 0 ∗ 1 1 0 1 (SAP) (SAP) (SAP) 0 ∗ 1 1 1 1 (SAP) L + R (SAP) 1 0 ∗ 0 0 1 L – R L R 1 0 ∗ 0 1 1 MUTE L + R L + R 1 1 1 0 0 1 L – R L R

STEREO

1 1 1 0 1 1 MUTE L + R L + R 1 0 0 1 0 1 SAP SAP SAP 1 0 0 1 1 1 SAP L + R SAP 1 ∗ 1 1 0 1 (SAP) (SAP) (SAP) 1 ∗ 1 1 1 1 (SAP) L + R (SAP) 0 1 ∗ 0 0 1 MUTE L + R L + R 0 1 ∗ 0 1 1 MUTE L + R L + R

MONO & SAP

0 1 0 1 0 1 SAP SAP SAP 0 1 0 1 1 1 SAP L + R SAP 0 1 1 1 0 1 (SAP) (SAP) (SAP) 0 1 1 1 1 1 (SAP) L + R (SAP) 1 1 ∗ 0 0 1 L – R L R 1 1 ∗ 0 1 1 MUTE L + R L + R

STEREO & SAP

1 1 0 1 0 1 SAP SAP SAP 1 1 0 1 1 1 SAP L + R SAP 1 1 1 1 0 1 (SAP) (SAP) (SAP) 1 1 1 1 1 1 (SAP) L + R (SAP)

Input signal mode

Mode detection

Mode control

dbx input

Output

ST SAP NOISE NRSW FOMO SAPC Lch Rch

∗1

– 25 –

CXA2094Q

Decoder Output and Mode Control Table 2 (SAPC = 0)

0 0 ∗ ∗ ∗ 0 MUTE L + R L + R 0 1 1 0 0 0 MUTE L + R L + R

MONO 0 1 1 0 1 0 MUTE L + R L + R

0 1 1 1 0 0 (SAP) (SAP) (SAP) 0 1 1 1 1 0 (SAP) L + R (SAP) 1 0 ∗ 0 0 0 L – R L R 1 0 ∗ 0 1 0 MUTE L + R L + R 1 0 ∗ 1 0 0 L – R L R

STEREO

1 0 ∗ 1 1 0 MUTE L + R L + R 1 1 1 0 0 0 L – R L R 1 1 1 0 1 0 MUTE L + R L + R 1 1 1 1 0 0 (SAP) (SAP) (SAP) 1 1 1 1 1 0 (SAP) L + R (SAP) 0 1 0 0 0 0 MUTE L + R L + R 0 1 0 0 1 0 MUTE L + R L + R 0 1 0 1 0 0 SAP SAP SAP

MONO & SAP

0 1 0 1 1 0 SAP L + R SAP 0 1 1 0 0 0 MUTE L + R L + R 0 1 1 0 1 0 MUTE L + R L + R 0 1 1 1 0 0 (SAP) (SAP) (SAP) 0 1 1 1 1 0 (SAP) L + R (SAP) 1 1 0 0 0 0 L – R L R 1 1 0 0 1 0 MUTE L + R L + R 1 1 0 1 0 0 SAP SAP SAP

STEREO & SAP

1 1 0 1 1 0 SAP L + R SAP 1 1 1 0 0 0 L – R L R 1 1 1 0 1 0 MUTE L + R L + R 1 1 1 1 0 0 (SAP) (SAP) (SAP) 1 1 1 1 1 0 (SAP) L + R (SAP)

Input signal mode

Mode detection

Mode control

dbx input

Output

ST SAP NOISE NRSW FOMO SAPC Lch Rch

∗1

Note

(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).

The signal is soft muted when NOISE = 1.

∗ : Don’t care. ∗1

SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

– 26 –

CXA2094Q

Mode Control Table 3

TV (L) / TV (R) are selected in MATRIX

TV (L): MONO, ST-L, SAP, (SAPBPFout, D/Aout) TV (R): MONO, ST-R, SAP, (NRBPFout, STVCO freerun (4fH))

TVSW

—

0 1 1 1 1

FEXT2

— — — —

0 1

FEXT1

— —

0

1 — —

EXT

— —

0 0 1 1

M1

0 1 1 1 1 1

1 2 3 4 5 6

TVOUT-L

MUTE

TV (L) AUX1-L AUX1-L AUX2-L AUX2-L

TVOUT-R

MUTE

TV (R)

AUX1-R

AUX1-L

AUX2-R

AUX2-L

I2C BUS block items (SDA, SCL)

I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V)

Load capacity 200pF (Connect to GND)

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 48) during 3mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation

VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSU: DAT tR tF tSU: STO

3.0 0

— —

0 3

—

0

4.7

4.0

4.7

4.0

4.7 0

250

— —

4.7

— — — — — — — — — — — — — — — — — —

5.0

1.5 10 10

0.4

—

10

100

— — — — — — —

1

300

—

V

µA

V

mA

pF

kHz

µs

ns µs ns µs

No. Item Symbol Min. Typ. Max. Unit

– 27 –

CXA2094Q

SDA

SCL

Start Condition S Stop Condition P

H L HIZ L

I2C BUS Signal

There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.

• Accordingly there are 3 values outputs, H, L and HIZ.

• I2C transfer begins with Start Condition and ends with Stop Condition.

SDA

SCL

tBUF

P

S

t

HD: STA

t

LOW

tHD: DAT

t

HIGH

tR

tF

tHD: STA

tSU: STA

Sr

t

SU: STO

P

tSU: DAT

I2C BUS Control Signal

– 28 –

CXA2094Q

• I2C data Write (Write from I2C controller to the IC)

∗

Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically.

• I2C data Read (Read from the IC to I2C controller)

• Read timing

∗

Data Read is performed during SCL rise.

S

Address

1 6 7 8 9 1 8 9

SCL

ACK DATA ACK

SDA

H during Read

HIZ

7

P

DATA

1 2 3 4 5 6 7 89 9

IC output SDA

SCL

MSB

LSB

ACK ACK

Read timing

ACKACKDATA DATA

P

8 9 1 8 9

HIZ HIZ

DATA (n) DATA (n + 1)ACK

1 8 9 1 8 9

ACK DATA (n + 2)

HIZ HIZ

LSBMSB

S

Address

1 2 3 4 5 6 7 8 9 1 8 9

SDA

SCL

MSB

L during Write

MSB LSB

HIZ HIZ

ACK Sub Address ACK

– 29 –

CXA2094Q

Input level vs. Distortion characteristics 1 (MONO)

Distortion [%]

1.0

0.1

–10 0 10

Input level vs. Distortion characteristics 2 (Stereo)

Distortion [%]

10

1.0

–10 0 10

Input level [dB]

Input signal: Stereo L = –R (dbx-TVNR ON), 1kHz 0dB = 100% modulation level V

CC = 9V, 30kHz using LPF, ST mode

Measurement point: TVOUT-L/R

Input level vs. Distortion characteristics 3 (SAP)

Distortion [%]

10

1.0

–10 0 10

Input level [dB]

Standard level (100%)

Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB = 100% modulation level V

CC = 9V, 30kHz using LPF, SAP mode

Measurement point: TVOUT-L/R

Standard level (100%)

Input signal: MONO (Pre-emphasis on), 1kHz 0dB = 100% modulation level V

CC = 9V, 30kHz using LPF

Measurement point: TVOUT-L/R

– 30 –

CXA2094Q

Frequency [kHz]

Gain [dB]

Stereo LPF frequency characteristics

10

5

0

–5

–10

0 20 40 60 80 100

30

10

0

–20

–50

1 2 5 10 20 50

7 70 100

–40

–30

–10

20

Gain (FC main and FC sub) [dB]

Frequency [kHz]

Main LPF and Sub LPF frequency characteristics

10

0

–20

20 40 60 80 100 120

–10

20

SAP frequency characteristics and group delay

Group delay [µs]

100

90 80 70 60 50 40

10

20

0

30

5fH

Gain

Group delay

3.8fH

6.2fH

Frequency [kHz]

Gain [dB]

Frequency [kHz]

Additional SAP frequency characteristics

Output level [mVrms]

500

100

10

1.0 10

100% modulation

30% modulation

10% modulation

1% modulation

0.1

– 31 –

CXA2094Q

Package Outline Unit: mm

SONY CODE EIAJ CODE JEDEC CODE

M

PACKAGE STRUCTURE

PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN SOLDER / PALLADIUM

PLATING COPPER / 42 ALLOY

48PIN QFP (PLASTIC)

15.3 ± 0.4

12.0 – 0.1

+ 0.4

0.8 0.3 – 0.1

+ 0.15

± 0.12

13

24

2536

37

48

1 12

2.2 – 0.15

+ 0.35

0.9 ± 0.2

0.1 – 0.1

+ 0.2

13.5

0.15

0.15 – 0.05

+ 0.1

QFP-48P-L04 ∗QFP048-P-1212-B

0.7g

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).