Datasheet CXA2054S Datasheet (Sony)

—1—

E96Y15B86-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

US Audio Multiplexing Decoder

48 pin SDIP (Plastic)

CXA2054S

Absolute Maximum Ratings (Ta=25 °C)

• Supply voltage VCC 11 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 2.2 W

Range of Operating Supply Voltage

9±0.5 V

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

Description

The CXA2054S is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built in while adjustment, mode control and sound processor control are all executed through I2C BUS.

Features

• Audio multiplexing decoder, dbx noise reduction

decoder and sound processor (surround, volume

limiter, bass · treble, volume) are all included in a

single chip. Almost any sort of signal processing is

possible through this IC.

• All adjustments are possible through I2C BUS to

allow for automatic adjustment.

• Various built-in filter circuits greatly reduce external

parts.

• There are two channel external inputs for LSOUT

outputs.

• Automatic volume control between input sources is

possible through volume limiter.

Standard I/O Level

• Input level

COMPIN (Pin 19) 245 mVrms

AUX1-L/R (Pins 40 and 39) 490 mVrms

AUX2-L/R (Pins 42 and 41) 490 mVrms

SURRIN (Pin 4) 490 mVrms

Pin Configuration (Top View)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

38 37 36 35 34 33 32 31 30 29 28 27 26 2548 46 45 44 43 42 41 40 3947

BASSL2

TRER

TREL

SURRIN

SURROUT

LSOUT-R

LSOUT-L

NC

SDA

SCL

DGND

SAD

MAININ

MAINOUT

NC

PCINT1

PCINT2

PLINT

COMPIN

VGR

IREF

GND

SAPTC

V

CC

BASSL1

BASSR2

BASSR1

SURRTC

TVOUT-L

TVOUT-R

AUX2-L

AUX2-R

AUX1-L

AUX1-R

VLTC

VLDC

VCAWGT

VCATC

VCAIN

VEOUT

VETC

VEWGT

VE

SAPIN

SAPOUT

NOISETC

STIN

SUBOUT

• Output level TVOUT-L/R (Pins 44 and 43) 490 mVrms LSOUT-L/R (Pins 7 and 6) 490 mVrms SURROUT (Pin 5) 490 mVrms

∗A license of the dbx-TV noise reduction system is required for the use this device.

—2—

CXA2054S

1/4 1/2

STLPF

“FILTER”

VCA

VCA LPF DeEm LPF

WIDEBAND

LFLT VCO

STIND

FLT LPF

“STEREO”

(+6dB)

ATT

BPF

SAPVCO

LPF

NOISE

DET

“NOISE”

“SAP”

SAPIND

19

22

24

27

23

VCO

FILTER

COMPIN

V

CC

GND

NOISETC

SAPTC

IREF

I

2

C BUS I/F

“PONRES”

LOGIC

NRSW/FOMO/SAPC

LPF LPF

SW

DeEm VE

RMSDETHPF

AMP

(+4dB)

SPECTRAL

VCA

RMSDET

MATRIX

SW1

16 17 25 1418 13 40 39

SW2

VOLLIM

PREVOL

SURROUND

PR-VOLSURR

BASS

TREB

TREBLE

VOL-L

VOL-R

VOL-S

MATRIX

SW3

VOL-SURR

(L-R)

44

43

42

41

37

38

45

1

46

47

3482

4

SURRSW

TVOUT-L

TVOUT-R

AUX2-L

AUX2-R

VLDC

VLTC

SURRTC

BASSL1

BASSL2

BASSR1

BASSR2

TREL

TRER

SURRIN

VOL-RVOL-L

VGR

IREF

SAD

DGND

SCL

SDA

SAPOUT

SAPIN

STIN

VE

VEWGT

VETC

VEOUT

VCAIN

VCAWGT

VCATC

LSOUT-R

LSOUT-L

SURROUT

20 21 12 11 10

9

28 29 26 30 33 34 3631 32 35

7 6 5

PCINT1

PCINT2

SUBOUT

MAINOUT

PLINT

MAININ

AUX1-L

AUX1-R

FEXT1

EXT1/EXT2/M1

VL

FEXT2

M2

Block Diagram

—3—

CXA2054S

Pin Description (Ta=25 °C, VCC=9 V)

Symbol

Equivalent circuit Description

No. voltage

1

48

47

46

2

3

4

BASSL2

BASSL1

BASSR2

BASSR1

TRER

TREL

SURRIN

4.0 V

48

47

1

13.2k

10.7k

8.57k

6.89k

5.66k

4.44k

3.67k

15.3k

46

4V

3k

VCC

580

V

CC

3

2

VCC

4.2k

3.42k

2.73k

2.2k

1.8k

1.42k

1.17k

4.88k

580

VCC

3k

10k

4

VCC

20k 20k

27.5k

47k

4V

BASS filter pin. (Left channel) (Connect a 15 nF capacitor between Pins 1 and 48.) The cutoff frequency is determined by the built-in resistor and the external capacitance.

BASS filter pin. (Right channel) (Connect a 15 nF capacitor between Pins 47 and 46.) The cutoff frequency is determined by the built-in resistor and the external capacitance.

TREBLE filter pin. (Right channel) (Connect a 6.8 nF capacitor between this pin and GND.)

TREBLE filter pin. (Left channel) (Connect a 6.8 nF capacitor between this pin and GND.)

Surround external input pin.

—4—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

5

6

7

8

9

10

11

SURROUT

LSOUT-R

LSOUT-L

NC

SDA

SCL

DGND

4.0 V

—

6 7

5

VCC

580

7.5k

×2

4.5k

×5

9

4k

3k

2.1V

↓ 35µ

7.5k

V

CC

10.5k

×4

4k

3k

2.1V

↓ 35µ

7.5k

V

CC

10

(L-R) signal output pin.

LSOUT right channel output pin.

LSOUT left channel output pin.

—

Serial data I/O pin. VIH > 3.0 V VIL < 1.5 V

Serial clock input pin. VIH > 3.0 V VIL < 1.5 V

Digital block GND.

8

11

—5—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

12

13

14

15

16

17

SAD

MAININ

MAINOUT

NC

PCINT1

PCINT2

—

4.0 V

—

4.0 V

12

80k

10k

40k

2V

V

CC

13

4V

53k

147

10k

V

CC

VCC

14

VCC

147

V

CC

×4

15k

1k

↓

200µ

16

147

30k

22k

VCC

17

147

4k

V

CC

2k

10k 10k

×2

Slave address control switch. The slave address is selected by changing the voltage applied to this pin.

Input the (L+R) signal from MAINOUT (Pin 14).

(L+R) signal output pin.

—

Stereo block PLL loop filter integrating pin.

15

—6—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

18

19

20

21

PLINT

COMPIN

VGR

IREF

5.1 V

4.0 V

1.3 V

15k 15k

20k 20k

20k 10k

↓

26µ

↓

50µ

147

18

VCC

147

19

3k

50k

16k4k

VCC

9.7k 19.4k

2.06k

×4

20

3k 147

VCC

11k

40k 40k

30p1.8k

16k

30k 30k

21

147

VCC

Pilot cancel circuit loop filter integrating pin. (Connect a 1 µF capacitor between this pin and GND.)

Audio multiplexing signal input pin.

Band gap reference output pin. (Connect a 10 µF capacitor between this pin and GND.)

Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62 kΩ (±1 %) resistor between this pin and GND.)

—7—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

22

23

24

25

26

29

GND

SAPTC

VCC

SUBOUT

STIN

SAPIN

—

4.5 V

—

4.0 V

22

24

8k

VCC

23

10k

1k

3k

VCC

4k ↓ 50µ

2k

2k 2k

2k

4k

14.4k

580

10P

4k

1k

147

25

VCC

26

147

18k

4V

23k

11.7k

20k

23k

4V

147

29

VCC

18k

Analog block GND.

Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.)

Supply voltage pin.

(L-R) signal output pin.

Input the (L-R) signal from SUBOUT (Pin 25).

Input the (SAP) signal from SAPOUT (Pin 28).

—8—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

27

28

30

31

NOISETC

SAPOUT

VE

VEWGT

3.0 V

4.0 V

8k

×2

2k

10k

1k

27

3k

200k

V

CC 3k

4k

4V

3.3k

VCC

24k ↓ 10µ

5P

4k ↓ 50µ

580

580 10k

147

28

V

CC

30

147

7.5k

VCC

31

147

580

8k

30k ↓ 8µ

4V

36k

2.9V

4k ↓ 50µ

V

CC

Set the time constant for the noise detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.)

SAP FM detector output pin.

Variable de-emphasis integrating pin. (Connect a 2700 pF capacitor and a 3.3 kΩ resistor in series between this pin and GND.)

Weight the variable deemphasis control effective value detection circuit. (Connect a 0.047 µF capacitor and a 3 kΩ resistor in series between this pin and GND.)

—9—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

32

33

34

35

VETC

VEOUT

VCAIN

VCATC

1.7 V

4.0 V

1.7 V

4k

↓ 50µ

×4

20k ↓ 7.5µ

32

VCC

33

VCC

580

10k

5P

VCC

47k 47k

34

20k

VCC

35

VCC

↓

50µ

4k

×4

20k

↓

7.5µ

Determine the restoration time constant of the variable deemphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3 µF capacitor between this pin and GND.)

Variable de-emphasis output pin. (Connect a 4.7 µF non-polar capacitor between Pins 33 and 34.)

VCA input pin. Input the variable deemphasis output signal from Pin 33 via a coupling capacitor.

Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10 µF capacitor between this pin and GND.)

—10—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

36

37

38

39

40

41

42

VCAWGT

VLDC

VLTC

AUX1-R

AUX1-L

AUX2-R

AUX2-L

4.0 V

0.7 V

4.0 V

40k 40k

30k

36k

2.9V

4k

↓

50µ

↓

8µ

8k

3P

580

147

36

VCC

147

3k

37

VCC

147

38

200 200

100k 100k

10k

20k 20k

27.5k

47k

4V

39 40 41 42

V

CC

Weight the VCA control effective value detection circuit. (Connect a 1 µF capacitor and a 3.9 kΩ resistor in series between this pin and GND.)

Volume limiter detection circuit bias pin. (Connect a 1 MΩ resistor between pins 37 and 38.)

Set the time constant for the volume limiter detection circuit.

Right channel external input 1 pin.

Left channel external input 1 pin.

Right channel external input 2 pin.

Left channel external input 2 pin.

—11—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

43

44

45

TVOUT-R

TVOUT-L

SURRTC

4.0 V

44

43

580

3k

VCC

147

10k

20k

45

20k

24k

580

40k

V

CC

VCC

TVOUT right channel output pin.

TVOUT left channel output pin.

Set the central frequency of the SURROUND circuit phase shifter. The frequency is determined by the built-in resistor and the external capacitance. (Connect a 0.022 µF capacitor between this pin and GND.)

—12—

CXA2054S

Electrical Characteristics

COMP IN input level

(100 % modulation level)

(Ta=25 °C, VCC=9 V)

Main (L+R) (Pre-Emphasis : OFF)

SUB (L–R) (dbX-TV : OFF)

Pilot

SAP Carrier

f

H

=245 mVrms

=490 mVrms

=49 mVrms

=147 mVrms

=15.734 kHz

No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Item

Current consumption

Main output level

Main de-emphasis frequency

characteristic

Main LPF frequency

characteristic

Main distortion

Main overload distortion

Main S/N

Sub output level

Sub LPF frequency

characteristic

Sub distortion

Sub overload distortion

Sub S/N

ST

→

SAP

Cross talk

Sub pilot leak

Symbol

I

CC

Vmain

FCdeem

FCmain

THDm

THDmmax

SNmain

Vsub

FCsub

THDsub

THDsmax

SNsub

CTst

PCsub

Mode

MONO

ST

SAP

ST

Input pin

19

Input signal

No signal

Mono 1 kHz 100 % mod.

Pre-em. on

Mono 5 kHz 30 % mod.

Pre-em. on

Mono 12 kHz 30 % mod.

Pre-em.on

Mono 1 kHz 100 % mod.

Pre-em. on

Mono 1 kHz 200 % mod.

Pre-em off

Mono 1 kHz,

Pre-em on

SUB (L-R), 1 kHz,

100 % mod., NR OFF

SUB (L-R) 12 kHz,

30 % mod., NR OFF

SUB (L-R) 1 kHz,

100 % mod., NR OFF

SUB (L-R), 1 kHz,

200 % mod., NR OFF

SUB (L-R) 1 kHz,

NR OFF

SUB (L-R) 1 kHz,

100 % mod., NR ON

SAP Carrier (5 f

H

)

PILOT (f

H

) 0 dB

Measurement

conditions

20 log ('5 k'/'1 k')

20 log

('12 k'/'1 k')

20 log

('100 %'/'0 %')

20 log

('12 k'/'1 k')

20 log

('100 %'/'0 %')

20 log

('NRSW=0'/

'NRSW=1')

20 log

('out'/'in')

Filter

15 kLPF

1 kBPF

f

H

BPF

Output

43/44

25

44

25

Min.

37

440

–1.2

–3.0

—

61

150

–3.0

—

56

60

—

Typ.

47

490

0

–1.0

0.1

0.15

69

190

–0.5

0.1

0.2

64

70

–42

Max.

57

540

1.0

0.5

—

230

1.0

2.0

—

–30

Unit

mA

mVrms

dB

%

dB

mVrms

dB

%

dB

—13—

CXA2054S

No.

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Item

Stereo ON level

Stereo ON/OFF hysteresis

SAP output level

SAP LPF frequency

characteristic

SAP distortion

SAP S/N

SAP soft mute

dbx out noise level

SAP

→

ST

Cross talk

SAP ON level

SAP ON/OFF hysteresis

ST separation 1 L

→

R

ST separation 1 R

→

L

ST separation 2 L

→

R

ST separation 2 R

→

L

TVOUT output level

Symbol

THst

HYst

Vsap1

Vsap2

FCsap

THDsap1

THDsap2

SNsap

Smute

Ndbx

CTsap

THsap

HYsap

STLsep1

STRsep1

STLsep2

STRsep2

Vtv

Mode

ST

SAP

ST

SAP

ST

EXT

Input pin

19

—

19

39/40

Input signal

Change

PILOT (f

H

) Level

SAP 1 kHz 100 % mod.

NR OFF

SAP 1 kHz 100 % mod.

NR ON

SAP 10 kHz, 30 % mod.

NR OFF

SAP 1 kHz 100 % mod.

NR OFF

SAP 1 kHz 100 % mod.

NR ON

SAP 1 kHz, NR OFF

SAP 1 kHz, 100 % mod.

NR OFF

No signal

SAP 1 kHz, 100 % mod.

NR ON, Pilot (f

H

)

Change

SAP Carrier (5 f

H

) Level

ST-L 300 Hz 30 % mod.

NR ON

ST-R 300 Hz 30 % mod.

NR ON

ST-L 3 kHz 30 % mod.

NR ON

ST-R 3 kHz 30 % mod.

NR ON

Sine wave 1 kHz,

490 mVrms

Measurement

conditions

0 dB=49 mVrms

20 log (‘on

level’/’off level’)

20 log

('10 k'/'1 k')

20 log

('100 %'/'0 %')

20 log (‘NRSW=1’

/‘NRSW=0’)

0 dB=147 mVrms

20 log (‘on

level’/’off level’)

20 log

(‘Lch’/‘Rch’)

20 log

(‘Rch’/‘Lch’)

20 log

(‘Lch’/‘Rch’)

20 log

(‘Rch’/‘Lch’)

0 dB=490 mVrms

Filter

15 kLPF

1 kBPF

15 kLPF

Output

BUS

RETURN

28

43/44

28

43/44

28

43/44

44

BUS

RETURN

43/44

Min.

–9.0

2.0

150

370

–3.0

—

46

–8.5

—

60

–12.0

2.0

23

–0.5

Typ.

–6.0

6.0

190

490

0

2.5

0.6

55

–7.0

–75

70

–9.0

4.0

35

0

Max.

–3.0

10.0

230

610

2.5

6.0

1.5

—

–5.5

–54

—

–6.5

6.0

—

0.5

Unit

dB

mVrms

dB

%

dB

dBm

dB

—14—

CXA2054S

No.

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Item

TVOUT

cross talk

TVOUT

muted amount

TVOUT DC offset

TVOUT distortion

TVOUT S/N

TVOUT overload distortion

LSOUT output level

LSOUT cross talk

LSOUT muted amount

LSOUT DC offset

LSOUT distortion

LSOUT S/N

LSOUT overload distortion

BASS maximum value

BASS minimum value

Symbol

CTtv1

CTtv2

MUtv1

MUtv2

OStv

THDtv

SNtv

THDtvmax

Vls1

Vls2

CTls1

CTls2

MUls

OSls

THDls

SNls

THDlsmax

TBmax

TBmin

Mode

INT

EXT

INT

EXT

INT

EXT

INT

EXT

INT

EXT

INT

EXT

Input pin

39/40

19

39/40

—

39/40

19

39/40

41/42

39/40

41/421939/40

41/42—39/40

41/42

39/40

41/42

39/40

41/42

39/40

41/42

39/40

41/42

Input signal

Sine wave 1 kHz,

490 mVrms

MONO 1 kHz, 100 %,

mod. Pre-em. on

MONO 1 kHz, 100 %,

mod. Pre-em. on

Sine wave 1 kHz,

490 mVrms

No signal

Sine wave 1 kHz,

490 mVrms

Sine wave 1 kHz,

490 mVrms/No signal

Sine wave 1 kHz,

2 Vrms

MONO 1 kHz, 100 %,

mod. Pre-em. on

Sine wave 1 kHz,

490 mVrms

Sine wave 1 kHz,

490 mVrms

MONO 1 kHz, 100 %,

mod. Pre-em. on

Sine wave 1 kHz,

490 mVrms

No signal

Sine wave 1 kHz,

490 mVrms

Sine wave 1 kHz,

490 mVrms

Sine wave 1 kHz,

2 Vrms

Sine wave 100 Hz,

245 mVrms

Sine wave 100 Hz,

245 mVrms

Measurement

conditions

0 dB=490 mVrms

EXT

→

INT

0 dB=490 mVrms

INT

→

EXT

20 log (M1="0"/M1="1")

0 dB=490 mVrms

20 log (M1="0"/M1="1")

0 dB=490 mVrms

Mute (M1=0)/DC difference

when there is no signal

20 log ('490 mVrms'/'No

signal')

0 dB=490 mVrms

EXT

→

INT

0 dB=490 mVrms

INT

→

EXT

20 log (M2="0"/M2="1")

0 dB=490 mVrms

Mute (M2=0)/DC difference

when there is no signal

20 log ('490 mVrms'/'No

signal')

BASS="F"

0 dB=245 mVrms

BASS="0"

0 dB=245 mVrms

Filter

1 kBPF

15 kLPF

1 kBPF

15 kLPF

Output

43/44

6/7

Min.

—

–25

—

75

—

–0.9

—

–25

—

75

—

11

–13

Typ.

–75

–90

–85

–90

0

0.01

88

0.1

0

–75

–90

0

0.01

88

0.1

12

–12

Max.

–60

–80

–70

–75

25

0.5

—

1.0

0.9

–60

–80

–75

25

0.5

—

1.0

13

–11

Unit

dB

mV

%

dB

%

dB

mV

%

dB

%

dB

—15—

CXA2054S

No.

51

52

53

54

55

56

57

58

59

60

Item

TREBLE maximum value

TREBLE minimum value

Volume minimum value

SURROUT volume

minimum value

SURROUND frequency

characteristic 1

SURROUND frequency

characteristic 2

VL limit level 1

VL limit level 2

TVOUT overload leak

LSOUT

overload leak

SURROUT

Symbol

TTmax

TTmin

VOLmin

SVOLmin

Sr1

Sr2

VL1

VL2

Oltv

Olls

Mode

EXT

INT

Input pin

39/40

41/42

39/40

41/42

39/40

41/42

39/40

41/42

40/42

39/40

41/42

39/40

41/42

19

Input signal

Sine wave 10 kHz,

245 mVrms

Sine wave 10 kHz,

245 mVrms

Sine wave 1 kHz,

490 mVrms

Sine wave 1 kHz,

490 mVrms

Sine wave 330 Hz,

490 mVrms

Sine wave 10 kHz,

490 mVrms

Sine wave 1 kHz,

220 mVrms

Sine wave 1 kHz,

1 Vrms

Sine wave 1 kHz,

9 Vp-p

Sine wave 1 kHz,

9 Vp-p

Measurement

conditions

TREBLE="F"

0 dB=245 mVrms

TREBLE="0"

0 dB=245 mVrms

VOL-L="0", VOL-R="0"

0 dB=490 mVrms

VOL-SURR="0"

0 dB=490 mVrms

SURR="1"

0 dB=490 mVrms

SURR="1"

0 dB=490 mVrms

VL=“1”

M1=M2=“0”

VOL-L=VOL-R=

VOL-SURR=“0”

Filter

1 kBPF

Output

6/7

5

7

6/7

43/44

5/6/7

Min.

11

–13

—

1.3

4.5

175

200

—

Typ.

12

–12

–90

3.0

6.0

220

250

0.04

Max.

13

–11

–75

4.6

7.5

265

300

0.2

Unit

dB

mVrms

—16—

CXA2054S

I2C BUS block items (SDA, SCL)

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 9) during 3 mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation

Symbol

VIH

VIL

IIH

IIL

VOL

IOL

CI fSCL tBUF

tHD : STA

tLOW

tHIGH tSU : STA tHD : DAT tSU : DAT

tR tF

tSU : STO

Min.

3.0 0

— —

0 3

—

0

4.7

4.0

4.7

4.0

4.7 0

250

— —

4.7

Typ.

— — — — — — — — — — — — — — — — — —

Max.

5.0

1.5 10 10

0.4

—

10

100

— — — — — — —

1

300

—

Unit

V

µA

V

mA

pF

kHz

µs

ns µs ns µs

I2C BUS load conditions : Pull-up resistor 4 kΩ (Connect to +5 V)

Load capacity 200 pF (Connect to GND)

I2C BUS Control Signal

SDA

SCL

tBUF

P S

t

R

tHD;STA

t

LOW

tHD;DAT

t

HIGH

tSU;DAT

t

SU;STA

Sr

t

HD;STA

t

SU;STO

P

t

F

—17—

CXA2054S

BASSL2

TRER

TREL

SURRIN

SURROUT

LSOUT-R

LSOUT-L

NC

SDA

SCL

DGND

SAD

MAININ

MAINOUT

NC

PCINT1

PCINT2

PLINT

COMPIN

VGR

IREF

GND

SAPTC

V

CC

BASSL1

BASSR2

BASSR1

SURRTC

TVOUT-L

TVOUT-R

AUX2-L

AUX2-R

AUX1-L

AUX1-R

VLTC

VLDC

VCAWGT

VCATC

VCAIN

VEOUT

VETC

VEWGT

VE

SAPIN

SAPOUT

NOISETC

STIN

SUBOUT

C1

15n

C3

15n

C6

0.022µ

4.7µ

C7

4.7µ

C9

4.7µ

C11

V2

AC

4.7µ

C13

V3

AC

4.7µ

C14

V4

AC

S3

S4

4.7µ

C15

V5

AC

SIGNAL

GENERATOR

SIGNAL

GENERATOR

SIGNAL

GENERATOR

SIGNAL

GENERATOR

4.7µ

C16

R3

1MEG

1µ

C17R43.9k

10µ

C19

C20

4.7µ

TANTALUM

3.3µC23

TANTALUM

0.047µ

C25

R7

3k

2700P

C27

R8

3.3k

S2

S1

C29

4.7µ

C30

C32

4.7µ

38 37 36 35 34 33 32 31 30 29 28 27 26 2548 46 45 44 43 42 41 40 3947

FILTERS MEASURES

S5

S6

S7

BUFF

15kHz LPF

fHBPF

1kHz BPF

6.8n

C4

C18

4.7µ

R6

1MEG

C21

5600p

R5

C22

100k 0.012µ

4.7µ

C8

6.8n

C2

4.7µ

C10

4.7µ C12

4.7µ

C5

V1

AC

SIGNAL

GENERATOR

R1

220

R2

220

GND GND

I

2

C BUS DATA

1µ

C24

V1

AC

SIGNAL

GENERATOR

GND

4.7µ C26

10µ C28

R9

62k

GND

METAL ±1%

4.7µ C31

100µ

C33

GND

A

VCC

V7

9V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Electrical Characteristics Measurement Circuit

—18—

CXA2054S

I2C BUS Register Data Standard Setting Values

Register

ATT VCO FILTER SPECTRAL WIDEBAND TEST-DA TEST1 FST PR-VOL VOL-L VOL-R VOL-SURR TREBLE BASS NRSW FOMO FEXT1 FEXT2 VL SURR SURRSW EXT1 EXT2 M1 M2 ATTSW SAPC

Number

of bit

4 6 6 6 6 1 1 1 4 6 6 6 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1

Classifi-

cation

A A A A A

T T

T U U U U U U U U U U U U U U U U U S S

Standard

setting

9 1 F 1 F 1 F 1 F

0

F 3 F 3 F 3 F

8

— —

0

1

— —

Contents

Center point

Normal mode

F=0 dB 3 F=0 dB 3 F=0 dB 3 F=0 dB 7 or 8=0 dB 7 or 8=0 dB

According to the modecontrol table AUX1 forced MONO OFF

AUX2 forced MONO OFF VL OFF Surround OFF Internal mode selection

TV decoder output selection

Mute OFF

Fixed by the set specifications

Setting value when electrical characteristics are measured

Adjustment point

Classification A : Adjustment

U : User control S : Proper to set T : Test

—19—

CXA2054S

List of Adjustment Contents

1

2

3

4

Adjustment

item

MAIN VCA

ST & SAP VCO ST & SAP & dbx FILTER Low frequency ST separation High frequency ST separation

Adjustment

data

ATT

VCO

FILTER

WIDEBAND

SPECTRAL

Input pin

COMPIN

(Pin 19)

None

COMPIN

(Pin 19)

COMPIN

(Pin 19)

COMPIN

(Pin 19)

Input signal

data 100 Hz 245 mVrms

None

9.4 kHz 600 mVrms ST-L 30 % 300 Hz ST-L 30 % 3 kHz

Measurement

TVOUT-L output level TVOUT-R output frequency STA5 (FILADJ) TVOUT-R output level TVOUT-R output level

Adjustment contents

Adjust as close to 490 mVrms as possible Adjust as close to

62.936 kHz as possible Adjust to the center of the FILADJ=1 condition

Minimize the output level

Test mode

setting

TEST-DA=1

TEST1=1

—20—

CXA2054S

Adjustment Method (Adjust this through Tuner and IF when this IC is mounted on the set.)

1. ATT adjustment

1) TEST BIT is set to “TEST1=0” and “TEST-DA=0”.

2) Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then, adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value (490mVrms).

3) Adjustment range : ±30 % Adjustment bits : 4 bits

2. Stereo, SAP VCO adjustment

1) TEST BIT is set to “TEST1=0” and “TEST-DA=1”.

2) Monitor the TVOUT-R output (4 fH free running) frequency in a no input state, and adjust “VCO” adjustment data so that this frequency is as close to 4 fH (62.936 kHz) as possible.

3) Adjustment range : ±20 % Adjustment bits : 6 bits

3. Stereo, SAP, dbx filter adjustment

1) TEST BIT is set to “TEST1=1” and “TEST-DA=0”.

2) Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA5) condition, adjust the “FILTER” adjustment data.

3) Adjustment range : ±20 % Adjustment bits : 6 bits Align with the center of the STA5=1 (adjustment OK) condition range.

4. Separation adjustment

1) TEST BIT is set to “TEST1=0” and “TEST-DA=0”.

2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30 %, frequency 300 Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUT-R output to the minimum.

3) Next, set the frequency only of the input signal to 3 kHz and adjust the “SPECTRAL” adjustment data to reduce TVOUT-R output to the minimum.

4) Then, the adjustments in 2 and 3 above are performed to optimize the separation.

5) “WIDEBAND” “SPECTRAL” Adjustment range : ±30 % Adjustment range: ±15 % Adjustment bits : 6 bits Adjustment bits: 6 bits

0

1 0

3F

Adjustment point

Control data “FILTER”

Measurement data STA5 “FILTER”

—21—

CXA2054S

Description of Operation

The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.

Fig. 1. Base band spectrum

Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)

Fig 3. dbx-TV block

PEAK DEV

kHz

50

25

AM-DSB-SC

50

25

L + R

50-15KHZ

5

PILOT

L-R

dbx-TV

BR

15

SAP

dbx-TV NR

FM 10kHz

50-10kHz

TELEMETRY

FM 3kHz

3

f

H=15.734kHz

fH 2fH 3fH 4fH 5fH 6fH 6.5fH f

19

MVCA

(COMPIN)

PILOT

CANCEL

L-R (DSB)

DET

SUBVCA

14

(MAIN OUT) (MAIN IN)

13

4.7µ

L+R

PLL

(VCO 8fH)

2fHL0° f

HL90°

f

HL0°

PILOT

DET

I2C BUS DECODER

MODE CONTROL

MAIN LPFDE.EMSTEREO LPF

SUB LPF WIDEBAND

25

(SUBOUT)

26

4.7µ

(STIN)

L–R

SAP BPF

INJ.

LOCK

SAP (FM)

DET

SAP LPF

28

(SAP OUT)

4.7µ

29

(SAP IN)

NOISE

DET

SAP DET

I2C BUS DECODER MODE CONTROL

I

2

C BUS

DECODER

dbx-TV BLOCK

A

NR SW

B

MODE

CONTROL

MATRIX

(Lch)

(Rch)

TO SW

26

29

33 34

4.7µ

VCA

RMS

DET

RMS

DET

HPF

LPF

NR SW

A B

TO MATRIX

LPF

FIXED

DEEMPHASIS

VARIABLE

DEEMPHASIS

(VE OUT) (VCAIN)

(STIN)

(SAPIN)

—22—

CXA2054S

Fig. 4. Sound processor block

(1) L+R (MAIN)

After the audio multiplexing signal input from COMPIN (Pin 19) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L-R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (deemphasized) and input to the matrix.

(2) L-R (SUB)

The L-R signal follows the same course as L+R before the pilot signal is canceled. L-R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L-R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L-R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA.

(3) SAP

SAP is an FM signal using 5 fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 28 output is soft muted.

(4) Mode discrimination

Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5 fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25 kHz after FM detection of SAP signal.

(5) dbx-TV block

Either the SAP signal or L-R signal input respectively from ST IN (Pin 26) or SAP IN (Pin 29) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix.

43

SW1

40 39

(AUX1-L)

(AUX1-R)

(Lch)(Rch)

from MATRIX

PREVOL

44

(TVOUT-L) (TVOUT-R)

SW2

(AUX2-L) (AUX2-R)

41 40

VOLLIM

SURROUND

BASS TREBLE

VOL-R

7VOL-L

(LSOUT-L)

6

SW3

5

(LSOUT-R)

(SURROUT)

VOL-S

4

(SURRIN)

—23—

CXA2054S

The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal.

(6) Matrix, SW1, SW2

The signals (L+R, L-R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the BUS data and whether there is ST/SAP discrimination. “SW1” switch the “MATRIX” output signal, external input signal (input to AUX1-L, R (Pins 40 and 39)) and external forced MONO. “SW2” switch the “SW1” output signal, external input signal (input to AUX2-L, R (Pins 42 and 41)) and external forced MONO.

(7) Sound processor block

The sound processor block contains “VOLUME LIMITER”, “PREVOL”, “BASS/TREBLE” tone control functions, “SURROUND” (quasi-surround function) and “VOLUME”.

VL : 250 mVrms (limit level) BASS : ±12 dB (±1.7 dB/STEP at 100 Hz) TREBLE : ±12 dB (±1.7 dB/STEP at 10 kHz) VOLUME : 0 to –80 dB (–1.25 dB/STEP)

• Prevolume “PREVOL” controls the input signal level of the sound processor block. When turning on the bass boost, treble boost or surround, attenuate the input signal to the sound processor block using “PREVOL” so that the signal is not dissipated inside the processor.

PR-VOL : 0 to –13.75 dB (–1.25 dB/STEP)

• Surround At “SURROUND”, the L and R differential components are phase-shifted and these components are added to the left and right channels.

When surround is OFF (SURR=0) Inputs are output as is.

{

Lout=Lin Rout=Rin

When surround is ON (SURR=1)

{

Lout=Lin –

1–jωRC

(Lin-Rin)

1+jωRC

Rout=Rin +

1–jωRC

(Lin-Rin)

1+jωRC

{

R=24 kΩ (IC on-chip) C=0.022 µF (Externally attached to Pin 45)

(Lin, Lout) and (Rin, Rout) indicate the left- and right- channel I/O of the surround circuit.

—24—

CXA2054S

(8) Others

“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 21) with GND become the reference current.

Standard input and output levels

∗1 MONO, 25 kHz Deviation, Pre-Em. off ∗2 MONO, 25 kHz Deviation, Pre-Em. on ∗3 VOLUME MAX, PREVOL MAX, BASS & TREBLE CENTER, SURROUND OFF, VL OFF ∗4 Only SURROUT output

Input pin COMPIN AUX1-L/AUX1-R AUX2-L/AUX2-R SURRIN

Pin No.

19 40/39 42/41

4

Input level

245 mVrms

∗1

490 mVrms 490 mVrms 490 mVrms

TVOUT output level

490 mVrms

∗2

490 mVrms

— —

LSOUT output level

∗3

490 mVrms

∗2

490 mVrms 490 mVrms

490 mVrms

∗4

—25—

CXA2054S

Register Specifications

Slave address

Register table

SAD pin

GND

VCC

SLAVE RECEIVER

80 H

8 AH

SLAVE TRANSMITTER

81 H 8 BH

SUB ADDRESS

MSB LSB

∗∗∗∗

0000

∗∗∗∗

0001

∗∗∗∗

0010

∗∗∗∗

0011

∗∗∗∗

0100

∗∗∗∗

0101

∗∗∗∗

0110

∗∗∗∗

0111

∗∗∗∗

1000

∗∗∗∗

1001

∗∗∗∗

1010

∗∗∗∗

1011

∗∗∗∗

1100

DATA

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

∗ TEST-DA TEST1 ATT (4) ∗ VCO (6) ∗ FILTER (6) ∗ SPECTRAL (6) ∗ WIDEBAND (6)

∗ EXT1 EXT2 M2 NRSW FOMO SAPC M1

∗ ATTSW SURRSW FST FEXT1 FEXT2 ∗ VL SURR PR-VOL (4) ∗ VOL-L (6) ∗ VOL-R (6) ∗ VOL-SURR (6)

∗ TREBLE (4) ∗ BASS (4)

∗ : Don’t care

Status Registers

When TEST1=0

When TEST1=1

STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

POWER

STEREO SAP NOISE — — — —

ON RESET

STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

POWER

STEREO SAP NOISE FILADJ — — —

ON RESET

—26—

CXA2054S

Description of Registers

Control registers

Register

ATT VCO FILTER

SPECTRAL WIDEBAND

TEST-DA

TEST1 FST

PR-VOL VOL-L VOL-R VOL-SURR TREBLE BASS NRSW

FOMO FEXT1

FEXT2 VL SURR SURRSW

EXT1

EXT2

M1

M2 ATTSW SAPC

Number of bits

4 6 6

6 6

1

1 1

4 6 6 6 4 4 1

1 1

1 1 1 1

1

1 1 1

Classification∗

A A A

A A

T

T U U U U U U U

U U

U U U U

U

U S S

Contents Input level adjustment STEREO VCO and SAP VCO free running frequency adjustment STEREO, SAP and dbx filter adjustment Adjustment of stereo separation (3 kHz) Adjustment of stereo separation (300 Hz) Turn to DAC test mode and STVCO adjustment mode by means of TEST-DA=1. Turn to test mode by means of TEST=1. (Adjustment of FILTER) Turn to forced stereo by means of FST=1. Input signal level control of sound processor block LSOUT-L output signal level control LSOUT-R output signal level control SURROUT output signal level control LSOUT output treble control LSOUT output bass control Selection of the output signal (Stereo mode, SAP mode) Turn to forced MONO by means of FOMO=1. (Left channel only is MONO during SAP output.) External input 1 forced MONO (1 : forced MONO ON) External input 2 forced MONO (1 : forced MONO ON) Selection of volume limiter function ON/OFF (0 : OFF, 1 : ON) Selection of quasi-surround function ON/OFF (0 : OFF, 1 : ON) Selection of internal or external mode for SURROUT output Selection of TV mode or external input mode for TVOUT output Selection of internal mode or external input mode for LSOUT output Selection of TVOUT mute ON/OFF (0 : mute ON, 1 : mute OFF) Selection of LSOUT mute ON/OFF (0 : mute ON, 1 : mute OFF) Turn the input stage MVCA off when ATTSW=1. Selection of SAP mode or L+R mode according to the presence of SAP broadcasting

∗

Classification U : User control

U : Adjustment S : Proper to set T : Test

—27—

CXA2054S

Status registers

Register PONRES STEREO SAP NOISE FILADJ

Number of bits

1 1 1 1 1

Contents POWER ON RESET detection; 1 : RESET Stereo discrimination of the COMPIN input signal; 1 : Stereo SAP discrimination of the COMPIN input signal; 1 : SAP Noise level discrimination of the SAP signal; 1 : Noise Status of FILTER adjustment; 1 : OK range

Description of Control Registers

ATT (4) : Adjust the signal level input to COMPIN (Pin 19) to the standard input level.

Variable range of the input signal : 245 mVrms –5.0 dB to +3.0 dB 0 = Level min. F = Level max.

VCO (6) : Adjust STEREO & SAP VCO free running frequency (fo).

Variable range : fo ±20 % 0 = Free running frequency min. 3F = Free running frequency max.

FILTER (6) : Adjust the filter fo of the ST, SAP and dbx blocks.

Variable range : fo ±20 % 0 = Frequency min. 3F = Frequency max.

SPECTRAL (6) : Perform high frequency (fs=3 kHz) separation adjustment.

0 = Level max. 3F = Level min.

WIDEBAND (6) : Perform low frequency (fs=300 Hz) separation adjustment.

0 = Level min. 3F = Level max.

TEST-DA (1) : Set DAC output test mode and VCO adjustment mode.

0 = Normal mode 1 = DAC output test mode and STVCO adjustment mode In addition, the following outputs are present at Pins 44 and 43. TVOUT-L (Pin 44) : DA control DC level TVOUT-R (Pin 43) : STEREO VCO oscillation frequency (4fH)

TEST1 (1) : Set filter adjustment mode.

0 = Normal mode 1 = FILTER (STA5) adjustment mode In addition, the following outputs are present at Pins 44 and 43. TVOUT-L (Pin 44) : SAP BPF OUT TVOUT-R (Pin 43) : NR BPF OUT

—28—

CXA2054S

FST (1) : Select forced STEREO mode

0 = Normal mode 1 = Forced stereo mode

PR-VOL (4) : Input signal level control of sound processor block

When turning on the bass boost, treble boost or surround, attenuate the input signal to the sound processor block using “PR-VOL” so that the signal is not dissipated inside the processor. 4 = Volume Min. (–13.75 dB) F = Volume Max. (0 dB)

–1.25 dB/STEP

VOL-L (6) : LSOUT-L output signal level control

0 = Volume Min. (–80 dB) 3F = Volume Max. (0 dB)

–1.25 dB/STEP

VOL-R (6) : LSOUT-R output signal level control

0 = Volume Min. (–80 dB) 3F = Volume Max. (0 dB)

–1.25 dB/STEP

VOL-SURR (6) : SURROUT output signal level control

0 = Volume Min. (–80 dB) 3F = Volume Max. (0 dB)

–1.25 dB/STEP

TREBLE (4) : LSOUT output treble control

0 = Treble Min. 7 & 8 = Treble Center (0 dB) F = Treble Max.

BASS (4) : LSOUT output bass control

0 = Bass Min. 7 & 8 = Bass Center (0 dB) F = Bass Max.

NRSW (1) : Select stereo mode or SAP mode

0 = Stereo mode 1 = SAP mode

FOMO (1) : Select forced MONO mode

0 = Normal mode 1 = Forced MONO mode

—29—

CXA2054S

FEX1 (1) : Turn external input [1] to forced MONO.

0 = Normal mode 1 = External input [1] is forced MONO.

Input the same signal to both AUX1-L and AUX1-R.

FEX2 (1) : Turn external input [2] to forced MONO.

0 = Normal mode 1 = External input [2] is forced MONO.

Input the same signal to both AUX2-L and AUX2-R.

VL (1) : Volume limiter function selection

0 = Volume limiter OFF 1 = Volume limiter ON

SURR (1) : Surround function selection

0 = Surround OFF 1 = Surround ON

SURRSW (1) : Select INT mode or EXT mode for SURROUT output

0 = INT mode 1 = EXT mode

EXT1 (1) : Select TV mode or external input mode for TVOUT output.

0 = TV mode 1 = External input mode

EXT2 (1) : Select internal mode or external input mode for LSOUT output.

0 = internal mode 1 = External input mode

M1 (1) : Mute the TVOUT-L and TVOUT-R output.

0 = Mute ON 1 = Mute OFF

M2 (1) : Mute the LSOUT-L and LSOUT-R output.

0 = Mute ON 1 = Mute OFF

ATTSW (1) : Select BYPASS SW of Main VCA

0 = Normal mode 1 = Main VCA is passed

SAPC (1) : Select the SAP signal output mode

When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L+R output is selected 1 = SAP output is selected

—30—

CXA2054S

Description of Mode Control

Priority ranking : M1/M2 > EXT1/EXT2 > TEST-DA > TEST1 > (NRSW & FOMO & SAPC)

Mode control

NRSW

FOMO

SAPC

M1/M2

EXT1/EXT2

TEST1

TEST-DA

“Forced MONO”

FOMO=1

• During SAP output: left channel : L+R, right channel : SAP

• During ST or MONO output: left channel : L+R, right channel : L+R Change the selection conditions for “MONO or ST output” and “SAP output”.

SAPC=0 : Switch to SAP output when there is SAP discrimination.

Do not switch to SAP output when there is no SAP discrimination.

SAPC=1 : Switch to SAP output regardless of whether there is SAP discrimination.

“MUTE” M1=0 : TVOUT output is muted. M2=0 : LSOUT output is muted.

“TV mode/external input mode selection” EXT1=0 : Set TVOUT output to TV mode. EXT1=1 : Set TVOUT output to external input [1] mode. EXT2=0 : Set LSOUT output to internal mode. EXT2=1 : Set LSOUT output to external input [2] mode.

“TEST1” TEST1=1 Return adjustment data with STATUS REGISTER as an adjustment mode. In addition, outputs are as follows. left channel : SAP BPF OUT right channel : NR BPF OUT

“TEST-DA” TEST-DA=1 Used to adjust the D/A TEST and STVCO. left channel : D/A output right channel : STVCO oscillation frequency (4fH)

SAPC=0 “Select dbx input and TV decoder output” Conditions : FOMO = 0 NRSW=0 (MONO or ST output)

• During ST input : left channel: L,

right channel: R

• During other input : left channel: L+R,

right channel: L+R

NRSW=1 (SAP output)

• When there is “SAP” during

SAPdiscrimination

–left channel : SAP, right channel : SAP

• When there is “No SAP”, output is the

same as when NRSW=0.

SAPC=1 “Select dbx input and TV decoder output” Conditions : FOMO = 0 NRSW=0 (MONO or ST output)

As on the left

NRSW = 1 (SAP output)

• Regardless of the presence of SAP

discrimination, dbx input : “SAP”

left channel : SAP, right channel : SAP However, when there is no SAP, SAPOUT output is soft muted (–7 dB)

—31—

CXA2054S

Decoder Output and Mode Control Table 1 (SAPC=1)

Input signal mode

MONO

1)

STEREO

1)

MONO & SAP

STEREO & SAP

Mode detection

ST SAP NOISE

0 0 0 0 0 0 0 0 0 0 ∗ 1 0 ∗ 1 0 ∗ 1 1 0 ∗ 1 0 ∗ 1 1 1 1 1 1 1 0 0 1 0 0 1 ∗ 1 1 ∗ 1 0 1 ∗ 0 1 ∗ 0 1 0 0 1 0 0 1 1 0 1 1 1 1 ∗ 1 1 ∗ 1 1 0 1 1 0 1 1 1 1 1 1

dbx

input

MUTE

SAP

SAP MUTE (SAP) (SAP)

L-R

MUTE

L-R

MUTE

SAP

SAP (SAP) (SAP) MUTE MUTE

SAP

SAP (SAP) (SAP)

L-R

MUTE

SAP

SAP (SAP) (SAP)

Output

Lch Rch

L+R L+R

SAP SAP

L+R SAP L+R L+R

(SAP) (SAP)

L+R (SAP)

L R

L+R L+R

L R

L+R L+R

SAP SAP

L+R SAP

(SAP) (SAP)

L+R (SAP) L+R L+R L+R L+R

SAP SAP

L+R SAP

(SAP) (SAP)

L+R (SAP)

L R

L+R L+R

SAP SAP

L+R SAP

(SAP) (SAP)

L+R (SAP)

Mode control

NRSW FOMO SAPC

0 ∗ 1 1 0 1 1 1 1 0 ∗ 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1

Note

(SAP) : The SAPOUT output signal is soft muted (approximately –7 dB).

The signal is soft muted when NOISE=1.

∗ : Don’t care.

1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. “NOISE” status rises earlier than “SAP” status when the amount of noise is increased to COMPIN.

—32—

CXA2054S

Decoder Output and Mode Control Table 2 (SAPC=0)

Input signal mode

MONO

1)

STEREO

1)

MONO & SAP

STEREO & SAP

Mode detection

ST SAP NOISE

0 0 ∗ 0 1 1 0 1 1 0 1 1 0 1 1 1 0 ∗ 1 0 ∗ 1 0 ∗ 1 0 ∗ 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

dbx

input MUTE MUTE MUTE

(SAP) (SAP)

L-R

MUTE

L-R

MUTE

L-R

MUTE

(SAP)

(SAP) MUTE MUTE

SAP

SAP MUTE MUTE

(SAP) (SAP)

L-R

MUTE

SAP

L-R

MUTE

(SAP) (SAP)

Output

Lch Rch L+R L+R L+R L+R L+R L+R

(SAP) (SAP)

L+R (SAP)

L R

L+R L+R

L R

L+R L+R

L R

L+R L+R

(SAP) (SAP)

L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP L+R L+R L+R L+R

(SAP) (SAP)

L+R (SAP)

L R L+R L+R SAP SAP L+R SAP

L R L+R L+R SAP (SAP) L+R (SAP)

Mode control

NRSW FOMO SAPC

∗ ∗ 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0

Note

(SAP) : The SAPOUT output signal is soft muted (approximately –7 dB).

The signal is soft muted when NOISE=1.

∗ : Don’t care.

1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. “NOISE” status rises earlier than “SAP” status when the amount of noise is increased to COMPIN.

—33—

CXA2054S

Mode Control Table 3

EXT1

0 1 1

∗

EXT2

0 0 0

1

∗

FEXT1

* 0 1

∗

FEXT2

∗ ∗ ∗

0

1

∗

M1

1 1 1

1

0

1

M2

1 1 1

1

0

TV OUT-L TV-L AUX1-L AUX1-L Selected according to the EXT1, FEXT1 conditions Selected according to the EXT1, FEXT1 conditions

MUTE

Selected according to the EXT1, FEXT1 conditions

TV OUT-R TV-R AUX1-R AUX1-L Selected according to the EXT1,FEXT1, conditions Selected according to the EXT1,FEXT1, conditions

MUTE

Selected according to the EXT1,FEXT1, conditions

LS OUT-L TV-L AUX1-L AUX1-L

AUX2-L

Selected according to the EXT2, FEXT2, conditions

MUTE

LS OUT-R TV-R AUX1-R AUX1-L

AUX2-R

AUX2-L

Selected according to the EXT2, FEXT2, conditions

MUTE

I2C BUS Signal

There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.

• Accordingly there are 3 values outputs, H, L and HIZ.

• I2C transfer begins with Start Condition and ends with Stop Condition.

SDA

SCL

Start Condition S

H L LHIZ

Stop Condition P

TV-L/TV-R are selected in Matrix. TV-L : MONO, ST-L, SAP (SAPBFout, D/A out) TV-R : MONO, ST-R, SAP (NRBPFout, STVCO free run (4fH))

—34—

CXA2054S

• I2C data Write (Write from I2C controller to the IC)

SDA

SCL

MSB MSB LSB

L during Write

HIZ HIZ

S

1 2 3 4 5 6 7 8 9 1 8 9

Address ACK Sub Address ACK

MSB LSB

HIZ HIZ

1 8 9 1 8 9

DATA (n) ACK DATA (n+1) ACK DATA (n+2)

HIZ HIZ

DATA ACK DATA ACK

P

8 9 1 8 9

• I2C data Read (Read from the IC to I2C controller)

• Read timing

∗ Data Read is performed during SCL rise.

SDA

SCL

H during Read

HIZ

S P

Address ACK DATA ACK

1 6 7 8 9 1 7 8 9

IC output SDA

SCL

Reat timing

MSB LSB

9 1 2 3 4 5 6 7 8 9

ACK DATA ACK

∗ Data can be transferred in 8-bit units to be set

as required. Sub address is incremented automatically.

—35—

CXA2054S

Input level vs. Distortion characteristics 1 (MONO)

Distortion (%)

Input level vs. Distortion characteristics 2 (Stereo)

Distortion (%)

Input level (dB)

Input level vs. Distortion characteristics 3 (SAP)

Distortion (%)

Input level (dB)

1.0

0.1

Standard level (100%)

–10 0 10

Input signal : MONO (Pre-emphasis on), 1kHz 0dB=100% modulation level VCC=9V, 30kHz using LPF Measurement point : TVOUT-L/R

Standard level (100%)

10

1.0

Input signal : Stereo L=–R (dbx-TVNR ON), 1kHz 0dB=100% modulation level VCC=9V, 30kHz using LPF, ST mode Measurement point : TVOUT-L/R

–10 0 10

10

1.0

Input level (dB)

–10 0 10

Standard level (100%)

Input signal : SAP (dbx-TVNR ON) 1kHz, 0dB=100% modulation level VCC=9V, 30kHz using LPF, SAP mode Measurement point : TVOUT-L/R

—36—

CXA2054S

Frequency (kHz)

Gain (dB)

Stereo LPF frequency characteristics

Gain (FC main and FC sub) (dB)

SAP frequency characteristics and group delay

Group delay (µs)

Frequency (kHz)

Main LPF and Sub LPF frequency characteristics

Gain (dB)

10

5

0

–5

–10

0 20 40 60 80 100

1 2 5 7 10 20 50 70 100

30

20

10

0

–10

–20

–30

–40

–50

20

10

0

–10

–20

40 60 80 100 120

100 90 80 70 60 50 40 30 20 10 0

5fH

Gain

3.8 fH

Group delay

6.2fH

—37—

CXA2054S

Frequency (Hz)

Boost amount (dB)

BASS - TREBLE characteristics

LSOUT output level (dB)

Volume characteristics

Control data VOL-L, VCL-R, VOL-SURR

BASS.MAX TREBLE.MAX

+12

+8

+4

0

–4

–8

–12

20 100 1k 10k 20k

BASS. MIN TREBLE.MIN

Input : AUXIN (Pins 40/39 and 42/41) 245 mVrms Output : LSOUT (PINS 5, 6 and 7)

0

–20

–40

–60

–80

–100

0 F 1F 2F 3F

Input : AUXIN (Pins 40/39 and 42/41) 1kHz, 490mVrms Output : LSOUT (Pins 5, 6 and 7)

OUT (mVrms)

Volume limiter characteristics

IN (Vrms)

10

–2

500

10

–1

100

10

1

48PIN SDIP (PLASTIC)

13.0

+ 0.3

– 0.1

4.6

+ 0.4

– 0.1

0.25

+ 0.1

– 0.05

48 25

1 24

1.778

15.24

0° to 15°

0.5 ± 0.1

0.9 ± 0.15

3.0 MIN 0.5 MIN

SONY CODE EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT LEAD MATERIAL PACKAGE MASS

EPOXY RESIN

PLATING

42/COPPER ALLOY

5.1g

SDIP-48P-02 SDIP048-P-0600

43.2

+ 0.4 – 0.1

SOLDER/PALLADIUM

1.All mat surface type.

Two kinds of package surface:

2.Center part is mirror surface.

Package Outline Unit : mm

CXA2054S

—38—