Datasheet CXA2134Q Datasheet (Sony)

US Audio Multiplexing Decoder

Description

The CXA2134Q is an IC designed as a decoder for
the Zenith TV Multi-channel System and also
corresponds with I2C bus. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built in this IC.
Adjustment, mode control and sound processor
control are all executed through I2C bus.

Features

• Alignment-free VCO and filter

• Audio multiplexing decoder

dbx noise reduction decoder

sound processor

— Two external inputs

— Quasi-surround

— Bass control

— Treble control

— Volume control

are all included in a single chip. Almost any soft of

signal processing is possible through this IC.

• Input level, separation adjustments and each mode

control are possible through I2C bus.

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VCC 11 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 0.6 W

Range of Operating Supply Voltage

9 ± 0.5 V

– 1 –

E99832-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA2134Q

48 pin QFP (Plastic)

∗

A license of the dbx-TV noise reduction system is required for the use of this device.

– 2 –

CXA2134Q

Block Diagram

VGR

IREF

DGND

SCL

SDA

SAPOUT

SAPIN

STIN

VE

VEWGT

VETC

VEOUT

VCAIN

VCAWGT

VCATC

MAININ

MAINOUT

SUBOUT

PLINT

PCINT1

COMPIN

V

CC

GND

NOISETC

SAPTC

AUX2-L

IREF

SW

LPF LPF

HPF

RMSDET

RMSDET

VCA

VE

DeEm

LOGIC

MATRIX

VCA

LPF

LPF

1/21/4VCOLFLT

VCA LPF

BPF

SAPVCO

LPF

NOISE

DET

SAPIND

"PONRES"

STIND

"SAP"

"NOISE"

NRSW/FOMO/SAPC

WIDEBAND

SPECTRAL

"STEREO"

DeEm

FLT

AMP

(+4dB)

I

2

C BUS I/F

(+6dB)

LSOUT-L

LSOUT-R

VOL-L

VOL-R

VOL-L

VOL-R

TREB

SURROUND

TREBLE

TREB

AUX1-R
AUX1-L

AUX2-R

BASS-R

TRE-L

TRE-R

VOLIN-R

PCINT2

BASS

BASS

BASS

TVSW

SURRTC

BASS-L

TVOUT-L

TVOUT-R

FEXT2

FEXT1

EXT1/EXT2/M1

TOUT-R

ATT/ATTSW

28
27

26

8

9

21

19

17

23

18

24

25

22

SURR

M2

TOUT-L

VOLIN-L

13

10

11

12

34

33

37

36

39

38

40

2

45

47

41

44

43

3

4

48
1

31
32

30
29

5

6

7

1514

– 3 –

CXA2134Q

Pin Configuration (Top View)

25

26

27

28

29

30

36

35

34

31

32

33

AUX2-R

NC

AUX1-L

AUX1-R

VCAWGT

VCATC

VCAIN

VEOUT

VETC

VEWGT

VE

SAPIN

2

3

4

5

6

7

8

9

10

11

121

TOUT-L

BASS-L

LSOUT-R

SDA

SCL

DGND

PLINT

PCINT1

MAINOUT

MAININ

LSOUT-L

PCINT2

13

14

15

16

17

18

19

20

21

22

23

24

COMPIN

VGR

NC

GND

SAPTC

NC

STIN

NOISETC

IREF

V

CC

SAPOUT

SUBOUT

40

39

38

37

41

42

43
44
45
46
47
48

VOLIN-L

TRE-L

NC

BASS-R

SURRTC

TOUT-R

NC

TRE-R

TVOUT-L

TVOUT-R

AUX2-L

VOLIN-R

– 4 –

CXA2134Q

Pin Description (Ta = 25°C, Vcc = 9V)

Pin No.

Symbol

Pin

voltage

Equivalent circuit

Description

580

VCC

580

44

1

147

1

44

4.0V

4.0V

TOUT-L

TOUT-R

Treble output pin.
(Left channel)

Treble output pin.
(Right channel)

1.2k

5.4k

11k

1.2k

11k

147

2

45

Vcc

4V

2

45

4.0V

4.0V

BASS-L

BASS-R

Bass filter pin.
(Left channel)

Bass filter pin.
(Right channel)

580

580

VCC

3k

3
4

3

4

4.0V

4.0V

LSOUT-R

LSOUT-L

LSOUT right channel output
pin.

LSOUT left channel output
pin.

5

—SDA

Serial data I/O pin.
VIH > 3.0V
VIL < 1.5V

7.5k

4.5k

× 5

4k

3k

7.5k

V

CC

↓ 35µ

2.1V

× 2

5

– 5 –

CXA2134Q

6

—

SCL

Serial clock input pin.
VIH > 3.0V
VIL < 1.5V

7

—

DGND Digital block GND.

8

4.0V

MAININ

Input pin of (L + R) signal
from MAINOUT (Pin 9).

9

4.0V

MAINOUT

(L + R) signal output pin.

7

VCC

147

10k

53k

4V

VCC

8

147

1k

15k

↓

200µ

V

CC

× 4

9

Pin No.

Symbol

Pin

voltage

Equivalent circuit

Description

10.5k

VCC

4k

× 4

3k

7.5k

↓ 35µ

2.1V

6

– 6 –

CXA2134Q

10

4.0V

PCINT1

11

4.0V

PCINT2

Stereo block PLL loop filter
integrating pin.

12

5.1V

PLINT

Pilot cancel circuit loop filter
integrating pin.
(Connect a 1µF capacitor
between this pin and GND.)

13

4.0V

COMPIN

Audio multiplexing signal
input pin.

4k

VCC

× 2

10k

10k

2k

147

11

VCC

147

20k

20k

10k

20k

20k

20k

12

VCC

22k

3V

20k

4k 4k 4k 16k

24k

50k 147

3k

13

Pin No.

Symbol

Pin

voltage

Equivalent circuit

Description

VCC

147

10

30k

22k

– 7 –

CXA2134Q

14

1.3V

VGR

Band gap reference output
pin.
(Connect a 10µF capacitor
between this pin and GND.)

40k 40k 30k

30p 1.8k

16k

6.3k

147

30k 15k 30k

VCC

× 2

V

CC

15

15

1.3V

IREF

Set the filter and VCO
reference current. The
reference current is adjusted
with the BUS DATA based
on the current which flows to
this pin.
(Connect a 62kΩ (±1%)
resistor between this pin and
GND.)

17

—

GND Analog block GND.

17

19

—

Vcc Supply voltage pin.

19

18

4.5V

SAPTC

Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)

8k

4k

3k

10k

V

CC

↓ 50µ

1k

VCC

18

Pin No.

Symbol

Pin

voltage

Equivalent circuit

Description

11k

3k

9.7k

2.06k

19.4k

× 4

14

VCC

147

11k

11k

– 8 –

CXA2134Q

21

4.0V

SUBOUT (L – R) signal output pin.

23

3.0V

NOISETC

Set the time constant for the
noise detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)

24

4.0V

SAPOUT SAP FM detector output pin.

25

4.0V

SAPIN

Input pin of (SAP) signal from
SUPOUT (Pin 24).

22

4.0V

STIN

Input pin of (L – R) signal
from SUBOUT (Pin 21).

3k

3k

3.3k

4k

4V

Vcc

8k

× 2

10k

1k

2k

Vcc

200k

23

24k
↓ 10µ

580

Vcc

5P

580

4k
↓ 50µ

10k

147

24

Pin No.

Symbol

Pin

voltage

Equivalent circuit

Description

22

2k 2k

2k

147

18k

4V

23k

2k2k

14.4k

4k

11.7k

20k

23k

580

580

4V

10P
4k

147

1k

147

18k

Vcc

21

VCC

25

– 9 –

CXA2134Q

26

4.0V

VE

Variable de-emphasis
integrating pin.
(Connect a 2700pF capacitor
and a 3.3kΩ resistor in series
between this pin and GND.)

Vcc

4V

36k

2.9V

580

147

580

8k

30k
↓ 8µ

4k
↓ 50µ

27

27

4.0V

VEWGT

Weight the variable
de-emphasis control
effective value detection
circuit.
(Connect a 0.047µF
capacitor and a 3kΩ resistor
in series between this pin
and GND.)

20k
↓ 7.5µ

4k
↓ 50µ

Vcc

× 4

× 4

28

28

1.7V

VETC

Determine the restoration
time constant of the variable
de-emphasis control
effective value detection
circuit.
(The specified restoration
time constant can be
obtained by connecting a

3.3µF capacitor between this
pin and GND.)

Vcc

10k

580

580

5P

29

29

4.0V

VEOUT

Variable de-emphasis output
pin.
(Connect a 4.7µF non-polar
capacitor between Pins 29
and 30.)

Pin No.

Symbol

Pin

voltage

Equivalent circuit

Description

147

26

VCC

7.5k

– 10 –

CXA2134Q

30

4.0VVCAIN

VCA input pin.
Input the variable
de-emphasis output signal
from Pin 29 via a coupling
capacitor.

↓

50µ

VCC

4k

20k

× 4

× 4

↓

7.5µ

31

31

1.7VVCATC

Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(The specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
pin and GND.)

4k

VCC

30k 8k

36k

2.9V

3p

580

580

147

40k 40k

↓

50µ

↓

8µ

32

VCC

4V

27.5k

27.5k

147

10k

33

34
36
37

32

4.0VVCAWGT

Weight the VCA control
effective value detection
circuit.
(Connect a 1µF capacitor
and a 3.9kΩ resistor in series
between this pin and GND.)

33

4.0VAUX1-R

Right channel external input
1 pin.

34

4.0VAUX1-L

Left channel external input
1 pin.

36

4.0VAUX2-R

Right channel external input
2 pin.

37

4.0VAUX2-L

Left channel external input
2 pin.

Pin No.

Symbol

Pin

voltage

Equivalent circuit

Description

VCC

47k

20k

VCC

30

47k

– 11 –

CXA2134Q

38

4.0VTVOUT-R

TVOUT right channel output
pin.

39

4.0VTVOUT-L

TVOUT left channel output
pin.

40

4.0V

SURRTC

Set the center frequency of
the Surround circuit phase
shifter.
The frequency is determined
by the built-in resistor and
the external capacitor.
(Connect a 0.022µF
capacitor between this pin
and GND.)

43

4.0V

VOLIN-R

Volume right channel input
pin.

48

4.0V

VOLIN-L

Volume left channel input pin.

16
20
35
42
46

—

NC

1.2k6k1.2k

147

Vcc

5.7k

5.7k

41

47

41

4.0VTRE-R

Treble filter pin.
(Right channel)

47

4.0VTRE-L

Treble filter pin.
(Left channel)

VCC

4V

66k

147

10k

43

48

Pin No.

Symbol

Pin

voltage

Equivalent circuit

Description

40

147

38

39

20k

580

580

10k

20k

3k

24k

VCC

580

580

VCC

40k

– 12 –

CXA2134Q

Electrical Characteristics

COMPIN input level

(100% modulation level)

(Ta = 25°C, V

CC = 9V)

Main (L + R) (Pre-Emphasis: OFF) = 245mVrms

SUB (L – R) (dbx-TV: OFF) = 490mVrms

Pilot = 49mVrms

SAP Carrier = 147mVrms

f

H = 15.734kHz

Item

Current consumption

Main output level

Main de-emphasis

frequency response

Main LPF frequency

response

Main distortion

Main overload distortion

Main S/N

Sub output level

Sub LPF frequency

response

Sub distortion

Sub overload distortion

Sub S/N

Crosstalk

Stereo → SAP

Sub pilot leak

Stereo ON level

Stereo ON/OFF

hysteresis

No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Signal

Icc

Vmain

FCdeem

FCmain

THDm

THDmmax

SNmain

Vsub

FCsub

THDsub

THDsmax

SNsub

CTst

PCsub

THst

HYst

Mode

MONO

MONO

MONO

MONO

MONO

MONO

ST

ST

ST

ST

ST

SAP

ST

ST

Input pin

—

13

13

13

13

13

13

13

13

13

13

13

13

13

13

Min.

37

440

–1.2

–3.0

—

—

61

150

–3.0

—

—

56

60

—

–9.0

3.5

Typ.

47

490

0

–1.0

0.1

0.15

69

190

–0.5

0.1

0.2

64

70

–38

–6.0

6.0

Max.

57

540

1.0

1.0

0.5

0.5

—

230

1.0

1.0

2.0

—

—

–27

–3.0

8.5

Unit

mA

mVrms

dB

dB

%

%

dB

mVrms

dB

%

%

dB

dB

dB

dB

dB

Input signal

No signal

Mono 1kHz 100% mod.

Pre-em. ON

Mono 5kHz 30% mod.

Pre-em. ON

Mono 12kHz 30% mod.

Pre-em. ON

Mono 1kHz 100% mod.

Pre-em. ON

Mono 1kHz 200% mod.

Pre-em. ON

Mono 1kHz,

Pre-em. ON

SUB (L-R), 1kHz,

100% mod., NR OFF

SUB (L-R) 12kHz,

30% mod., NR OFF

SUB (L-R) 1kHz,

100% mod., NR OFF

SUB (L-R), 1kHz,

200% mod., NR OFF

SUB (L-R) 1kHz,

NR OFF

ST-L (R), 1kHz,

100% mod., NR ON,

SAP Carrier (5fH)

PILOT (fH) 0dB

Change

PILOT (f

H) Level

Measurement

conditions

20 log

('5k'/'1k')

20 log

('12k'/'1k')

20 log

('100%'/'0%')

20 log

('12k'/'1k')

20 log

('100%'/'0%')

20 log

('NRSW = 0'/

'NRSW = 1')

0dB = 49mVrms

0dB = 49mVrms

20 log (‘on

level'/'off level')

Filter

15kLPF

15kLPF

15kLPF

15kLPF

15kLPF

15kLPF

1kBPF

f

H BPF

Output

pin

19

38/39

38/39

38/39

38/39

38/39

38/39

21

21

21

21

21

39

21

BUS

RETURN

– 13 –

CXA2134Q

No.

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

Item

SAP output level

SAP LPF frequency

response

SAP distortion

SAP S/N

Cross talk

SAP → Stereo

SAP ON level

SAP ON/OFF hysteresis

ST separation 1 L → R

ST separation 1 R → L

ST separation 2 L → R

ST separation 2 R → L

TVOUT output level

TVOUT

mute amount

LSOUT output level

LSOUT cross talk

EXT → INT

LSOUT cross talk

INT → EXT

Symbol

Vsap

FCsap

THDsap

SNsap

CTsap

THsap

HYsap

STLsep1

STRsep1

STLsep2

STRsep2

Vtv

MUtv1

MUtv2

Vls

CTls

Mode

SAP

SAP

SAP

SAP

ST

SAP

ST

ST

ST

ST

EXT

INT

EXT

INT

EXT

INT

EXT

Input pin

13

13

13

13

13

13

13

13

13

13

33/34

36/371333/34

36/371333/34

36/37

33/34

36/37

13

Min.

130

–3.0

—

46

60

–12.0

2.0

23

23

23

23

440

—

—

440

440

—

—

Typ.

160

0

2.5

55

70

–9.0

4.0

35

35

35

35

490

–95

–95

490

490

–75

–90

Max.

190

2.5

6.0

—

—

–6.5

6.0

—

—

—

—

540

–80

–80

540

540

–60

–80

Unit

mVrms

dB

%

dB

dB

dB

dB

dB

dB

dB

dB

mVrms

dB

dB

mVrms

mVrms

dB

dB

Input signal

SAP 1kHz 100% mod.

NR OFF

SAP 10kHz, 30% mod

.

NR OFF

SAP 1kHz 100% mod

.

NR OFF

SAP 1kHz, NR OFF

SAP 1kHz 100% mod.

NR ON, Pilot (fH)

Change

SAP Carrier (5f

H)

Level

ST-L 300Hz 30% mod

.

NR ON

ST-R 300Hz 30% mod

.

NR ON

ST-L 3kHz 30% mod

.

NR ON

ST-R 3kHz 30% mod

.

NR ON

Sine wave 1kHz,

490mVrms

Mono 1kHz 100% mod.

Pre-em. ON

Sine wave 1kHz,

490mVrms

Mono 1kHz 100% mod.

Pre-em. ON

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

Mono 1kHz 100% mod.

Pre-em. ON

Measurement

conditions

20 log

('10k'/'1k')

20 log

('100%'/'0%')

20 log ('NRSW

= 1'/'NRSW = 0')

0dB = 147mVrms

20 log (‘on

level’/’off level’)

20 log

('Lch'/'Rch')

20 log

('Rch'/'Lch')

20 log

('Lch'/'Rch')

20 log

('Rch'/'Lch')

20 log

(M1 =

"0"/M1 = "1")

20 log

(M1 =

"0"/M1 = "1")

Filter

15kLPF

15kLPF

1kBPF

15kLPF

15kLPF

15kLPF

15kLPF

1kBPF

1kBPF

1kBPF

Output

pin

24

24

24

24

39

BUS

RETURN

38/39

38/39

38/39

38/39

38/39

38/39

3/4

3/4

3/4

– 14 –

CXA2134Q

No.

35

36

37

38

39

40

41

42

43

44

45

46

Item

LSOUT mute amount

LSOUT DC offset

LSOUT distortion

LSOUT S/N

LSOUT overload distortion

Bass maximum value

Bass minimum value

Treble maximum value

Treble minimum value

Volume minimum value

SURROUND

frequency response 1

SURROUND

frequency response 2

Symbol

MUls

OSls

THDls

SNls

THDlsmax

TBmax

TBmin

TTmax

TTmin

VOLmin

Sr1Sr2

Mode

EXT

INT

EXT

EXT

EXT

EXT

EXT

EXT

EXT

EXT

EXT

EXT

EXT

Input pin

33/34

36/37

—

33/34

36/37

33/34

36/37

33/34

36/37

33/34

36/37

33/34

36/37

33/34

36/37

33/34

36/37

33/34

36/37

34/37

34/37

Min.

—

–25

—

67

—

9

–13

9

–13

—

1.5

4.5

Typ.

–90

0

0.01

77

0.03

11

–11

11

–11

–90

3.0

6.0

Max.

–80

25

0.5

—

0.5

13

–9

13

–9

–80

4.8

7.5

Unit

dB

mV

%

dB

%

dB

dB

dB

dB

dB

dB

dB

Input signal

Sine wave 1kHz,

490mVrms

No signal

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

490mVrms

Sine wave 1kHz,

2Vrms

Sine wave 100Hz,

490mVrms

Sine wave 100Hz,

490mVrms

Sine wave 10kHz,

490mVrms

Sine wave 10kHz,

490mVrms

Sine wave 1kHz,

490mVrms

Sine wave 330Hz,

490mVrms

Sine wave 10kHz,

490mVrms

Measurement

conditions

20 log (M2 =

"0"/M2 = "1")

Mute (M2 = "0")/

DC difference

when there is

no signal

BASS = "3F"

BASS = "0"

TREBLE = "3F"

TREBLE = "0"

VOL-L = "0",

VOL-R = "0"

Filter

1kBPF

15kLPF

15kLPF

15kLPF

1kBPF

Output

pin

3/4

3/4

3/4

3/4

3/4

3/4

3/4

3/4

3/4

3/4

4

4

– 15 –

CXA2134Q

Electrical Characteristics Measurement Circuit

MEASURESFILTER

15kHz LPF
f

H BPF

1kHz BPF

I

2

C BUS DATA

S6
S5
S4
S3
S2
S1

BUF

R6

3.3k

R7

3k

C16

2700p

C17

0.047µ

25

2627

28

29

30

36

35

34

31

32

33

AUX2-R

NC

AUX1-L

AUX1-R

VCAWGT

VCATC

VCAIN

VEOUT

VETC

VEWGT

VE

SAPIN

2

3

4

5

6

7

8

9

10

11

12

1

TOUT-L

BASS-L

LSOUT-R

SDA

SCL

DGND

PLINT

PCINT1

MAINOUT

MAININ

LSOUT-L

PCINT2

13

14

15

16

17

18

19

20

21

22

23

24

COMPIN

VGR

NC

GND

SAPTC

NC

STIN

NOISETC

IREF

V

CC

SAPOUT

SUBOUT

40

39

38

37

41

42

43

44

45

46

47

48

VOLIN-L

TRE-L

NC

BASS-R

SURRTC

TOUT-R

NC

TRE-R

TVOUT-L

TVOUT-R

AUX2-L

VOLIN-R

C18

3.3µ
TANTALUM

C19

4.7µ

C20
10µ

TANTALUM

R8

3.9k
C21

1µ

C24

4.7µ

SIGNAL
GENE­RATOR

V2

AC

V1
AC

C28

0.022µ

C26

4.7µ
C27

4.7µ

C1

4.7µ

C5

4.7µ

R1

220R2220

R3

1MEG

C6

5600P

R4

100kC70.012µ

DGND

C13

4.7µ

C9

4.7µ

GND

V6
AC

SIGNAL
GENERATOR

GND

GND

C10

10µ

R5
62k ± 1% METAL

C11

4.7µ

C12

100µ

V5
9V

V

CC

C14

4.7µ

C15

4.7µ

C8
1µ

C2

0.1µC34.7µC44.7µ

C29

4700p

C30

4.7µ

C32

4700p

C31

0.1µ

C25

4.7µ

SIGNAL
GENE­RATOR

C23

4.7µ

V3
AC

SIGNAL
GENE­RATOR

C22

4.7µ

V4
AC

SIGNAL
GENE­RATOR

– 16 –

CXA2134Q

Adjustment Method

The resister data is set to the standard value.

1.ATT adjustment

1) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then,
adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value
(490mVrms).

2) Adjustment range: ±20%
Adjustment bits: 4 bits

2.Separation adjustment

1) Input ST-L signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the
“WIDEBAND” adjustment data to reduce TVOUT-R output to the minimum.

2) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to
reduce TVOUT-R output to the minimum.

3) The adjustments in 1 and 2 above are performed to optimize the separation.

4) “WIDEBAND” “SPECTRAL”
Adjustment range: ±30% Adjustment range: ±15%
Adjustment bits: 6 bits Adjustment bits: 6 bits

Note) Adjust this IC through tuner and IF when this IC is mounted on the set.

– 17 –

CXA2134Q

Slave receiver

84H (1000 0100)

Slave transmitter
85H (1000 0101)

Register Specifications

Slave address

Register table

Status registers

STA1

BIT7

POWER

ON RESET

STA2

BIT6

STEREO

STA3

BIT5

SAP

STA4

BIT4

NOISE

STA5

BIT3

—

STA6

BIT2

—

STA7

BIT1

—

STA8

BIT0

—

Note) The microcomputer reads both SAP and NOISE status and judges SAP discrimination.

SPECTRAL
WIDEBAND

BASS

TREBLE

VOL-L
VOL-R

∗∗∗∗0000
∗∗∗∗0001
∗∗∗∗0010
∗∗∗∗0011
∗∗∗∗0100
∗∗∗∗0101
∗∗∗∗0110
∗∗∗∗0111
∗∗∗∗1000

Data

Sub address

MSB LSB

BIT7

∗

BIT6

M2

∗
∗
∗

∗
∗
∗
∗

BIT5 BIT4 BIT3 BIT2

BIT1

BIT0

TEST-DA

EXT1

TEST1

EXT2

SURR

NRSW

ATTSW

FOMO

∗

SAPC

FEXT1

M1

FEXT2

ATT

∗

∗: Don't care

– 18 –

CXA2134Q

PONRES
STEREO
SAP
NOISE

1
1
1
1

POWER ON RESET detection; 1: RESET
Stereo discrimination of the COMPIN input signal; 1: Stereo
SAP discrimination of the COMPIN input signal; 1: SAP
Noise level discrimination of the SAP input signal; 1: Noise

Register Number of bits Contents

Description of Registers
Control registers

∗1

Classification U: User control

A: Adjustment
S: Proper to set
T: Test

Status registers

ATT
SPECTRAL
WIDEBAND
TEST-DA
TEST1
VOL-L
VOL-R
BASS
TREBLE
SURR
NRSW

FOMO
EXT1
EXT2
FEXT1

FEXT2
M1
M2
ATTSW

SAPC

4
6
6
1
1
6
6
6
6
1
1

1
1
1
1

1
1
1
1

1

A
A
A
T
T
U
U
U
U
U
U

U
U
U
U

U
U
U
S

S

Input level adjustment
Adjustment of stereo separation (3kHz)
Adjustment of stereo separation (300Hz)
DAC test mode
Test mode
Left channel volume control
Right channel volume control
Bass control
Treble control
Quasi-surround function ON/OFF
Selection of the output signal (Stereo mode, SAP mode)
Forced MONO.

(Left channel only is MONO during SAP output.)
Selection of TV mode or external input mode
Selection of external input 1 mode or external input 2

mode (EXT1 = 1)
External input 1 forced MONO
External input 2 forced MONO
Selection of TVOUT mute function ON/OFF
Selection of LSOUT mute function ON/OFF
Main VCA ON/OFF
Selection of SAP mode or L + R mode according to the

presence of SAP broadcasting

9
1F
1F

0

0
3F
3F
1F
1F

0

0

0

0

0

0

0

1

1

0

0

Register

Number
of bits

Classification

∗1

Contents

Standard
setting

– 19 –

CXA2134Q

Description of Control Registers

ATT (4): Perform input level adjustment.

0 = Level Min.
F = Level Max.

SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.

0 = Level Max.
3F = Level Min.

WIDEBAND (6):Perform low frequency (fs = 300Hz) separation adjustment.

0 = Level Min.
3F = Level Max.

TEST-DA (1):Set DAC output test mode.

0 = Normal mode
1 = DAC output test mode
In addition, the following outputs are present at Pin 39.
TVOUT-L (Pin 39): DA control DC level

TEST1 (1): Monitor SAPBPF and NRBPF outputs.

0 = Normal mode
1 = SAPBPF, NRBPF outputs
In addition, the following outputs are present at Pins 39 and 38.
TVOUT-L (Pin 39): SAP BPF OUT
TVOUT-R (Pin 38): NR BPF OUT

VOL-L (6): LSOUT-L output signal level control

0 = Volume Min.
3F= Volume Max.

–1.25 dB/STEP

VOL-R (6): LSOUT-R output signal level control

0 = Volume Min.
3F= Volume Max.

–1.25 dB/STEP

BASS (6): LSOUT output bass control

0 = Bass Min.
1F = Bass Center
3F = Bass Max.

TREBLE (6): LSOUT output treble control

0 = Treble Min.
1F = Treble Center
3F = Treble Max.

– 20 –

CXA2134Q

SURR (1): Surround function selection

0 = Surround OFF
1 = Surround ON

NRSW (1): Select stereo mode or SAP mode

0 = Stereo mode
1 = SAP mode

FOMO (1): Select forced MONO mode

0 = Normal mode
1 = Forced MONO mode

EXT1 (1): Select TV mode or external input mode for TVOUT output.

0 = TV mode
1 = External input mode

EXT2 (1): Select external input [1] mode or external input [2] mode for TVOUT output. (EXT1 = 1)

0 = External input [1] mode
1 = External input [2] mode

FEXT1 (1): Turn external input [1] to forced MONO.

0 = Normal mode
1 = External input [1] is forced MONO.

Input the same signal to both AUX1-L and AUX1-R.

FEXT2 (1): Turn external input [2] to forced MONO

0 = Normal mode
1 = External input [2] is forced MONO
Input the same signal to both AUX2-L and AUX2-R.

M1 (1): Mute the TVOUT-L and TVOUT-R output.

0 = Mute ON
1 = Mute OFF

M2 (1): Mute the LSOUT-L and LSOUT-R output.

0 = Mute ON
1 = Mute OFF

ATTSW (1) Select BYPASS SW of MVCA

0 = Normal mode
1 = MVCA is passed

SAPC (1): Select the SAP signal output mode

When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC.
0 = L + R output is selected
1 = SAP output is selected

– 21 –

CXA2134Q

Description of Mode Control

NRSW

FOMO

SAPC

“Select dbx input and TV decoder output”
Conditions: FOMO = 0

NRSW = 0 (MONO or ST output)

• During ST input: left channel: L,
right channel: R

• During other input: left channel: L + R,
right channel: L + R

NRSW = 1 (SAP output)

• When there is “SAP” during SAP

discrimination
– left channel: SAP, right channel: SAP

• When there is “No SAP”, output is the

same as when NRSW = 0.

“Select dbx input and TV decoder output”
Conditions: FOMO = 0

NRSW = 0 (MONO or ST output)
As on the left

NRSW = 1 (SAP output)

• Regardless of the presence of SAP
discrimination,
dbx input: “SAP”
left channel: SAP, right channel: SAP

However, when there is no SAP, SAPOUT
output is soft muted (–7dB)

SAPC = 0 SAPC = 1

“Forced MONO”

FOMO = 1

• During SAP output: left channel: L + R, right channel: SAP

• During ST or MONO output: left channel: L + R, right channel: L + R
Change the selection conditions for “MONO or ST output” and “SAP output”.

SAPC = 0: Switch to SAP output when there is SAP discrimination.

Do not switch to SAP output when there is no SAP discrimination.

SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.

– 22 –

CXA2134Q

Decoder Output and Mode Control Table 1 (SAPC = 1)

Note

(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).

The signal is soft muted when NOISE = 1.

∗ : Don’t care.
∗1

SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
input in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is output.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

0 0 0 0 ∗ 1 MUTE L + R L + R
0 0 0 1 0 1 SAP SAP SAP

MONO

0 0 0 1 1 1 SAP L + R SAP
0 ∗ 1 0 ∗ 1 MUTE L + R L + R
0 ∗ 1 1 0 1 (SAP) (SAP) (SAP)
0 ∗ 1 1 1 1 (SAP) L + R (SAP)
1 0 ∗ 0 0 1 L – R L R
1 0 ∗ 0 1 1 MUTE L + R L + R
1 1 1 0 0 1 L – R L R

STEREO

1 1 1 0 1 1 MUTE L + R L + R
1 0 0 1 0 1 SAP SAP SAP
1 0 0 1 1 1 SAP L + R SAP
1 ∗ 1 1 0 1 (SAP) (SAP) (SAP)
1 ∗ 1 1 1 1 (SAP) L + R (SAP)
0 1 ∗ 0 0 1 MUTE L + R L + R
0 1 ∗ 0 1 1 MUTE L + R L + R

MONO & SAP

0 1 0 1 0 1 SAP SAP SAP
0 1 0 1 1 1 SAP L + R SAP
0 1 1 1 0 1 (SAP) (SAP) (SAP)
0 1 1 1 1 1 (SAP) L + R (SAP)
1 1 ∗ 0 0 1 L – R L R
1 1 ∗ 0 1 1 MUTE L + R L + R

STEREO & SAP

1 1 0 1 0 1 SAP SAP SAP
1 1 0 1 1 1 SAP L + R SAP
1 1 1 1 0 1 (SAP) (SAP) (SAP)
1 1 1 1 1 1 (SAP) L + R (SAP)

Input signal mode

Mode detection

Mode control

dbx

input

Output

ST SAP NOISE NRSW FOMO SAPC Lch Rch

∗1

∗1

– 23 –

CXA2134Q

Decoder Output and Mode Control Table 2 (SAPC = 0)

Note

(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).

The signal is soft muted when NOISE = 1.

∗ : Don’t care.
∗1

SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
input in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is output.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

0 0 ∗ ∗ ∗ 0 MUTE L + R L + R
0 1 1 0 0 0 MUTE L + R L + R

MONO 0 1 1 0 1 0 MUTE L + R L + R

0 1 1 1 0 0 (SAP) (SAP) (SAP)
0 1 1 1 1 0 (SAP) L + R (SAP)
1 0 ∗ 0 0 0 L – R L R
1 0 ∗ 0 1 0 MUTE L + R L + R
1 0 ∗ 1 0 0 L – R L R

STEREO

1 0 ∗ 1 1 0 MUTE L + R L + R
1 1 1 0 0 0 L – R L R
1 1 1 0 1 0 MUTE L + R L + R
1 1 1 1 0 0 (SAP) (SAP) (SAP)
1 1 1 1 1 0 (SAP) L + R (SAP)
0 1 0 0 0 0 MUTE L + R L + R
0 1 0 0 1 0 MUTE L + R L + R
0 1 0 1 0 0 SAP SAP SAP

MONO & SAP

0 1 0 1 1 0 SAP L + R SAP
0 1 1 0 0 0 MUTE L + R L + R
0 1 1 0 1 0 MUTE L + R L + R
0 1 1 1 0 0 (SAP) (SAP) (SAP)
0 1 1 1 1 0 (SAP) L + R (SAP)
1 1 0 0 0 0 L – R L R
1 1 0 0 1 0 MUTE L + R L + R
1 1 0 1 0 0 SAP SAP SAP

STEREO & SAP

1 1 0 1 1 0 SAP L + R SAP
1 1 1 0 0 0 L – R L R
1 1 1 0 1 0 MUTE L + R L + R
1 1 1 1 0 0 (SAP) (SAP) (SAP)
1 1 1 1 1 0 (SAP) L + R (SAP)

Input signal mode

Mode detection

Mode control

dbx

input

Output

ST SAP NOISE NRSW FOMO SAPC Lch Rch

∗1

∗1

– 24 –

CXA2134Q

Mode Control Table 3

TV (L) / TV (R) are selected in MATRIX

TV (L): MONO, ST-L, SAP
TV (R): MONO, ST-R, SAP

EXT1

–
0
1
1
1
1

FEXT2

–
–
–
–
0
1

FEXT1

–
–
0
1
–
–

EXT2

–
–
0
0
1
1

M1

0
1
1
1
1
1

1
2
3
4
5
6

TVOUT-L

MUTE

TV (L)
AUX1-L
AUX1-L
AUX2-L
AUX2-L

TVOUT-R

MUTE
TV (R)

AUX1-R

AUX1-L

AUX2-R

AUX2-L

– 25 –

CXA2134Q

Description of Operation

The US audio multiplexing system possesses the base-band spectrum shown in Fig. 1.

Fig. 1. Base-band spectrum

Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)

Fig 3. dbx-TV block

PEAK DEV

kHz

50

25

25

L + R

50 – 15kHz

L-R

dbx-TV

NR

50

AM-DSB-SC

SAP

dbx-TV NR

FM 10kHz

50 – 10kHz

TELEMETRY

FM 3kHz

15

f

H = 15.734kHz

f

H 2fH 3fH 4fH 5fH 6fH 6.5fH

f

5

PILOT

3

(COMPIN)

STEREO LPF

PLL

(VCO 8f

H)

2f

HL0°

f

HL90°

f

HL0°

MODE
CONTROL

PILOT

DET

MVCA

PILOT

CANCEL

MAIN LPF DE.EM

(MAIN OUT)

L + R

4.7µ

(MAIN IN)

L-R (DSB)

DET

INJ.

LOCK

SUBVCA

SUB LPF

WIDEBAND

(SUBOUT)

(ST IN)

4.7µ
NR SW

dbx-TV

BLOCK

MATRIX

(Lch)

(Rch)

MODE

CONTROL

(SAP IN)

4.7µ

SAP(FM)

DET

SAP LPF

MODE
CONTROL

SAP BPF

(SAP OUT)

L – R

to
TVSW

NOISE

DET

I2C BUS
DECODER

SAP
DET

A B

I2C BUS
DECODER

I

2

C BUS

DECODER

13

9

8

21

22

24

25

NR SW

FIXED

DEEMPHASIS

VARIABLE

DEEMPHASIS

(VE OUT) (VCA IN)

to
MATRIX

4.7µ

HPF

LPF

LPF

RMS
DET

RMS

DET

VCA

A B

(ST IN)

(SAP IN)

22

25

29

30

– 26 –

CXA2134Q

Fig. 4. Sound processor block

(1) L + R (MAIN)

After the audio multiplexing signal input from COMPIN (Pin 13) passes through MVCA, the SAP signal
and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the
L – R signal and SAP signal are removed by MAIN LPF, and the frequency response is flattened (de­emphasized) and input to the matrix.

(2) L – R (SUB)

The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.

(3) SAP

SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency response flattened using SAP LPF, and the SAP signal is
input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 24 output is soft
muted.

(4) Mode discrimination

Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.

(Lch) (Rch)

(AUX1-L)

(AUX1-R)

from MATRIX

SURROUND

BASS

TREBLE

(LSOUT-L)

(LSOUT-R)

(TVOUT-L) (TVOUT-R)

TVSW

(AUX2-L) (AUX2-R)

VOL-L

VOL-R

33

34

37

36

39

38

1

44

48

43

3

4

(VOLIN-L)

(VOLIN-R)

(TOUT-L)

(TOUT-R)

4.7µ

4.7µ

– 27 –

CXA2134Q

(5) dbx-TV block

Either the L – R signal or SAP signal input respectively from ST IN (Pin 22) or SAP IN (Pin 25) is
selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de­emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.

(6) Matrix, TVSW

The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the BUS data and whether there is ST / SAP discrimination.
“TVSW” switches the “MATRIX” output signal, external input signal (input to AUX1-L, R), external input
signal (input to AUX2-L, R) and external forced MONO.

(7) Sound processor block

The sound processor block contains "SURROUND" (quasi-surround function), “BASS/TREBLE” tone
control functions, and “VOLUME”.

• Surround
At "SURROUND", the L and R differential components are phase-shifted and these components are
added to the left and right channels.
When surround is OFF (SURR = 0)
Inputs are output as is.

Lout = Lin
Rout = Rin

When surround is ON (SURR = 1)

Lout = Lin – (Lin – Rin)

Rout = Rin + (Lin – Rin)

R = 24kΩ (On-chip)
C = 0.022µF (Externally attached to Pin 40)

(Lin, Lout) and Rin, (Rout) indicate the left- and right- channel I/O of the surround circuit.

(8) Others

“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 15) with GND become the reference current.

1 – jωRC
1 + jωRC

1 – jωRC
1 + jωRC

{

{

{

– 28 –

CXA2134Q

Application Circuit

3.3k3k

2700p

0.047µ

4.7µ

3.9k

1µ

4.7µ

0.022µ

4.7µ

4.7µ

4.7µ

4.7µ

220 220

1MEG

5600P

100k 0.012µ

DGND

4.7µ

4.7µ

+9V

GND

10µ

62k ± 1%
METAL

4.7µ

100µ

4.7µ

4.7µ

1µ

0.1µ 4.7µ 4.7µ

4700p

4.7µ

4700p

0.1µ

4.7µ 4.7µ4.7µ

AUX1 input

25

262728

29

30

36

35

34

31

32

33

AUX2-R

NC

AUX1-L

AUX1-R

VCAWGT

VCATC

VCAIN

VEOUT

VETC

VEWGT

VE

SAPIN

2

3

4

5

6

7

8

9

10

11

12

1

TOUT-L

BASS-L

LSOUT-R

SDA

SCL

DGND

PLINT

PCINT1

MAINOUT

MAININ

LSOUT-L

PCINT2

13

14

15

16

17

18

19

20

21

22

23

24

COMPIN

VGR

NC

GND

SAPTC

NC

STIN

NOISETC

IREF

V

CC

SAPOUT

SUBOUT

40

39

38

37

41

42

43

44

45

46

47

48

VOLIN-L

TRE-L

NC

BASS-R

SURRTC

TOUT-R

NC

TRE-R

TVOUT-L

TVOUT-R

AUX2-L

VOLIN-R

AUX2 input

TVOUT
output

LS output µ-com

Composite
baseband
signal input

10µ
TANTALUM

3.3µ

TANTALUM

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 29 –

CXA2134Q

I2C Bus Block Items (SDA, SCL)

I2C bus load conditions: Pull-up resistor 4kΩ (Connect to +5V)

Load capacitor 200pF (Connect to GND)

I2C Bus Control Signal

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

High level input voltage
Low level input voltage
High level input current
Low level input current
Low level output voltage SDA (Pin 5) during 3mA inflow
Maximum inflow current
Input capacitance
Maximum clock frequency
Minimum waiting time for data change
Minimum waiting time for start of data transfer
Low level clock pulse width
High level clock pulse width
Minimum waiting time for start preparation
Minimum data hold time
Minimum data preparation time
Rise time
Fall time
Minimum waiting time for stop preparation

VIH
VIL
IIH
IIL
VOL
IOL
CI
fSCL
tBUF
tHD: STA
tLOW
tHIGH
tSU: STA
tHD: DAT
tSU: DAT
tR
tF
tSU: STO

3.0
0

—
—

0
3

—

0

4.7

4.0

4.7

4.0

4.7
0

250

—
—

4.7

—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—

5.0

1.5
10
10

0.4
—
10

100

—
—
—
—
—
—
—

1

300

—

V

µA

V

mA

pF

kHz

µs

ns
µs
ns
µs

SDA

SCL

tBUF

P

S

t

HD: STA

t

LOW

tHD: DAT

t

HIGH

tR

tF

tHD: STA

t

SU: STA

Sr

t

SU: STO

P

t

SU: DAT

No. Item Symbol Min. Typ. Max. Unit

– 30 –

CXA2134Q

I2C Bus Signal

There are two I2C bus signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional
signal.

• Accordingly there are 3 values outputs, H, L and Hi-Z.

• I2C transfer begins with Start Condition and ends with Stop Condition.

SDA

SCL

Start Condition S Stop Condition P

H L Hi-Z L

– 31 –

CXA2134Q

• I2C data Write (Write from I2C controller to the IC)

∗

Data can be transferred in 8-bit units to be
set as required.
Sub address is incremented automatically.

• I2C data Read (Read from the IC to I2C controller)

• Read timing

∗

Data Read is performed during SCL rise.

S

Address

1 6 7 8 9 1 8 9

SCL

ACK DATA ACK

SDA

High during Read

Hi-Z

7

P

DATA

1 2 3 4 5 6 7 89 9

IC output SDA

SCL

MSB

LSB

ACK ACK

Read timing

ACKACKDATA DATA

P

8 9 1 8 9

Hi-Z Hi-Z

DATA (n) DATA (n + 1)ACK

1 8

9

1 8 9

ACK DATA (n + 2)

Hi-Z Hi-Z

LSBMSB

S

Address

1 2 3 4 5 6 7 8 9 1 8 9

SDA

SCL

MSB

Low during Write

MSB LSB

Hi-Z Hi-Z

ACK Sub Address ACK

– 32 –

CXA2134Q

Input level vs. Distortion characteristics 1 (MONO)

1.0

0.1

–10 0 10

Input level vs. Distortion characteristics 2 (Stereo)

THD – Distortion [%]

10

1.0

–10 0 10

Input level [dB]

Input signal: Stereo L = –R
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
V

CC = 9V, 30kHz using LPF, ST mode

Measurement point: TVOUT-L/R

Input level vs. Distortion characteristics 3 (SAP)

10

1.0

–10 0 10

Input level [dB]

Input level [dB]

Standard level (100%)

Standard level (100%)

Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB = 100% modulation
level
V

CC = 9V, 30kHz using LPF, SAP mode

Measurement point: TVOUT-L/R

Standard level (100%)

Input signal: MONO (Pre-emphasis on), 1kHz
0dB = 100% modulation level
V

CC = 9V, 30kHz using LPF

Measurement point: TVOUT-L/R

THD – Distortion [%]

THD – Distortion [%]

– 33 –

CXA2134Q

Frequency [kHz]

Gain [dB]

Stereo LPF frequency response

10

5

0

–5

–10

0 20 40 60 80 100

30

10

0

–20

–50

1 2 5 10 20 507 70 100

–40

–30

–10

20

Gain (FC main and FC sub) [dB]

10

0

–20

20 40 60 80 100 120

–10

20

SAP frequency response and group delay

Group delay [µs]

100

90
80
70
60
50
40

10

20

0

30

5fH

Gain

Group delay

3.8fH

6.2fH

Frequency [kHz]

Frequency [kHz]

Main LPF and Sub LPF frequency response

Gain [dB]

– 34 –

CXA2134Q

0 F 1F

Control data VOL-L, VOL-R

2F 3F

Input: AUX1, 2

1kHz, 490mVrms

Output: LSOUT

0

–20

–40

–60

–80

–100

LSOUT output level [dB]

Volume characteristics

– 35 –

CXA2134Q

Package Outline Unit: mm

SONY CODE
EIAJ CODE
JEDEC CODE

M

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER / PALLADIUM
PLATING

42/COPPER ALLOY

48PIN QFP (PLASTIC)

15.3 ± 0.4

12.0 – 0.1

+ 0.4

0.8

0.3 – 0.1

+ 0.15

0.24

13

24

2536

37

48

1 12

2.2 – 0.15

+ 0.35

0.9 ± 0.2

0.1 – 0.1

+ 0.2

13.5

0.15 – 0.05

+ 0.1

QFP-48P-L04
QFP048-P-1212

0.7g

0.15

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).