Page 1
Description
The CXA1998BQ is an IC developed for analog
signal processing in tape recorders. Processing for
both the recording and playback systems is
achieved on one chip.
Features
• 11-bit serial data interface
• Recording/playback mute function
• Recording equalizer Gp and Fp can be adjusted
externally.
• AGC (Automatic Gain Control)
• Comparator for AMS (Automatic Music Sensor)
• Recording/playback equalizer amplifier with 1.7
times speed switching
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VCC, VDD 12 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation
PD 645 mW
Operating Conditions
Supply voltage VCC 6.5 to 10.0 V
VDD 4.5 to 5.5 V
Structure
Bipolar silicon monolithic IC
Applications
All analog signal processing in the cassette decks
of tape recorders and compact music centers
Applicable Head
Applicable to MITSUMI ELECTRIC Co., Ltd.
Playback head: BP-7442-CP-6973
Recording/playback head: BC-9242-CB-9267
– 1 –
CXA1998BQ
E98Z31-PS
Recording/Playback Equalizer Amplifier
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
48 pin QFP (Plastic)
Page 2
– 2 –
CXA1998BQ
Block Diagram and Pin Configuration (Top View)
D1
D2
D3
D4
D5
D6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
37
38
39
40
41
42
43
44
45
46
47
48
MUTE
AGC GAIN 19.5dB
10k
40k
RECEQ
AMS
GND
GND
GND
V
DD
VDD
20k 20k
20k20k
D11
D9
D10
D8
GND
D7
GND
D11
GND
D9
GND
GND
GND
GND
GND
GND
VDD
GND
40k
AGC GAIN 19.5dB
10k
RECEQ
IREF
36
35
34
33
GND
RFS
2.8V
210k
GND
GND
210k
GND
210k
210k
GND
2.8V
AGC
AGC OFF
A EQ
B EQ
PBEQ CTLRECEQ CTL
DECK A/B
SPEED
SHIFT REGISTERS
LATCHES
GP CAL
A EQ
B EQ
AGC TC
AGC IN1
REC IN1
AGC OUT1
REC OUT1
AMS GAIN
AMS GND
AMS TC
AMS OUT
PBMUTE
RMUTEI
RMUTE
SPEED
BPA
BPB
PL1
PL2
M1
M2
V
DD
LATCH
RFC
Vcc
VG
GND
AGC IN2
REC IN2
AGC OUT2
REC OUT2
DGND
XRESET
DATA
CLK
FP CAL
PB OUT1
PB FB21
PB FB11
PB INB1
PB INA1
PB INA2
PB INB2
PB FB12
PB FB22
PB OUT2
IREF
Page 3
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CXA1998BQ
Pin Description
Pin
No.
1
Symbol
DC
voltage
I/O Equivalent circuit Description
GP CAL
1.2V —
Connects a resistor
for determining the
high-band peak gain
of recording equalizer.
Reference setting
resistance is 27kΩ.
I/O
resistance
—
2
A EQ
— I
Deck A equalizer
switch.
Low: 120µs EQ
High: 70µs EQ
—
3
B EQ
2.5V
(OPEN)
I
Deck B equalizer
switch.
Low: NORMAL TAPE,
120µs EQ
Medium: Cro2 TAPE,
70µs EQ
High: METAL TAPE,
70µs EQ
53kΩ
4
AGC TC
0.0V
—
Connects a resistor
and capacitor for
determining AGC
attack/recovery time
constants.
—
1
Vcc
Vcc
GND GND
147
× 2
30k
VCC
147
GND
GND
VCC
2
VCC
147 50k
V
CC
GND
GND
5k
5k
3
VCC
GND
GND
VCC
× 2
200
100k
500
500
× 2
147
× 2
× 4
200
5k
4
(Ta = 25°C, VCC = 8V, VDD = 5V, no signal, RESET ON)
Page 4
– 4 –
CXA1998BQ
5
32
AGC IN1
AGC IN2
4.0V I
AGC signal input.
Input resistance
changes between
50kΩ and 100kΩ.
AGC functions when
the signal of –30dBm
or more is input to
AGC for AGC ON.
(External 47µF//300kΩ
for Pin 4)
50kΩ
6
31
REC IN1
REC IN2
4.0V I
Recording equalizer
input.
50kΩ
7
30
AGC OUT1
AGC OUT2
4.0V O AGC output.147Ω
8
29
REC OUT1
REC OUT2
4.0V O
Recording equalizer
output.
147Ω
VCC
147
40k
500
× 10
V
CC
GND
GND
× 3
500
× 2
5p
8
29
VCC
147
18752
500
× 4
V
CC
GND
VGS
GND
× 2
500
7
30
107423
9945
VGS
VCC
147
50k
V
CC
GND
VGS
23186
1759
VGS
GND
6
31
VCC
147 10k
40k
× 4
V
CC
GND
VGS
5
32
Pin
No.
Symbol
DC
voltage
I/O Equivalent circuit Description
I/O
resistance
Page 5
– 5 –
CXA1998BQ
AMS block ground.
9
AMS GAIN
3.5V —
Connects a resistor
for determining AMS
signal detection level
and a capacitor for
determining HPF cutoff frequency.
—
10
AMS GND
0.0V
— —
12
AMS OUT
8.0V
O
AMS output.
No signal detection:
High
Signal detection: Low
—
11
AMS TC
8.0V —
Connects time
constant for AMS
detection.
—
VCC
147
GND
VCC
GND
100k
10µ
9
11
Vcc
GND
1k
GND
147
VccVcc
GND
Vcc
12
Vcc
Vcc
10k
GND
10
GND
Pin
No.
Symbol
DC
voltage
I/O Equivalent circuit Description
I/O
resistance
Page 6
– 6 –
CXA1998BQ
13
PBMUTE
14
RMUTE1
5.0V —
Connects a capacitor
for setting time
constant for playback
mute ON/OFF
switching.
—
15
RMUTE
Output for recording
mute ON/OFF switch
control signal. Outputs
D11 from Pin 26
(DATA).
16
SPEED
5.0V
O
Output for
recording/playback
equalizer speed switch
control signal. Outputs
D9 from Pin 26 (DATA).
Low: Normal Speed
High: High Speed
(1.7 times)
—
17
BPA
5.0V O
Outputs D6 from
Pin 26 (DATA).
18
BPB
Outputs D5 from
Pin 26 (DATA).
19
PL1
Outputs D4 from
Pin 26 (DATA).
20
PL2
Outputs D3 from
Pin 26 (DATA).
21
M1
Outputs D2 from
Pin 26 (DATA).
22
M2
Outputs D1 from
Pin 26 (DATA).
23
VDD
Power supply of serial
data interface block.
—
5.0V
—
—
13
14
VDD
VDD
20k
20k
GND
× 4
147
GND
GND
Connects a capacitor
for setting time
constant for recording
mute ON/OFF
switching.
× 4
VDD
5k
GND
GND
VDD
× 4
5k
20k
15
16
× 4
VDD
GND
GND
VDD
× 4
10k
20k
17
18
19
20
21
22
VDD
23
Pin
No.
Symbol
DC
voltage
I/O Equivalent circuit Description
I/O
resistance
Page 7
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CXA1998BQ
24
LATCH
27
XRESET
— I
Serial data interface
latch input.
—
25
DATA
—
I
Serial data interface
reset input.
Low: Reset.
At this time serial
data outputs
(Pins 15 to 22)
are all open
(high).
—
26
Serial data interface
clock input.
Serial data interface
serial data input.
28
DGND
0.0V
—
Serial data interface
block ground.
—
CLK
2k
GND
VDD
10.5k
25µA
GND
30k
5p
× 4
30k
24
27
4k
GND
VDD
10.5k
25µA
GND
30k
× 4
30k
25
26
GND
28
33
GND
0.0V
—
Ground.
—
35
VCC
8.0V — Power supply.—
34
VG
4.0V —
Signal reference
voltage. Connects a
capacitor for ripple
rejection.
60kΩ
GND
33
34
VCC
147
45k
30k
× 4
V
CC
GND
GND
500
500
× 2
30k
× 2
To each VGS
35
VCC
Pin
No.
Symbol
DC
voltage
I/O Equivalent circuit Description
I/O
resistance
Page 8
– 8 –
CXA1998BQ
Connects a resistor
(12kΩ) for determining
equalizer gains.
36
RFC
8.0V —
Connects a resistor
and capacitor for
obtaining stable
voltage with power
supply ripple rejected.
—
37
IREF
38
47
PB OUT2
PB OUT1
2.8V O
Playback equalizer
output.
147Ω
48 FP CAL
1.2V —
Connects a resistor for
determining the highband peak frequency
of recording equalizer.
Reference setting
resistance is 27kΩ.
—
36
VCC
147
V
CC
GND
× 3
× 250
× 3
To each RFS
Vcc
GND
× 2
GND
37
48
147
5p
Vcc
Vcc
GND
Vcc
× 3
500
147
× 6
GND
15p
47
38
500
39
46
PB FB22
PB FB21
2.8V —
Connects a capacitor
for determining
playback equalizer
time constants, such
as 120µs and 70µs.
—
39
46
VCC
147
× 3
GND
2k2k
GND GND
× 4
7k
× 3
× 4
RFS
Pin
No.
Symbol
DC
voltage
I/O Equivalent circuit Description
I/O
resistance
Page 9
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CXA1998BQ
40
45
PB FB12
PB FB11
1.4V —
Playback equalizer
negative feedback.
105kΩ
41
42
43
44
PB INB2
PB INA2
PB INA1
PB INB1
0.0V I
Playback equalizer
input.
70kΩ
41
42
43
44
45
70k
10p
VCC
GND
VCC
GND
× 6
VCC
40
GND
1k
1k
210k
210k
VCC
RFS
× 2
10k
5k
× 6
147
30p
147
Note)
• AMS GND (Pin 10), DGND (Pin 28) and GND (Pin 33) are each independent in the IC and are not connected.
Be sure tp ground each of the ground pins listed above.
• The resistance of open collector outputs (Pins 15 to 22) can be connected Vcc.
Pin
No.
Symbol
DC
voltage
I/O Equivalent circuit Description
I/O
resistance
Page 10
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CXA1998BQ
Electrical Characteristics
(Ta = 25°C, VCC = 8.0V, VDD = 5.0V, refer to Electrical Characteristics Measurement Circuit)
Item
Operating voltage
Current consumption
Measurement conditions Min. Typ. Max. Unit
VCC
VDD
Sum of VCC and VDD pin currents
NORM – NS, no signal
Pin 4 external R300kΩ//C47µF
f = 1kHz, Vin = –25dBm
Pin 4 external R300kΩ//C47µF
f = 1kHz, Vin = –25dBm
Pin 4 external R300kΩ//C47µF
f = 1kHz, Vin = 0dBm
Pin 4 external R300kΩ//C 47µF
f = 1kHz, Vin = –25dBm
Pin 9 external R9.1kΩ, C0.015µF
Pin 11 external R100kΩ//C0.1µF
f = 5kHz, 0dB = –21dBm
(at PBEQ reference output level)
f = 315Hz, Vin = –70dBm
Reference for frequency response
f = 2.7kHz, Vin = –58.5dBm
at 120µs – NS, 315Hz
f = 4.5kHz, Vin = –53.8dBm
at 120µs – NS, 315Hz
f = 5.3kHz, Vin = –52.5dBm
at 120µs – NS, 315Hz
f = 9.1kHz, Vin = –47.8dBm
at 120µs – NS, 315Hz
120µs – NS, RL = 2.7kΩ
f = 1kHz, THD + N = 1%
120µs – NS, RL = 2.7kΩ
f = 1kHz, Vin = –56.0dBm
120µs – NS, Rg = 470Ω
“A” weighting filter
120µs – NS, Rg = 470Ω, playback mute OFF
120µs – NS, f = 1kHz, Vin = –51.0dBm
AGC ON
output level
AGC ON
channel balance
AGC ON distortion
AGC OFF
output level
No signal detection
threshold level
120µs – NS
frequency response
120µs – NS
frequency response
70µs – NS
frequency response
120µs – HS
frequency response
70µs – HS
frequency response
Signal handling
Total harmonic
distortion
S/N ratio
Output offset voltage
Playback mute
characteristics
6.5
4.5
13.5
–13.0
–2.0
—
–7.5
–11.5
–23.0
–0.6
–1.2
1.8
2.1
–10.0
—
55.0
2.4
—
8.0
5.0
19.7
–11.0
0.0
0.3
–5.5
–8.2
–21.0
0.8
0.6
3.0
3.6
–6.0
0.3
62.0
2.7
–100
10.0
5.5
25.0
–9.0
2.0
1.5
–3.5
—
–19.0
2.4
1.8
4.8
5.1
—
0.7
—
3.2
–80
V
V
mA
dBm
dB
%
dBm
dB
dBm
dB
dBm
%
dB
V
dB
AGCAMSPlayback equalizer amplifier block
Page 11
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CXA1998BQ
Reference input level
Reference output level
Channel balance
NORM – NS
frequency response
NORM – NS
frequency response
NORM – NS
frequency response
CrO2 – NS
frequency response
CrO2 – NS
frequency response
CrO2 – NS
frequency response
METAL – NS
frequency response
METAL – NS
frequency response
METAL – NS
frequency response
NORM – HS
frequency response
NORM – HS
frequency response
NORM – HS
frequency response
CrO2 – HS
frequency response
CrO2 – HS
frequency response
CrO2 – HS
frequency response
METAL – HS
frequency response
METAL – HS
frequency response
METAL – HS
frequency response
dB
NORM – NS, 315Hz, input level at which
reference output can be obtained
NORM – NS, 315Hz
NORM – NS, 315Hz, output level
difference 1ch-2ch for –27.7dBm input
f = 3kHz at NORM – NS,
315Hz, reference output –20dB
f = 8kHz at NORM – NS,
315Hz, reference output –20dB
f = 12kHz at NORM – NS,
315Hz, reference output –20dB
f = 3kHz at NORM – NS,
315Hz, reference output –20dB
f = 8kHz at NORM – NS,
315Hz, reference output –20dB
f = 12kHz at NORM – NS,
315Hz, reference output –20dB
f = 3kHz at NORM – NS,
315Hz, reference output –20dB
f = 8kHz at NORM – NS,
315Hz, reference output –20dB
f = 12kHz at NORM – NS,
315Hz, reference output –20dB
f = 5kHz at NORM – NS,
315Hz, reference output –20dB
f = 15kHz at NORM – NS,
315Hz, reference output –20dB
f = 20kHz at NORM – NS,
315Hz, reference output –20dB
f = 5kHz at NORM – NS,
315Hz, reference output –20dB
f = 15kHz at NORM – NS,
315Hz, reference output –20dB
f = 20kHz at NORM – NS,
315Hz, reference output –20dB
f = 5kHz at NORM – NS,
315Hz, reference output –20dB
f = 15kHz at NORM – NS,
315Hz, reference output –20dB
f = 20kHz at NORM – NS,
315Hz, reference output –20dB
–27.7
–10.0
0.0
–1.7
3.5
10.2
3.2
9.0
15.8
4.0
8.1
12.8
–0.8
8.7
13.9
5.4
15.2
18.7
7.0
14.5
18.4
–29.2
—
–1.5
–2.9
2.1
7.6
1.9
7.1
12.5
2.8
6.7
10.9
–2.6
6.6
10.9
4.2
13.1
15.7
5.8
12.7
15.9
–26.2
—
1.5
–0.5
5.7
14.6
4.3
11.1
21.0
5.2
9.7
15.9
1.2
10.8
16.4
6.6
17.3
21.7
8.2
16.3
20.9
dBm
Recording equalizer amplifier block
Item Measurement conditions Min. Typ. Max. Unit
Page 12
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CXA1998BQ
NORM – NS, RL = 2.7kΩ
f = 1kHz, THD + N = 1%
NORM – NS, RL = 2.7kΩ
f = 1kHz, 0dB
NORM – NS, Rg = 5.1kΩ
“A” weighting filter
NORM – NS
NORM – NS, f = 1kHz
8dB
A-EQ (Pin 2)
A-EQ (Pin 2)
B-EQ (Pin 3)
B-EQ (Pin 3)
B-EQ (Pin 3)
Signal handling
Total harmonic
distortion
S/N ratio
Output offset voltage
Recording mute
characteristics
8.0
—
57.0
3.6
—
0.0
2.5
0.0
2.2
4.2
8.8
0.2
60.6
4.0
–100
—
—
—
—
—
—
0.5
—
4.4
–80
0.5
VCC
0.5
2.8
VCC
dB
%
dB
V
Control voltage
low level 1
Control voltage
high level 1
Control voltage
low level 2
Control voltage
medium level 1
Control voltage
high level 2
Note) NORM – NS: NORMAL TAPE – NORMAL SPEED
NORM – HS: NORMAL TAPE – HIGH SPEED
CrO2 – NS: CrO2 TAPE – NORMAL SPEED
CrO2 – HS: CrO2 TAPE – HIGH SPEED
METAL – NS: METAL TAPE – NORMAL SPEED
METAL – HS: METAL TAPE – HIGH SPEED
120µs – NS: EQ = 120µs – NORMAL SPEED
120µs – HS: EQ = 120µs – HIGH SPEED
70µs – NS: EQ = 70µs – NORMAL SPEED
70µs – HS: EQ = 70µs – HIGH SPEED
dB
V
Recording equalizer amplifier block
Item Measurement conditions Min. Typ. Max. Unit
Page 13
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CXA1998BQ
VIL (LATCH/CLK/DATA/XRESET)
(Pins 24, 25, 26, 27)
VIH (LATCH/CLK/DATA/XRESET)
(Pins 24, 25, 26, 27)
VOL, IOL = 2mA (max)
(Pins 15, 16, 17, 18, 19, 20, 21, 22)
IOZ Leak current which flows to the output
pin when IOZ output is open; applied
voltage is 10V. (Pins 15 to 22)
(1) fCK
(2) tWC
(3) tWR
(4) tSDK (DATA → CLK)
(5) tHCD (CLK → DATA)
(6) tWD
(7) tSLD (LATCH → DATA)
(8) tHCL (CLK → LATCH)
(9) tHLC (LATCH → CLK)
Low level
input voltage
High level
input voltage
Low level
output voltage
High level output
off leak current
Maximum clock
frequency
Minimum clock
pulse width
Minimum reset
pulse width
Minimum data
setup time
Minimum data
hold time
Minimum data
pulse width
Minimum latch
setup time
Minimum latch
hold time
Minimum clock
hold time
0.0
3.5
0.0
—
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
VDD
0.5
1.0
—
1.0
1.0
1.0
1.0
2.0
1.0
1.0
1.0
Note)
• VDD is CPU supply voltage of 5.0V.
• VCC is 10.0V for high level output off-leak current.
• The threshold levels of low level input voltage and high level input voltage depend on VDD. Input level
detection is done by comparison with VDD/2. (Refer to “Equivalent circuit” of Pin Description.)
µs
V
µA
kHz
Item Measurement conditions Min. Typ. Max. Unit
11-bit serial data interface block
Page 14
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CXA1998BQ
Timing Chart for 11-bit Serial Data Interface (VDD = 5.0V)
tWCtWC
tWD
tHCD
tSDK
1.5V
3.5V
D1 D2
1.5V
3.5V
1.5V
tSLD
3.5V
1.5V
3.5V
1.5V
t
HCL
D10 D11
t
HLC
tWR
CLK
DATA
LATCH
CLK
DATA
LATCH
XRESET
Page 15
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CXA1998BQ
Electrical Characteristics
Measurement Circuit
6
7
8
11
12
13
14
15
16
17
18
19
20
21
22
24
25
262728
29
30
31
37
39
46
47
48
36
35
34
GP CAL
A EQ
B EQ
AGC TC
AGC IN1
REC IN1
AGC OUT1
REC OUT1
AMS GAIN
AMS GND
AMS TC
AMS OUT
PBMUTE
RMUTEI
RMUTE
SPEED
BPA
BPB
PL1
PL2
M1
M2
V
DD
LATCH
RFC
Vcc
VG
GND
AGC IN2
REC IN2
AGC OUT2
REC OUT2
DGND
XRESET
DATA
CLK
FP CAL
PB OUT1
PB FB21
PB FB11
PB INB1
PB INA1
PB INA2
PB INB2
PB FB12
PB FB22
PB OUT2
IREF
R114
10k
R103
2.2k
S36A
S36B
R113
10k
R102
2.2k
S35A
S35B
R112
10k
R101
2.2k
S34A
S34B
R111
R100
2.2k
S33B
R110
R99
2.2k
S32B
R109
R98
2.2k
S31B
10k
S33A
10k
S32A
10k S31A
R108
R97
2.2k
S30B
10k
S30A
R107
R96
2.2k
S29B
10k S29A
R106
C34
0.1
µ
S57A
10k
S53
R105
S57B
10k
S54
C33
0.1
µ
S56B
S56A
S58H
S58G
S58F
S58E
S58D
S58C
S58B
S58A
23
5V 5V
LATCH
2.2
µ/25V
C30
2.7k
R86
S12D
4.7µ/25V
C28
10k
R79
0.47
µ/50V
C26
0.47
µ/50V
C22
10k
R89
S27B
100
R84
S27A
100
R81
S21B
R76 390k
R72 47k
S21A
5.1k
32
33
10k
R61
47µ/25V
C18
8V
47
µ/25V
C17
47
µ/25V
C15
1k
R5B
S15
CLK
DATA
XRESET
38
40
100
R44
47µ/25V
C10
4.7k
R37
470
R50
41
0.018µ
C14
1µ
C9
4.7µ/25V
C4
82k
R35
470
R49
1µ
C8
4.7µ/25V
C3
82k
R34
470
R48
1µ
C7
4.7µ/25V
C2
82k
R33
470
R47
1µ
C6
4.7µ/25V
C1
82k
R32
42
43
44
100
R43
47
µ/25V
C5
4.7k
R36
0.018µ
C13
45
2.2µ/25V
C11
2.7k
R38
S12B
27k
R42
2.2µ/25V
2.7k
S12A
12k
R45
100
R41
S11A
10k
R52
S11B
2.2
µ/25V
C29
2.7k
R85
S12C
10k
R88
S26B
100
R83
S26A
4.7
µ/25V
C27
10k
R78
S22B
0.47µ
/25V
C25
R74
S25B
R73 390k
R71 47k
R80 100
0.47
µ/50V
C21
5.1k
S22A
5.1k
R68
300k
R66
4
5
47
µ/25V
C20
3
S20
S19
S18
METAL
CrO2
NORM
10k
R63
10k
R59
2
4.2V2.5V0.5V
27k
R56
1
9.1k
R90
0.015
µ
C31
9
10
0.1
µ
C32
100k
R92
100k
R93
10k
R94
S28
GND
DC OUTPUT
TL072
+
–
600
R30
ATT
S5BS5A
–6dB
ATT
S4BS4A
–9dB
ATT
S3BS3A
–17dB
ATT
S2BS2A
–29dB
ATT
S1BS1A
–40dB
AC INPUT
CHARGE1
CHARGE2
10k
R51
100
R40
S10B
S10A
1kHz Band Pass Filter (20dB)
Audio (22.2Hz – 22.2kHz) Filter
"A" Weighting Filter
30dB AMP
BUF
S505
S504
S503
S502
S501
AC OUTPUT
100k
R536
GND
4.7k
R54
10k
R64
S16
5.1k
R69
C24 0.1
µ
S25A
R75
C23 0.1
µ
S14
R39 C12
0.1
µ
C16
120
µs
70µs
S9
S8
S7
S6
S13
S55
S23
0.1
µ
C19
B EQ
A EQ
S17
S37
S24
Page 16
– 16 –
CXA1998BQ
Application Circuit
GP CAL
A EQ
B EQ
AGC TC
AGC IN1
REC IN1
AGC OUT1
REC OUT1
AMS GAIN
AMS GND
AMS TC
AMS OUT
PBMUTE
RMUTEI
RMUTE
SPEED
BPA
BPB
PL1
PL2
M1
M2
V
DD
LATCH
RFC
Vcc
VG
GND
AGC IN2
REC IN2
AGC OUT2
REC OUT2
DGND
XRESET
DATA
CLK
FP CAL
PB OUT1
PB FB21
PB FB11
PB INB1
PB INA1
PB INA2
PB INB2
PB FB12
PB FB22
PB OUT2
IREF
VDD
100k
VDD
VDD
47k
VDD
47k
VDD
47k
VDD
47k
VDD
47k
VDD
47k
VDD
47k
VDD
47k
GND
0.1µ
GND
22µ
100k
100k
0.1µ
2.2k
0.1µ
GND
27k
VCC
3.3meg
47µ
0.47µ
0.1µ
2.7k
4.7µ
10k
2.2µ
2.2µ
10k
GND
GND
GND GND
V
CC VCC
GND
27k
47µ
100
GND
0.018µ
47µ
100
GND
0.018µ
2.2µ
10k
GND
GND
12k
100k
GND
100k
GND
100k
GND
V
DD
2.2µ
GND
2.2µ
GND
0.1µ
2.7k
4.7µ
10k
0.47µ
GNDGND
47µ
GND
47µ
GND
100µ
1k
VCC
Bias
OSC
GND
DECK-A
PB-HEAD
GND
GND
R/P-HEAD
DECK-B
GND
150p
820p
10k
180p
12mH
GND
150p
180p
12mH
820p
10k
D1
D2
D3
D4
D5
D6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
37
38
39
40
41
42
43
44
45
46
47
48
MUTE
AGC GAIN 19.5dB
10k
40k
RECEQ
AMS
GND
GND
GND
V
DD
VDD
20k 20k
20k20k
D11
D9
D10
D8
GND
D7
GND
D11
GND
D9
GND
GND
GND
GND
GND
GND
VDD
GND
40k
AGC GAIN 19.5dB
10k
RECEQ
IREF
36
35
34
33
GND
RFS
2.8V
210k
GND
GND
210k
GND
210k
210k
GND
2.8V
AGC
AGC OFF
A EQ
B EQ
PBEQ CTLRECEQ CTL
DECK A/B
SPEED
SHIFT REGISTERS
LATCHES
REC PB
REC PB
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 17
– 17 –
CXA1998BQ
1. System control mode
Playback and recording equalizer
(1) Playback equalizer (120µs/70µs)
DECK-AB
(serial data
D10 (Pin 25))
A-EQ (Pin 2) B-EQ (Pin 3)
L H L M/H
L
H
120µs
(DECK A)
70µs
(DECK A)
According to A-EQ control
120µs
(DECK B)
70µs
(DECK B)
According to B-EQ control
(3) Recording equalizer (Normal, CrO2, Metal)
B-EQ (Pin 3)
REC MODE
L
NORMAL (TYPE I)
M
CrO2 (TYPE II)
H
METAL (TYPE IV)
(4) Recording mute (Pin 14)
ON/OFF control is performed by 11-bit serial data interface D11 (Pin 26). A fader function is achieved using a
time constant circuit formed with the external capacitor and incorporated 20kΩ resistor.
(5) FP CAL (Pin 48)
The standard resistor setting is 27kΩ, but when resistance value is larger, fo (Hz) is lower, and when
resistance value is smaller, fo (Hz) is higher. (fo: high-band peak frequency)
(6) GP CAL (Pin 1)
The standard resistor setting is 27kΩ, but when resistance value is larger, high-band peak gain is larger, and
when resistance value is smaller, high-band peak gain is smaller.
(2) Playback mute (Pin 13)
ON/OFF control is performed by 11-bit serial data interface D7 (Pin 26). A capacitor for setting the switching
time constant is connected.
Time constant = 20kΩ × C
Page 18
– 18 –
CXA1998BQ
2. 11-bit serial data interface
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
M2
M1
PL2
PL1
BPB
BPA
PB MUTE
AGC OFF
SPEED
DECK AB
REC MUTE
Pin 22
Pin 21
Pin 20
Pin 19
Pin 18
Pin 17
—
—
Pin 16
—
Pin 15
Low
Low
Low
Low
Low
Low
Low mute OFF
AGC function stops
Low, normal speed
DECK A selected
Low mute OFF
High (OPEN)
High (OPEN)
High (OPEN)
High (OPEN)
High (OPEN)
High (OPEN)
High mute ON
AGC function operates
High (open) 1.7
DECK B selected
High (open) mute ON
Output pin Input set at low
Input set at high
Output
DATA
(Pin 26)
Control signal
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
CLK
(Pin 25)
DATA
(Pin 26)
LATCH
(Pin 24)
XRESET
(Pin 27)
D11
• The DATA signal is taken in at the rising edge of the CLK signal.
• The DATA signal is taken into the internal shift register when the LATCH signal is low. (Outputs (Pins 15 to 22)
hold the previous value while the LATCH signal is low.)
• The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal.
(Internal shift register data is loaded while the LATCH signal is high.)
• The CLK signal of the 11th bit should fall after the LATCH signal rises.
• Reset is done when the XRESET pin is low. (asynchronous method)
Outputs (Pins 15 to 22) are all high (open) during reset.
Page 19
– 19 –
CXA1998BQ
• Make sure that VDD is 4.0V or more and XRESET is 1.5V or less, and 1µs or more when resetting by
applying CR time constant to XRESET (Pin 27) and turning power ON.
1µs or more
1.5V or less
4.0V or more
V
DD
(Pin 23)
XRESET
(Pin 27)
A
1µs or more
5.0V
4.0V or more
V
DD
(Pin 23)
XRESET
(Pin 27)
0V
• XRESET (Pin 27) input level detection is done by comparison with VDD/2.
The level should be VDD/2 > XRESET during the interval A.
• For resetting with CPU when power is turned ON
• Examples of AGC control during timer recording
(1) Resets when power is turned ON (AGC function operates).
(2) AGC is turned OFF after AGC inputs (Pins 5 and 32) rise.
(External capacitor charge of AGC TC is discharged.)
(3) AGC is turned ON and timer recording begins.
Page 20
– 20 –
CXA1998BQ
D11
H
L
D10
H
L
D9
H
L
D8
H
L
D12
H
L
D13
H
L
D14
H
L
D15
H
L
6
XQ2
Q2
XPR2
CLK2
D2
XR2
V
DD
VSS
XQ1
Q1
XPR1
CLK1
D1
XR1
74HC74 (1)
XQ2
Q2
XPR2
CLK2
D2
XR2
VDD
V
SS
XQ1
Q1
XPR1
CLK1
D1
XR1
74HC74 (2)
XQ2
Q2
XPR2
CLK2
D2
XR2
VDD
V
SS
XQ1
Q1
XPR1
CLK1
D1
XR1
74HC74 (3)
XQ2
Q2
XPR2
CLK2
D2
XR2
VDD
V
SS
XQ1
Q1
XPR1
CLK1
D1
XR1
74HC74 (4)
Y3
A3
B3
Y4
A4
B4
VDD
VSS
Y2
B2
A2
Y1
B1
A1
74HC00
Y3
A3
B3
Y4
A4
B4
VDD
VSS
Y2
B2
A2
Y1
B1
A1
74HC08 (2)
Y3
A3
B3
Y4
A4
B4
VDD
V
SS
Y2
B2
A2
Y1
B1
A1
74HC08 (1)
Y4
A4
Y5
A5
Y6
A6
VDD
V
SS
Y3
A3
Y2
A2
Y1
A1
74HC04
R5
10k
ON
OFF
START
3
ON
OFF
RESET
C5
0.1µ
4
C12
0.1µ
C9
0.1µ
C8
0.1µ
R3
10k
R6
10k
C4
0.1µ
18
C14
0.1µ
C13
0.1µ
C20
0.1µ
5
13
100
R16
12
7
14
Q1
CLOCK
RESET
Q9
Q8
Q10
Q11
VDD
V
SS
Q2
Q3
Q4
Q7
Q5
Q6
Q12
74HC4040
XA2
B2
XRES2
XQ2
Q1
C1
R/C1
V
DD
V
SS
R/C2
C2
Q2
XQ1
XRES1
B1
XA1
74HC123
B0
A0
B1
A1
A2
B2
A3
V
DD
VSS
A < BOUT
A = BOUT
A > BOUT
A > BIN
A = BIN
A < BIN
B3
74HC85
XLOAD
ENA 1
RESET
Q9
Q8
Q10
Q11
VDD
VSS
ENA P
DD
DC
DB
DA
CLOCK
XRESET
74HC161
QH
SERIALINA
B
C
D
CLK2
VDD
VSS
XQH
H
G
F
E
CLK1
S/XL
74HC165 (1)
C19
0.1µ
C18
0.1µ
1
2
4
8
H
L
H
L
HLH
L
D4
H
L
D5
H
L
D6
H
L
D7
H
L
QH
SERIALINA
B
C
D
CLK2
VDD
VSS
XQH
H
G
F
E
CLK1
S/XL
74HC165 (2)
C17
0.1µ
C11
0.1µ
C10
0.1µ
D3
H
L
D2
H
L
D1
H
L
8
17
68k
R17
11
C16
4.7µ
C15
1000P
R13
2.2k
1
R7
220
R8
220
R15
220
R14
220
R11
10k
R12
10k
9
16
R1
1M
R2
220
C6
15P
C7
15P
4.4MHz
R4
220
R9
220
2
LATCH
CLK
DATA
XRESET
DGND
5V
SW GND
GND
100µ/25V
C21
15
10
19
100
R18
DGND
EXCLK
C3
0.1µ
C2
0.1µ
C
0.1µ
EXCLK
250kHz
500kHz
100
R19
100
R10
8
9
10
11
12
13
14
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
1
1516
8
9
10
11
12
13
14
2
3
4
5
6
7
1
1516
8
9
10
11
12
13
14
2
3
4
5
6
7
1
1516
8
9
10
11
12
13
14
2
3
4
5
6
7
1
15
16
8
9
10
11
12
13
14
2
3
4
5
6
7
1
15
16
8
9
10
11
12
13
14
2
3
4
5
6
7
1
15
16
Circuit Diagram for 11-bit Serial Data Transfer Evaluation Tool
Page 21
– 21 –
CXA1998BQ
Timing Chart for 11-bit Serial Data Transfer Evaluation Tool
Dummy D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
2µs
COUNT RESET
CLOCK STOP
(14) RESET/CLOCK STOP and COUNT RESET
(15) DATA HC165
(16) CLK
(17) = (8)
(18)
(19) LATCH
(13)
(12)
(11) HC123
(10) H when A = B
(9)
(8) CLK GATE CONT.
(7) S/L
(6) = (4)
(5)
(4)
(3) START PULSE
(2) CLK
(1) CLK
The numbers (1) to (19) correspond to those of test pins for the 11-bit serial data transfer evaluation tool circuit.
Page 22
– 22 –
CXA1998BQ
Detection status
AMS OUT (Pin 12)
Signal detection
Low
No signal detection
High
PB OUT1
PB OUT2
20k 20k
SA
LPF
DET
25kHz
100k
GND
V
CC VCC VCC
GND
AMS GND
AMS OUT
AMS TC
C1
R1
R2
C2
R3
HPF
AMS GAIN
Inside IC
9
11
12
10
fC
G
10 1kHz 25kHz 100kHz
GAIN
(dB)
f (Hz)
3. AMS
(1) AMS output logic
AMS OUT (Pin 12) is an open collector output pin. When a 3.9 kΩ resistor is connected to VCC = 8V:
Low: approximately 0.5V (IOL = 2mA (max.))
High: 8V
Fig. 1 shows the AMS block diagram.
Fig. 1. AMS Block Diagram
Fig. 2 shows the frequency response of the signal output from HPF.
Fig. 2. Frequency Response
Page 23
– 23 –
CXA1998BQ
(2) AMS level setting
The AMS level is set by adjusting HPF gain and cut-off frequency with the external resistor and capacitor at
Pin 9.
G and fc in Fig. 2 are obtained from the following formula.
G = 20log (1 + 100k/R1) [dB] (1)
fc = 1 / (2 · π · C1 · R1) [Hz]
Full-wave rectifier is applied for the signal at DET.
Signal detection time is set by the time constant of Pin 11 external resistor and capacitor.
DET signal detection level:
= –7.5dBm (typ.)
= playback equalizer reference output level + AMS level + HPF gain (2)
Playback equalizer reference output level of –21dBm is 0dB.
Ex.)
To set AMS level at –25dB, determine and set the constant for Pin 9 external resistor.
(Calculate assuming PBOUT1 = PBOUT2)
First, get the required HPF gain from formula (2).
–7.5dBm = –21dBm + (–25dB) + HPFgain,
so HPF gain = 38.5dB.
Next, get Pin 9 external resistance from formula (1).
38.5dB = 20log (1 + 100k / R1),
so R1 ≈ 1.2kΩ,
and external resistance is 1.2kΩ.
Page 24
– 24 –
CXA1998BQ
Example of Representative Characteristics
Quiescent current consumption vs.
Supply voltage
Vcc – Supply voltage [V]
Quiescent current consumption [mA]
6
15
117 8 9 10
25
16
17
18
19
20
21
22
23
24
Icc is the sum of the Vcc and VDD currents.
VDD = 5.0V
PB IN
PB FB1
PB FB2
PB OUT
Playback equalizer frequency response
Frequency [Hz]
65
60
55
50
45
40
35
30
25
GAIN [dB]
20 50 100 200 500 1k 2k 5k 10k 20k 50k
120µs – NS
120µs – HS
70µs – NS
70µs – HS
M
VCC = 8V
0.018µ
470
10µF
47µ
100
2.2µ
Page 25
– 25 –
CXA1998BQ
Recording equalizer frequency response
Frequency [Hz]
Output response [dB]
20
0
10050 200 1k500 2k 10k5k 20k 50k
2
4
6
8
10
12
14
16
18
20
22
24
26
Recording equalizer frequency response
Frequency [Hz]
Output response [dB]
20 10050 200 1k500 2k 10k5k 20k 50k
VCC = 8V
0dB = NORM – NS, 315Hz, –30dBm
–2
–4
0
2
4
6
8
10
12
14
16
18
20
22
24
26
–2
–4
VCC = 8V
0dB = NORM – NS, 315Hz, –30dBm
(TAPE) (SPEED)
NORM – HS
CrO
2 – HS
METAL– HS
(TAPE) (SPEED)
NORM – HS
CrO2 – HS
METAL– HS
Page 26
– 26 –
CXA1998BQ
AMS quiescent detection level frequency response
Frequency [Hz]
30
25
20
15
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
AMS input level (playback equalizer output level) [dB]
20 50 100 200 500 1k 2k 5k 10k 20k 50k
VCC = 8V
120µs – NS
AMS OUT 8V
0dB = –21dBm, 315Hz (playback equalizer reference output level)
A
B
A: Pin 9 R9.1k C0.015µ
B: Pin 9 R1k C0.1µ
AMS GAIN
AMS TC
AMS OUT
0.1µ
100k
100k
to 8V
A : 0.015µ 9.1k
B : 0.1µ 1k
9
11
12
AGC output characteristics
AGC TC
47µ
300k
VCC = 8V
1kHz
AGC OFF
AGC ON
10
5
0
–5
–10
–15
–35 –30 –25 –20 –15 –10 –5
Input level [dBm]
Output level [dBm]
4
Page 27
– 27 –
CXA1998BQ
Recording equalizer total harmonic distortion
Output level [dBm]
T.H.D + Noise [%]
–15 100 5
0.1
0.2
0.5
1.0
2.0
VCC = 8V
NORM – NS
RL = 2.7kΩ
1kHz
0dB = –10dBm
–10 –5
Playback equalizer total harmonic distortion
Output level [dBm]
T.H.D + Noise [%]
–30 –5–15 –10
0.1
0.2
0.5
1.0
2.0
VCC = 8V
120µs – NS
RL = 2.7kΩ
1kHz
–25 –20
Page 28
– 28 –
CXA1998BQ
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
COPPER / 42 ALLOY
48PIN QFP (PLASTIC)
15.3 ± 0.4
12.0 – 0.1
+ 0.4
0.8 0.3 – 0.1
+ 0.15
± 0.12
13
24
2536
37
48
1 12
2.2 – 0.15
+ 0.35
0.9 ± 0.2
0.1 – 0.1
+ 0.2
13.5
0.15
0.15 – 0.05
+ 0.1
QFP-48P-L04
∗QFP048-P-1212-B
0.7g
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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