Page 1
Recording/Playback Equalizer Amplifier
Description
The CXA1898Q is an IC developed for analog
signal processing in tape recorders. Processing for
both the recording and playback systems is
achieved on one chip.
Features
• Recording equalizer Gp and Fp can be adjusted
externally.
• Recording mute function
• AGC (Automatic Gain Control)
• Comparator for AMS (Automatic Music Sensor)
• Recording/playback equalizer amplifier with
1.7 times speed switching
• 11-bit serial data interface
Absolute Maximum Ratings
• Supply voltage VCC 12 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 735 mW
Structure
Bipolar silicon monolithic IC
Applications
All analog signal processing in the cassette decks
of tape recorders and compact music centers
(Applicable to Sankyo Seiki mfg. Co., Ltd.
equivalent)
CXA1898Q
48 pin QFP (Plastic)
YK47R-KF202 R/P head or
Operating Conditions
Supply voltage VCC 6.5 to 10.0 V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94329B78
Page 2
Block Diagram and Pin Configuration (Top View)
CXA1898Q
IREF
PB OUT2
PB FB22
PB FB12
PB INB2
PB INA2
PB INA1
PB INB1
37
38
39
40
41
42
43
44
GND
210k
GND
GND
GND
GND
GND
GND
GND
GND
CC
RFC
36
V
35
210k
70k
70k
70k
70k
VG
34
IREF
GND
33
GND
AGC TC
32
AGC IN2
31
10k
40k
AGC
REC IN2
30
AGC OFF
D8
AGC OUT2
29
AGC GAIN 19.5dB
RECEQ
CTL
PBEQ
CTL
RECEQ
REC OUT2
28
DECK A/B
D10
SPEED
D9
B EQ
A EQ
D GND
27
GND
XRESET
26
SHIFT REGISTERS
DATA
25
CLK
24
LATCH
23
M2
22
D1
GND
D2
GND
D3
GND
D4
LATCHE S
GND
D5
GND
D6
M1
21
PL2
20
19
PL1
18
BPB
BPA
17
PB FB11
PB FB21
PB OUT1
AMS GAIN
45
210k
1
AMS
GND
AMS FIL
210k
MUTE
2
3
AMS OUT
4
AMS GND
5
FP CA L
GP CAL
GND
46
47
48
40k
AGC GAIN 19.5dB
10k
6
7
AGC IN1
REC IN1
8
AGC OUT1
SPEED
B EQ
RECEQ
D8
D10
D9
9
10
REC OUT1
A EQ
11
B EQ
D7
D9
D11
D11
12
GND
GND
GND
GND
GND
RMUTE1 I
16
15
14
13
PB MUTE
SPEED
R MUTE2
R MUTE1
– 2 –
Page 3
Pin Description
CXA1898Q
Pin
No.
6
31
7
30
Symbol
AGC IN1
AGC IN2
REC IN1
REC IN2
DC
voltage
4.0V I
4.0V I
I/O Equivalent circuit Description
I/O
resistance
50kΩ
50kΩ
31
6
VCC
GND
7
30
147 3k
VCC
GND
147
50k
47k
VGS
VGS
× 4
V
GND
CC
VGS
V
23k
1.8k
CC
AGC signal input.
Input resistance
changes between
47kΩ and 3kΩ
Recording equalizer
input.
8
29
9
28
AGC OUT1
AGC OUT2
REC OUT1
REC OUT2
4.0V O
4.0V
VCC
× 2
147
147Ω
O
147Ω
8
29
GND
VCC
9
28
GND
500
500
× 4
GNDGND
× 3
500
147
× 10
GND
18.8k
47.8k
5.3k
VGS
× 2
500
V
CC
AGC output pin.
AGC is applied at
–11dBm or more.
VGS
V
CC
40k
5p
Recording equalizer
output.
– 3 –
Page 4
CXA1898Q
Pin
No.
10
11
Symbol
A EQ
B EQ
DC
voltage
I/O Equivalent circuit Description
—I
2.5V
(when
I
open)
I/O
resistance
—
53kΩ
11
10
VCC
VCC
147
GND
147 50k
VCC
A deck equalizer
switch.
Low: 120µs EQ
High: 70µs EQ
GND
V
CC
B deck equalizer switch.
Low: Normal Tape,
5k
5k
120µs EQ
High: CrO2 Tape, 70µs
EQ
Medium: Metal Tape,
70µs EQ
12
13
14
15
16
RMUTE1 I
R MUTE1
R MUTE2
SPEED
PB MUTE
—I
5.0V
(when
reset)
(when
Pin 25
O
(DATA)
is set to
high)
—
—
VDD
GND
12
13
14
15
16
VCC
GND
GND
147
× 4
GND
GND
× 2
GND
5k
20k
20k
× 4
50µA
20k
× 2
5k
VCC
2.7V
Recording mute
ON/OFF switch.
Low: Mute OFF
High: Mute ON
∗
Fader function is
realized by the
external time
constant circuit.
Connects Pin 13
(RMUTE1).
Output for recording
mute ON/OFF switch
control signal.
Outputs D11 from Pin
25 (DATA).
VCC
Output for recording/
playback equalizer
speed switch control
signal. Outputs D9 from
Pin 25 (DATA).
Low: Normal Speed
High: High Speed
(1.7 times)
Output pin for playback
mute ON/OFF switch
control signal. Outputs
D7 from Pin 25 (DATA).
Connects a resistor to
VDD for Pins 13 to 16.
– 4 –
Page 5
CXA1898Q
Pin
No.
17
18
19
20
21
22
23
26
Symbol
BPA
BPB
PL1
PL2
M1
M2
LATCH
XRESET
DC
voltage
I/O Equivalent circuit Description
5.0V
(when
reset)
(when
Pin 25
O
(DATA)
is set to
high)
—I
I/O
resistance
—
—
VDD
23
26
17
18
19
20
21
22
GND
× 4
GND
GND
× 4
GND
20k
2k
5p
10.5k
25µA
× 4
10k
100µA
24k
Outputs D6 from
VCC
Pin 25 (DATA).
Outputs D5 from
Pin 25 (DATA).
Outputs D4 from
Pin 25 (DATA).
Outputs D3 from
Pin 25 (DATA).
Outputs D2 from
Pin 25 (DATA).
Outputs D1 from
Pin 25 (DATA).
Serial data interface
VCC
latch input.
Serial data interface
reset input.
Low: Reset.
At this time
serial data
outputs
(Pins 13 to 22)
are all open
(high).
24
25
32
CLK
DATA
AGC TC
—I
0.0V
—
—
—
24
25
GND
32
× 4
GND
VCC
GND
× 2
200
147
4k
10.5k
× 2
25µA
500
500
× 2
100k
GND
5k
VCC
100µA
24k
× 4
200
VCC
Serial data interface
clock input.
Serial data interface
serial data input.
Connects a resistor and
capacitor for
determining AGC
attack/recovery time
constants.
– 5 –
Page 6
CXA1898Q
Pin
No.
34
35
36
Symbol
VG
VCC
RFC
DC
voltage
4.0V —
8.0V
8.0V —
I/O Equivalent circuit Description
—
I/O
resistance
60kΩ
—
34
35
VCC
GND
VCC
× 2
147
45k
30k
30k
× 3
GND
× 2
500
500
× 4
CC
V
Signal reference
voltage. Connects a
To
each
capacitor for ripple
VSG
rejection.
CC
V
Power supply.
CC
V
Connects a resistor
and capacitor for
—
36
147
× 3
× 250
obtaining stable
voltage with power
supply ripple rejected.
38
47
PB OUT2
PB OUT1
2.8V
To each RFS
GND
V
VCC
× 3
500
38
O
147Ω
47
147
× 6
GND
GND
500
5p
5k
× 2
CC
Playback equalizer
× 2
output.
– 6 –
Page 7
CXA1898Q
Pin
No.
39
46
40
45
41
42
43
44
Symbol
PB FB22
PB FB21
PB FB12
PB FB11
PB INB2
PB INA2
PB INA1
PB INB1
DC
voltage
2.8V —
1.4V —
0.0V I
I/O Equivalent circuit Description
I/O
resistance
—
39
46
VCC
147
× 3
7k
× 3
× 4
× 4
RFS
2k2k
Connects a capacitor
for determining
playback equalizer
time constants, such
as 120µs and 70µs.
105kΩ
70kΩ
GND
VCC
VCC
10k10k
41
42
43
44
GND
147
70k
× 6
× 6
GND
GND GND
VCC
RFS
VCC
1k
210k
1k
5p
× 2
147
210k
GND
Playback equalizer
negative feedback.
40
45
Playback equalizer
input.
VCC
10µ
VCC
Connects a resistor
for determining AMS
48
AMS GAIN
3.5V
—
—
48
100k
147
signal detection level
and a capacitor for
determining HPF
cut-off frequency.
GND
GND
Note)
The resistance of open collector outputs (Pins 2 and 13 to 22) can be also connected to VCC.
– 7 –
Page 8
Electrical Characteristics
(Ta = 25°C, VCC = 8.0V, VDD = 5.0V, refer to Electrical Characteristics Measurement Circuit)
CXA1898Q
Item
Operating voltage
Current consumption
AGC ON output level
AGC ON channel
balance
AGC
AGC ON distortion
AGC OFF output
level
No signal detection
threshold level
AMS
120µs–NS
frequency response
120µs–NS
frequency response
70µs–NS
frequency response
120µs–HS
frequency response
Measurement conditions Min. Typ. Max. Unit
VCC
NORM–NS, VCC = 8V, No signal
Pin 32 external R300kΩ/ /C47µF
f = 1kHz, Vin = –25dBm
Pin 32 external R300kΩ/ /C47µF
f = 1kHz, Vin = –15dBm
Pin 32 external R300kΩ/ /C47µF
f = 1kHz, Vin = 0dBm
Pin 32 external R300kΩ/ /C 47µF
f = 1kHz, Vin = –25dBm
Pin 48 external R9.1kΩ, C0.015µF
Pin 1 external R100kΩ/ /C0.1µF
f = 5kHz, 0dB = –21dBm
(at PBEQ reference output level)
f = 315Hz, Vin = –70dBm
Reference for frequency response
f = 2.7kHz, Vin = –58.5dBm
at 120µs–NS, 315Hz
f = 4.5kHz, Vin = –53.8dBm
at 120µs–NS, 315Hz
f = 5.3kHz, Vin = –52.5dBm
at 120µs–NS, 315Hz
6.5
13.5
–13.0
–2.0
—
–7.5
–11.5
–23.0
–0.1
–0.1
1.8
8.0
18.0
–11.0
0.0
0.3
–5.5
–8.2
–21.0
1.3
1.7
3.0
10.0
22.5
–9.0
2.0
1.5
–3.5
—
–19.0
2.9
2.9
4.8
V
mA
dBm
dB
%
dBm
dB
dBm
dB
70µs–HS
frequency response
Signal handling
Total harmonic
Playback equalizer amplifier block
distortion
S/N ratio
Output offset voltage
f = 9.1kHz, Vin = –47.8dBm
at 120µs–NS, 315Hz
120µs–NS, RL = 2.7kΩ
f = 1kHz, THD + N = 1%
120µs–NS, RL = 2.7kΩ
f = 1kHz, Vin = –56.4dBm
120µs–NS, Rg = 2.2kΩ
"A" weighting filter
120µs–NS, Rg = 70kΩ
2.1
–10.0
—
55.0
2.4
3.6
–6.0
0.3
62.0
2.7
5.1
—
0.7
—
3.2
dBm
%
dB
V
– 8 –
Page 9
CXA1898Q
Item
Reference input level
Reference output level
Channel balance
NORM–NS
frequency response
NORM–NS
frequency response
NORM–NS
frequency response
CrO2–NS
frequency response
CrO2–NS
frequency response
CrO2–NS
frequency response
METAL–NS
frequency response
Measurement conditions Min. Typ. Max. Unit
NORM–NS, 315Hz, input level at which
reference output can be obtained
NORM–NS, 315Hz
NORM-NS, 315Hz, Output difference
1ch–2ch for –27.9dBm input
f = 3kHz
at NORM–NS, 315Hz, reference output –20dB
f = 8kHz
at NORM–NS, 315Hz, reference output –20dB
f = 12kHz
at NORM–NS, 315Hz, reference output –20dB
f = 3kHz
at NORM–NS, 315Hz, reference output –20dB
f = 8kHz
at NORM–NS, 315Hz, reference output –20dB
f = 12kHz
at NORM–NS, 315Hz, reference output –20dB
f = 3kHz
at NORM–NS, 315Hz, reference output –20dB
–29.4
—
–1.5
–1.3
3.7
10.4
1.8
6.7
13.2
3.3
–27.9
–10.0
0.0
–0.2
5.7
13.4
3.0
8.4
15.8
4.5
–26.4
dBm
—
1.5
1.1
7.3
16.4
4.2
9.7
18.2
5.7
METAL–NS
frequency response
METAL–NS
frequency response
NORM–HS
frequency response
Recording equalizer amplifier block
NORM–HS
frequency response
NORM–HS
frequency response
CrO2–HS
frequency response
CrO2–HS
frequency response
CrO2–HS
frequency response
METAL–HS
frequency response
METAL–HS
frequency response
f = 8kHz
at NORM–NS, 315Hz, reference output –20dB
f = 12kHz
at NORM–NS, 315Hz, reference output –20dB
f = 5kHz
at NORM–NS, 315Hz, reference output -20dB
f = 15kHz
at NORM–NS, 315Hz, reference output –20dB
f = 20kHz
at NORM–NS, 315Hz, reference output –20dB
f = 5kHz
at NORM–NS, 315Hz, reference output –20dB
f = 15kHz
at NORM–NS, 315Hz, reference output –20dB
f = 20kHz
at NORM–NS, 315Hz, reference output –20dB
f = 5kHz
at NORM–NS, 315Hz, reference output –20dB
f = 15kHz
at NORM–NS, 315Hz, reference output –20dB
5.9
11.3
–0.7
8.3
13.5
3.6
12.0
17.0
4.9
10.5
7.4
13.7
0.2
10.5
16.7
4.9
14.2
20.0
6.1
12.4
8.9
15.8
1.7
12.3
19.5
6.0
16.0
22.5
7.3
14.0
dB
METAL–HS
frequency response
f = 20kHz
at NORM–NS, 315Hz, reference output –20dB
– 9 –
14.7
17.4
19.7
Page 10
CXA1898Q
Item
Signal handling
Total harmonic distortion
S/N ratio
Output offset voltage
Mute characteristics 1
Mute characteristics 2
Recording equalizer amplifier block
Control voltage low level 1
Control voltage high level 1
Control voltage low level 2
Control voltage medium level 1
Control voltage high level 2
Control voltage low level 3
Measurement conditions Min. Typ. Max. Unit
NORM–NS, RL2.7kΩ
f = 1kHz, THD = 1%
NORM–NS, RL2.7kΩ
f = 1kHz, 0dB
NORM–NS, Rg = 5.1kΩ
"A" weighting filter
NORM–NS
NORM–NS, f = 1kHz
8dB, Pin 12 = 3.5V
NORM–NS, f = 1kHz
8dB, Pin 12 = 2.0V
A-EQ (Pin 10)
A-EQ (Pin 10)
B-EQ (Pin 11)
B-EQ (Pin 11)
B-EQ (Pin 11)
RMUTE1-I (Pin 12)
8.0
—
57.0
3.6
—
–8.3
0.0
2.5
0.0
2.2
4.2
0.0
8.8
0.2
60.6
4.0
–100
–7.0
—
—
—
—
—
—
–4.3
—
0.5
—
4.4
–80
0.5
VCC
0.5
2.8
VCC
0.5
dB
%
dB
V
dB
V
Control voltage high level 3
RMUTE1-I (Pin 12)
Note) NORM–NS : NORMAL TAPE–NORMAL SPEED
NORM–HS : NORMAL TAPE–HIGH SPEED
CrO2–NS : CrO2 TAPE–NORMAL SPEED
CrO2–HS : CrO2 TAPE–HIGH SPEED
METAL–NS : METAL TAPE–NORMAL SPEED
METAL–HS : METAL TAPE–HIGH SPEED
120µs–NS : EQ = 120µs–NORMAL SPEED
120µs–HS : EQ = 120µs–HIGH SPEED
70µs–NS : EQ = 70µs–NORMAL SPEED
70µs–HS : EQ = 70µs–HIGH SPEED
3.5
—
VCC
– 10 –
Page 11
CXA1898Q
Item
Low level input
voltage
High level input
voltage
Low level output
voltage
High level output offleak current
Maximum clock frequency
Minimum clock pulse
width
Minimum reset pulse
width
Minimum data setup
time
Minimum data hold
time
11-bit serial data interface block
Minimum data pulse
width
Measurement conditions Min. Typ. Max. Unit
VIL (LATCH/CLK/DATA/XRESET)
(Pins 23, 24, 25, 26)
VIH (LATCH/CLK/DATA/XRESET)
(Pins 23, 24, 25, 26)
VOL, IOL = 2mA (max) (Pins 13, 14, 15, 16,
17, 18, 19, 20, 21, 22)
IOZ Leak current which flows to the output
pin when Ioz output is open; applied
voltage is 10V.
(1) fCK
(2) tWC
(3) tWR
(4) tSDK (DATA → CLK)
(5) tHCD (CLK → DATA)
(6) tWD
0.0
3.5
0.0
—
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
VDD
0.5
1.0
—
1.0
1.0
1.0
1.0
2.0
V
µA
kHz
µs
Minimum latch setup
time
Minimum latch hold
time
Minimum clock hold
time
(7) tSLD (LATCH → DATA)
(8) tHCL (CLK → LATCH)
(9) tHLC (LATCH → CLK)
Note) • VDD is CPU supply voltage 5.0V.
• The maximum value for VDD is Pin 35 (VCC) voltage.
• For high level output off leak current, VCC is 10.0V.
—
—
—
—
—
—
1.0
1.0
1.0
– 11 –
Page 12
Timing Chart for 11-bit Serial Data Interface
3.5V
CLK
1.5V
3.5V
CXA1898Q
tWCtWC
tWDtHCDtSDK
DATA
LATCH
CLK
DATA
1.5V
SLD
t
1.5V
D10 D11
D1 D2
3.5V
HLC
t
HCL
t
LATCH
XRESET
3.5V
1.5V
1.5V
tWR
– 12 –
Page 13
CXA1898Q
CLK
LATCH
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
2k
2k
2k
2k
2k
2k
2k
2k
2k
2k
RMUTE1 I
B EQ
A EQ
REC OUT1
AGC OUT 1
REC IN1
AGC IN1
GP CAL
FP CAL
AMS GND
AMS OUT
AMS FIL
0.1µ
S28B
ON
12
11
10
9
8
7
6
5
4
3
2
1
REC MUTE
S27
10k
0.1µ
10k
0.1µ
10k
2.2µ
4.7µ
0.47µ
0.47µ
B EQ
A EQ
OFF
S28A
METAL
S26
CrO2
S25
NORM
S24
70µs
120µs
S23
S12D
2.7k
10k
5.1k
S20
5.1k
27k
27k
100k
0.1µ
100k
390k
S7F
47k
0.1µ
S18A
22
24
23
CLK
DATA
XRESET
10k
S21B
100
S21A
S17B
100
390k
47k
S17A
10k
S15
10k
S13B
100
S13A
8.0V
2.7k
S12C
10k
S7E
5.1k
S19
0.1µ
5.1k
47µ
300k
10µ
10µ
0.1µ
1k
10µ
0.1µ
DATA
25
26
27
28
2.2µ
4.7µ
29
0.47µ
30
0.47µ
31
32
33
34
35
36
LATCH
XRESET
D GND
REC OUT2
AGC OUT 2
REC IN2
AGC IN2
AGC TC
GND
VG
VCC
RFC
IREF
PB OUT2
38
37
12k
S12A
21
M2
PB FB22
39
2.2µ
2.7k
20
M1
PL2
PB FB12
PB INB2
40
41
0.018µ
100
2.2k
47µ
0.1µ
S7A
18
19
PL1
BPB
CXA1898Q
PB INA2
PB INA1
42
43
0.47µ
0.47µ
2.2k
2.2k
S9
S8
S10
0.1µ
S7B
0.1µ
S7C
16
17
BPA
PB INB1
44
0.47µ
2.2k
S11
S7D
15
SPEED
PB MUTE
PB FB11
PB FB21
46
45
0.018µ
0.47µ
100
47µ
0.1µ
13
14
R MUTE2
R MUTE1
PB OUT1
AMS GAIN
48
47
2.2µ
9.1k
2.7k
0.015µ
S12B
DC OUTPUT
GND
4.2V 2.0V 2.5V 3.5V 5.0V0.5V
S39
S22B
10k
100
S22A
S18B
100
10k
S16
10k
S14B
100
S14A
S1BS1A
S3BS3A
S6BS6A
S4BS4A
S2BS2A
ATT
ATT
ATT
ATT
AC INPU T
–40dB
–29dB
–17dB
–9dB
Electrical Characteristics Measurement Circuit
TL072
ATT
377k
600
GND
–6dB
– 13 –
377k
377k
377k
100k
GND
BUF
30dB AMP
"A" W eighting Filter
Audio (22.2Hz-22.2kHz) Filter
1kHz Band Pass Fi lter ( 20dB)
S501
S502
S503
S504
S505
AC OUTPUT
Page 14
Application Circuit
CXA1898Q
GND
R/P-HEAD
GND
100k
GNDGND VDD
2.2µ
DATA
XRESET
26
25
CLK
24
LATCH
23
M2
22
D1
M1
GND
21
D2
PL2
GND
20
D3
PL1
GND
19
D4
LA T CHES
SHIFT REGISTERS
D8
D10
D9
11
B EQ
0.1µ
D11
D11
12
BPB
GND
18
D5
BPA
GND
17
D6
PB MUTE
GND
16
D7
SPEED
GND
15
D9
R MUTE2
GND
14
R MUTE1
GND
13
GND
RMUTE1 I
10k
GND
47k
VDD
or
VCC
47k
VDD
or
VCC
47k
VDD
or
VCC
47k
VDD
or
VCC
47k
VDD
or
VCC
47k
VDD
or
VCC
47k
VDD
47k
47k
47k
47k
47k
or
VCC
VDD
or
VCC
VDD
or
VCC
VDD
or
VCC
DD
V
or
VCC
CC
V
GND
10µ
1k
CC
V
RFC
35
36
12k
1k
IREF
PB OUT2
PB FB22
0.018µ
PB FB12
PB INB2
PB INA2
PB INA1
PB INB1
PB FB11
0.018µ
PB FB21
PB OUT1
AMS GAIN
44
45
46
47
48
37
38
39
40
41
42
43
100k
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
210k
210k
210k
70k
70k
70k
70k
210k
AMS
GND
1
2
AMS FIL
AMS OUT
100k
0.1µ
V
DD
or
VCC
GND
GND
10k 2.2µ
820p
10k
47µ 100
12mH
150p
180p
DECK -B
180p
150p
820p
GND
REC
REC
GND
GND
PB
BIas
OSC
DECK -A
PB-HEAD
PB
GND
47µ 100
12mH
10k
10k 2.2µ
GND
GND
0.1µ
47µ
100µ
VG
34
IREF
3
AMS GND
GND GND
GND
33
GND
4
FP CAL
27k 27k
GND
GNDGNDGND
2.2meg
47µ
AGC TC
32
MUTE
5
GP CAL
GND
0.1µ
2.7k
0.47µ
10k
4.7µ
AGC OUT2
REC IN2
AGC IN2
31
30
29
10k
AGC GAIN 19.5dB
40k
AGC OFF
D8
AGC
40k
AGC GAIN 19.5dB
10k
6
AGC IN1
0.47µ
8
7
REC IN1
4.7µ
AGC OUT1
10k
2.7k
0.1µ
GND GND
RECE Q
PBEQ
RECE Q
SPEED
B EQ
RECE Q
REC OUT 2
28
DECK A/B
D10
CTL
SPEED
D9
B EQ
A EQ
CTL
REC OUT 1
2.2µ
9
2.2µ
D GND
27
GND
10
A EQ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 14 –
Page 15
1. System control mode
Playback and recording equalizer
(1) Playback equalizer (120µs/70µs)
A-EQ (Pin 10) B-EQ (Pin 11)
L H L M/H
CXA1898Q
DECK-AB
L
120µs
(A DECK)
70µs
(A DECK)
According to A EQ control
(serial data
D10 (Pin 25))
According to B EQ control
H
120µs
(B DECK)
70µs
(B DECK)
(2) Recording equalizer (Normal, CrO2, Metal)
B-EQ (Pin 11)
REC MODE
L
Normal (Type I)
M
CrO2 (Type II)
H
Metal (Type IV)
(3) Recording mute (Pin 12)
Rec Mute
Control voltage
Mute OFF
GND ≤ VCL ≤ 0.5V
–7dB attenuation
2.0V
Mute ON
3.5V ≤ VCH ≤ VCC
Muting is achieved by varying the recording equalizer amplifier gain just like an electronic volume, according to
the DC voltage applied to the REC MUTE pin.
(4) FP CAL (Pin 4)
The standard resistor setting is 27kΩ, but when resistance value is larger, fo (Hz) is low, and when resistance
value is smaller, fo (Hz) is high.
(5) Gp Cal (Pin 5)
The standard resistor setting is 27kΩ, but when resistance value is larger, gain is larger, and when resistance
value is smaller, gain is smaller.
– 15 –
Page 16
2. 11-bit serial data interface
CL k (Pin 24)
CXA1898Q
DAT A (Pin 2 5)
L ATCH (Pin 23)
XRESET (Pin 26)
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
D11
• The DATA signal is taken in at the rising edge of the CLK signal.
• The DATA signal is taken in to the internal shift register when the LATCH signal is low.
(Outputs (Pins 13 to 22) hold the previous value while the LATCH signal is low.)
• The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal.
(Internal shift register data is loaded while the LATCH signal is high.)
• The CLK signal of 11th bit should fall after the LATCH signal rises.
• Reset is done when the XRESET pin is low. (asynchronous method)
Outputs (Pins 13 to 22) are all high (open) during reset.
DATA
(Pin 25)
D1
Control signal
M2
Output pin Input set at low
Pin 22
Output
L
Input set at high
H (OPEN)
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
M1
PL2
PL1
BPB
BPA
PB-MUTE
AGC-OFF
SPEED
DECK-AB
REC-MUTE
Pin 21
Pin 20
Pin 19
Pin 18
Pin 17
Pin 16
—
Pin 15
—
Pin 14/Pin 13
L
L
L
L
L
L
AGC function stops
Low, normal speed
A DECK selected
Low mute OFF
H (OPEN)
H (OPEN)
H (OPEN)
H (OPEN)
H (OPEN)
H (OPEN)
AGC function operates
High (open) 1.7
B DECK selected
High (open) mute ON
– 16 –
Page 17
CXA1898Q
• Make sure that RFC is 5.5V or more and XRESET is 1.5V or less, and 1µs or more when resetting by
applying CR time constant to XRESET (Pin 26) and turning power ON.
5.5V or more
RFC (Pin 36)
XRESET (Pin 26)
1.5V or less
1µs or more
• When resetting with CPU or other when power is turned ON
5.5V or more
RFC (Pin 36)
XRESET (Pin 26)
0V
1µs or more
• Examples of AGC control during timer recording
(1) Resets when power is turned ON (AGC function operates).
(2) AGC is turned OFF after AGC inputs (Pins 6 and 31) rise.
(External capacitor charge of AGC TC is discharged.)
(3) AGC is turned ON and timer recording begins.
5.0V
– 17 –
Page 18
Circuit Diagram for 11-bit Serial Data Transfer Evaluation Tool
RESET
OFF
ON
R3
10kR610k
13
12
14
D2
XR2
V
DD
0.1µ
C5
0.1µ
C4
74HC74 (1)
CLK1
XR1
D1
1
2
3
13
12
14
D2
XR2
VDD
74HC74 (3)
CLK1
XR1
D1
1
2
3
9
10
11
CLK2
XPR1
4
OFF
11
CLK2
XPR1
4
8
XQ2
Q2
XPR2
XQ1
VSS
Q1
6
5
7
R5
10k
ON
START
3
15
9
10
8
XQ2
Q2
XPR2
XQ1
VSS
Q1
6
5
7
13
12
14
D2
XR2
V
0.1µ
DD
C14
74HC74 (2)
CLK1
XR1
D1
1
2
3
13
12
14
D2
XR2
V
DD
0.1µ
C13
74HC74 (4)
CLK1
XR1
D1
1
2
3
9
10
11
Q2
XPR2
CLK2
XPR1
XQ1
Q1
6
5
4
6
4
9
10
11
Q2
XPR2
CLK2
XPR1
XQ1
Q1
6
5
4
5
8
XQ2
VSS
7
13
R16
100
8
XQ2
VSS
7
CXA1898Q
SW GND
GND
100µ/25V
13
12
14
A4
B4
VDD
0.1µ
C20
Y1
B1
A1
1
2
3
11
Y4
74HC00
A2
4
9
10
8
Y3
A3
B3
VSS
Y2
B2
6
5
7
XRESET
DGND
5V
C21
LATCH
DATA
CLK
DGND
EXCLK
0.1µ
C3
4.4MHz
R1
1M
C6
15PC715P
0.1µ
C2
0.1µ
C
14
VDD
A1
1
16
VDD
Q12
1
VDD
XRESET
1
17
8
16
R10
100
13
12
Y6
A6
A2
Y1
2
3
220
15
14
Q10
Q11
Q5
Q6
2
3
1516
14
Q10
Q11
CLOCK
DA
2
3
74HC04
R2
EXCLK
11
A5
Y2
4
220
13
Q8
74HC4040
Q7
4
220
R7
13
Q8
74HC161
DB
4
9
10
8
Y4
A4
Y5
V
Y3
A3
SS
6
5
7
220
2
R9
R4
11
11
RESET
Q3
6
RESET
DD
6
9
10
Q1
CLOCK
VSS
Q2
8
7
220
R8
500kHz
1
9
10
XLOAD
ENA 1
ENA P
V
SS
8
7
12
Q9
Q4
5
250kHz
12
Q9
DC
5
R12
R11
10k
10k
14
V
0.1µ
DD
C12
0.1µ
0.1µ
C8
C9
A1
1
R13
2.2k
16
VDD
0.1µ
C11
XA1
1
VDD
0.1µ
C10
S/XL
1
12
1
9
13
12
A4
B4
74HC08 (1)
Y1
B1
2
3
R14
220
C15
1000P
15
14
C1
R/C1
XRES1
B1
2
3
H
1516
14
D
CLK2
CLK1
E
2
3
11
Y4
A2
4
13
Q1
74HC123
XQ1
4
L
L
H
D12
13
C
74HC165 (1)
F
4
D11
9
10
8
Y3
A3
B3
VSS
Y2
B2
6
5
7
R15
220
11
12
XQ2
Q2
5
H
D13
12
B
G
5
D10
9
10
11
XA2
B2
XRES2
R/C2
VSS
C2
6
8
7
R17
C16
4.7µ
68k
L
L
H
D14
D15
9
10
11
QH
SERIALINA
XQH
VSS
H
6
8
7
D9
D8
13
12
14
VDD
0.1µ
C19
A1
1
16
VDD
0.1µ
C18
B3
1
V
0.1µ
DD
C17
S/XL
1
11
Y4
A4
B4
74HC08 (2)
A2
Y1
B1
4
2
3
100
R18
19
H
H
L
L
8
4
13
15
14
A2
B2
A3
74HC85
A>BIN
A=BIN
A<BIN
4
2
3
L
H
H
D4
13
1516
14
C
D
CLK2
74HC165 (2)
CLK1
F
E
4
2
3
D3
L
D5
D2
10
B3
B2
5
12
A1
A>BOUT
5
L
H
D6
12
B
G
5
D1
14
9
Y3
A3
VSS
Y2
6
HLH
2
10
11
B1
A=BOUT
6
7
16
L
H
D7
10
11
H
6
8
7
L
1
9
B0
A0
A<BOUT
VSS
8
R19
100
9
QH
SERIALINA
XQH
VSS
8
7
15
H
H
H
H
L
L
L
L
H
H
H
L
L
L
– 18 –
Page 19
CXA1898Q
CLOCK STOP
COUNT RESET
2µs
(11) HC123
(10) A = B, H
(9)
(8) CLK GATE CONT.
(7) S/L
(6) = (4)
(5)
(4)
(3) START PULSE
(2) CLK
(1) CLK
Timing Chart for 11-bit Serial Data Transfer Evaluation Tool
– 19 –
(12)
Dummy D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
(14) RESET/CLOCK STOP and COUNT RESET
(13)
(16) CLOCK
(15) DATA HC165
(17) = (8)
(18)
(19) LATCH
Page 20
3. AMS
(1) AMS output logic
CXA1898Q
Detection status
AMS OUT (Pin 2)
Signal detection
L
No signal detection
H
AMS OUT (Pin 2) is an open collector output pin. When a 2.2kΩ resistor is connected to VDD:
Low : approximately 0.5V (IOL = 2mA (max.))
High : VDD
Fig. 1 shows the AMS block diagram.
PB OUT1
PB OUT2
20k
SA
20k
AMS GAIN
LPF
25kHz
Inside IC
48
R1
C1
GND
100k
HPF
DET
AMS OUT
1
AMS FIL
R2
C2
V
DD VDD VDD
R3
AMS GND
3
2
GND
Fig. 1 AMS Block Diagram
Fig. 2 shows the frequency response of the signal output from HPF.
f
G
GAIN
(dB)
10 1kHz 25kHz 100kHz
C
f (Hz)
Fig. 2 Frequency Response
– 20 –
Page 21
CXA1898Q
(2) AMS level setting
The AMS level is set by adjusting HPF gain and cut-off frequency with the external resistor and capacitor at
Pin 48.
G and fc in Fig. 2 are obtained from the following formula.
G = 20log (1 + 100k/R) [dB] – (1)
fc = 1/ (2 • π • C • R) [Hz]
Full-wave rectifier is applied for the signal at DET.
Signal detection time is set by the time constant of Pin 1 external resistor and capacitor.
DET signal detection level:
= –7.5dBm (typ.)
= playback equalizer reference output level + AMS level + HPF gain – (2)
Playback equalizer reference output level of –21dBm is 0dB.
Ex.)
To set AMS level at –25dB, determine and set the constant for Pin 48 external resistor.
(Calculate assuming PBOUT1 = PBOUT2)
First, get the required HPF gain from formula (2).
–7.5dBm = –21dBm + (–25dB) + HPF gain,
so HPF gain = 38.5dB.
Next, get Pin 48 external resistance from formula (1).
38.5dB = 20log (1 + 100k/R),
so R ≈ 1.2kΩ,
and external resistance is 1.2kΩ.
– 21 –
Page 22
Example of Representative Characteristics
Quiescent current consumption vs. Supply voltage
25
24
23
22
21
20
19
18
17
-Quiescent current consumption (mA)
CC
16
I
15
6 7 8 9 10 11
CXA1898Q
VCC-Supply voltage (V)
Playback equalizer frequency response
65
60
55
50
45
GAIN (dB)
40
35
30
25
20 50 100 200 500 1k 2k 5k 10k 20k 50k
Frequency (Hz)
120µs – NS
120µs – HS
70µs – NS
70µs – HS
VCC = 8V
PB IN
0.47µ
100
2.2k
PB FB1
0.018µ
47µ
PB FB2
PB OUT
2.2µ
M
– 22 –
Page 23
Recording equalizer frequency response
30
28
VCC = 8V
26
0dB = NORM – NS, 315Hz, –30dBm
24
22
20
18
16
14
12
10
8
Output response (dB)
6
4
2
0
–2
(Tape) (Speed)
NORM–
CrO2–
METAL–
20 50 100 200 500 1k 2k 5k 10k 20k 50k
NS
NS
NS
Frequency (Hz)
CXA1898Q
Recording equalizer frequency response
30
28
VCC = 8V
26
0dB = NORM – NS, 315Hz, –30dBm
24
22
20
18
16
14
12
10
8
Output response (dB)
6
4
2
0
–2
(Tape) (Speed)
NORM–
CrO2–
METAL–
20 50 100 200 500 1k
HS
HS
HS
2k 5k 10k 20k 50k
Frequency (Hz)
– 23 –
Page 24
10
0
–10
–20
–30
–40
–50
Output level (dB)
–60
CXA1898Q
Output level vs. Mute voltage
VCC = 8V
(Tape) (Speed)
NORM– NS
0dB = reference output level +8dB
f = 1kHz
–70
–80
–90
–100
0.0 1.0 2.0 3.0 4.0 5.0 6.0
RMUTE1 (Pin 1) voltage
VCC = 8V
120µs – NS
AMS OUT 5V
0dB = –21dBm, 315Hz (playback equalizer reference output level)
AMS no signal detection level frequency response
30
25
20
15
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
20 50 100 200 500 1k 2k 5k 10k 20k 50k
AMS input level (playback equalizer output level) (dB)
A : Pin 48 for R9.1k, C0.015µ
B : Pin 48 for R1k, C0.1µ
Frequency (Hz)
A : 0.015µ 9.1k
B : 0.1µ 1k
AMS OUT
AMS FIL
AMS GAIN
A
B
48
1
0.1µ
2
100k
100k
to5V
– 24 –
Page 25
AGC Output response
CXA1898Q
10
5
0
300k
–5
Output level (dBm)
–10
–15
–35 –30 –25 –20 –15 –10 –5
32
VCC = 8V
1kHz
AGC TC
47µ
Input level (dBm)
Recording equalizer total harmonic distortion
AGC OFF
AGC ON
Playback equalizer total harmonic distortion
2.0
1.0
0.5
T.H.D. + Noise (%)
0.2
0.1
–15 –10 –5 0 5 10
VCC = 8V
Norm – NS mode
RL = 2.7kΩ
1kHz
0dB = –10dBm
Output level (dB)
2.0
1.0
0.5
T.H.D. + Noise (%)
0.2
0.1
–30 –25 –20 –15 –10 –5
VCC = 8V
120µs – NS mode
RL = 2.7kΩ
1kHz
Output level (dB)
– 25 –
Page 26
Package Outline Unit: mm
15.3 ± 0.4
CXA1898Q
48PIN QFP (PLASTIC)
+ 0.4
12.0 – 0.1
2536
37
48
112
0.8 0.3 – 0.1
+ 0.15
24
13
± 0.12
M
+ 0.35
2.2 – 0.15
+ 0.1
0.15 – 0.05
0.15
+ 0.2
0.1 – 0.1
13.5
0.9 ± 0.2
PACKAGE STRUCTURE
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
COPPER / 42 ALLOY
0.7g
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-48P-L04
∗QFP048-P-1212-B
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 26 –
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