SANYO LC7930NW, LC7930N Datasheet

Ordering number: EN2778C

CMOS LSI

LC7930N, 7930NW

LCD Drivers

Overview

The LC7930N, 7930NW are CMOS LSIs which incorporate 20-bit shift register, latch, and two sets of 20 LCD drivers. They also have two switching pins: one of them (channel 2) can be used as a scan-line driver (back plate) and the other (channel 1) as a segment driver. They are optimal for LCD interface with microcontroller (4 or 8 bits) or dot matrix controller circuit incorporating character generator.

Features

. Two channels of 20 output segment drivers

. The configuration of 20 output segment drivers + 20

. scanning terminal drivers available

A series data to connect with the microcontroller and three

. control signals

. Able to be connected in series for large display Built-in bidirectional shift register can be shifted in the

. direction that makes wiring easy

Operating supply voltage/ Operating temperature:

. VDD = 4.5 to 5.5 V / Topr = ±20 to +75°C Operating current drain : IDD = 1.0 mA max

. (Logic = 400 kHz, LCD = 1 kHz) Package : Pin 60 Flat LC7930N : QIP60

Pin 64 Flat LC7930NW : SQFP64

Package Dimensions

unit : mm

3055A-QFP60C

[LC7930N]

SANYO : QIP60C

unit : mm

3190-SQFP64

[LC7930NW]

SANYO : SQFP64

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

13097HA(II)/12593JN/6031JN/6218TA,TS No.2778-1/7

LC7930N, 7930NW

Specifications

Absolute Maximum Ratings at Ta = 25 ± 2°C

	Parameter	Symbol	Conditions	Ratings	Unit
	Maximum supply voltage	VDD max		±0.3 to +7.0	V
		VEE max		VDD±13.5 to VDD+0.3	V
	Maximum input voltage	VI max		±0.3 to VDD+0.3	V
			V1, V2, V3, V4, V5, V6	VEE to VDD+0.3	V
	Maximum output voltage	VO max		±0.3 to VDD+0.3	V
			Output transistor OFF, Y1 to Y40	VEE to VDD+0.3	V
	Allowable power dissipation	Pd max		100	mW
	Operating temperature	Topr		±20 to +75	°C
	Storage temperature	Tstg		±55 to +125	°C

Note : Don't soak the whole of IC into the tank filled with melted solder for soldering

Allowable Operating Conditions at Ta = ±20 to +75°C, V SS = 0 V, VEE = ±4 to ±6 V

Parameter	Symbol		Conditions	min	typ	max	Unit
Supply voltage	VDD	VDD		4.5		5.5	V
High-level input voltage	VIH	Note (1)		0.7VDD		VDD	V
Low-level input voltage	VIL	Note (1)		VSS		0.3VDD	V
Shift frequency	fCL	CLKSR				400	kHz
High-level clock width	tCWH	CLKSR, CLKLA		800			ns
Low-level clock width	tCWL	CLKSR		800			ns
Data setup time	tSU	LDATA1, LDATA2,		300			ns
		RDATA1, RDATA2
Clock setup time	tSL	CLKSR, CLKLA	CLKSR → CLKLA	500			ns
	tLS	CLKSR, CLKLA	CLKLA → CLKSR	500			ns
Clock transition time	tct	CLKSR, CLKLA				200	ns
Data retention time	tDH	LDATA1, LDATA2,		300			ns
		RDATA1, RDATA2

Electirical Characteristics at Ta = ±20 to +75°C, V DD = +5 V ± 10%, VSS = 0 V, VEE = ±4 to ±6 V

Parameter	Symbol		Conditions	min	typ	max	Unit
Input leakage current	IIH	Note (1)	Vin = VDD			5	µA
	IIL	Note (1)	Vin = VSS	±5			µA
High-level output voltage	VOH	LDATA1, LDATA2,	IOH = ±0.4 mA	VDD±0.4			V
		RDATA1, RDATA2
Low-level output voltage	VOL	LDATA1, LDATA2,	IOL = 0.4 mA			0.4	V
		RDATA1, RDATA2
Vi to Yj voltage down	Vd1	Y1 to Y40 Note (2)	Ion = 100 µA, single output			1.1	V
	Vd2	Y1 to Y40 Note (2)	Ion = 50 µA, all outputs			1.5	V
	IVH	V1 to V6	Open output pins			10	µA
Vi quiescent current			Vin = VDD
	IVL	V1 to V6	Open output pins	±10			µA
			Vin = VEE
	IDD	VDD	Open output pins			1.0	mA
Supply current			CLKSR = 400 kHz
	IEE	VEE	Open output pins			10	µA
			M = 1 kHz
Output propagation	tPD	LDATA1, LDATA2,	CL = 15 pF			500	ns
delay time		RDATA1, RDATA2

Note (1): Applied to the pins; CLKSR, CLKLA, LDATA1, RDATA1, LDATA2, RDATA2, M, L/R1, L/R2, CH2-BP (2): The equivalent circuit between Vi to Yj (i = 1 to 6, j = 1 to 40)

No.2778-2/7

LC7930N, 7930NW

Switching Waveforms

Internal Equivalent Circuit

LCD driver (Channel 1)

20-bit latch

20-bit bidirectional shift register

20-bit bidirectional shift register

20-bit latch

LCD driver (Channel 2)

No.2778-3/7